DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Un-der 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/27/2026 has been entered.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
4. Claim(s) 1, is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., US 2006/0278957 A1, in view of Yamaguchi et al., US 2022/0336373 A1.
Claim 1. Lin et al., disclose a semiconductor die (such as the one in fig. 2, item 10), comprising:
-a device region (item 12);
-a dicing region (item 14), laterally surrounding the device region;
-and a seal ring region (item 30), laterally disposed between the device region and the dicing region. However, it is noted that [0020] of Lin disclose the active integrated circuit 18 is surrounded by a typical seal ring structure 30, which is well known as a die seal ring. Such seal ring structure consists of a plurality of patterned metal layers, positioned on top of each other and mutually connected by via or contact plugs. The seal ring structure 30 is common in the art and is utilized to protect the active integrated circuit 18 from being damaged by cracks originating from the wafer dicing process. The seal ring structure 30 may be single seal barrier wall or dual-wall barriers formed in layers of similar or dissimilar dielectric materials 42.
Lin appears to not explicitly indicate the limitation of “wherein the semiconductor die has a wavy edge in a cross- sectional view in the dicing region, wherein the wavy edge is at least defined by a dielectric material and the wavy edge is separated from a seal ring of the seal ring region by the dielectric material”.
However, in a similar package structure, fig. 3, [0033] of Yamaguchi et al., disclose for example, the portion 300 of the semiconductor device 100 may include one or more liners 324a-324d disposed in the grooves 306a and 306h that cover at least a portion of edge surfaces of the dielectric layers 316 and 318 facing the grooves 306a and 306b, respectively. Each of the liners 324a-324d may include a dielectric layer, including silicon nitride (Si3N4) and/or silicon carbide (SiC), for example. The liners 324a and 324b in the groove 306a may cover portions 322a and 322b of edge surfaces of the dielectric layers 316 ad 318 facing the groove 306a. In some embodiments, the portions 322a and 322b may include concave portions in the edge surfaces of the dielectric films 336a-336e facing the groove 306a. Each concave portion of the concave portions in the portions 322a and 322b may correspond to each of the dielectric films 336a-336e between the dielectric layers 340 above and below each dielectric film. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Lin et al., with the feature as taught by Yamaguchi et al., using the structure in FIG. 3 of Yamaguchi et al., would increase performance and density of semiconductor device. As noted further, concave portions in a dielectric hole (via or trench) of a package device are intentionally created in certain manufacturing processes to improve electrical performance, manufacturability, or integration density, rather than being purely a defect.
5. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., US 2019/0131276 A1, in view of Yamaguchi et al., US 2022/0336373 A1.
Claim 7. Chen et al., disclose a package structure (such as the one in fig. 7), comprising:
-a first die (item 100) and a second die (item 200) bonded together (fig. 7, item 30);
-a first encapsulant (item 118), laterally encapsulating the first die;
-and a second encapsulant (item 218), laterally encapsulating the second die, (as noted encapsulants and isolation material are designed to insulate and protect electrical and electronic components).
Chen appears to not explicitly indicate the limitation of “wherein dicing edge of the second die in contact with the second encapsulant is a wavy surface”.
However, in a similar package structure, fig. 3, [0033] of Yamaguchi et al., disclose for example, the portion 300 of the semiconductor device 100 may include one or more liners 324a-324d disposed in the grooves 306a and 306h that cover at least a portion of edge surfaces of the dielectric layers 316 and 318 facing the grooves 306a and 306b, respectively. Each of the liners 324a-324d may include a dielectric layer, including silicon nitride (Si3N4) and/or silicon carbide (SiC), for example. The liners 324a and 324b in the groove 306a may cover portions 322a and 322b of edge surfaces of the dielectric layers 316 ad 318 facing the groove 306a. In some embodiments, the portions 322a and 322b may include concave portions in the edge surfaces of the dielectric films 336a-336e facing the groove 306a. Each concave portion of the concave portions in the portions 322a and 322b may correspond to each of the dielectric films 336a-336e between the dielectric layers 340 above and below each dielectric film. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Chen et al., with the feature as taught by Yamaguchi et al., using the structure in FIG. 3 of Yamaguchi et al., would increase performance and density of semiconductor device. As noted further, concave portions in a dielectric hole (via or trench) of a package device are intentionally created in certain manufacturing processes to improve electrical performance, manufacturability, or integration density, rather than being purely a defect.
Allowable Subject Matter
6. Claims 2-6, 8-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 2 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the wavy edge has at least one wave crest and at least one wave trough connected to each other, wherein the wavy edge is a dicing surface which is physically separated from an adjacent dicing surface of an adjacent semiconductor die by an opening.
(B) Claims 3, 8, contain allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the semiconductor die has four edges and four corners in a top view, and all of the four edges have wavy sides.
(C) Claims 4, 9 contain also allowable subject matter, as depend on Claims 3, 7.
(D) Claim 5 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of further comprising: a substrate; an interconnect structure, disposed over the substrate; the seal ring, embedded in the interconnect structure of the seal ring region; and a bonding structure, disposed over the interconnect structure, wherein the substrate, a dielectric layer of the interconnect structure, and a dielectric layer of the bonding structure together define the wavy edge, and the wavy edge extends from a top surface of the bonding structure to a bottom surface of the substrate, wherein the dicing region between the seal ring region and the wavy edge is free of metal material.
(E) Claim 6, contains also allowable subject matter, as depend on Claim 5.
(F) Claim 10 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the second interface dicing edge of the second die is free of metal material, and the second interface dicing edge of the second die extends from a top surface of the second die to a bottom surface of the second die.
(G) Claim 11 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein dicing edge of the first die in contact with the first encapsulant is a wavy surface in the cross-sectional view.
(H) Claim 12, contains also allowable subject matter, as depend on Claim 11.
(I) Claim 13 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of further comprising: a third die disposed side by side with the second die and disposed over the first die, wherein the second encapsulant laterally encapsulates the third die, and dicing edge of the third die in contact with the second encapsulant is a wavy surface in the cross-sectional view.
(J) Claim 14, contains also allowable subject matter, as depend on Claim 13.
(K) Claim 15 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein a backside of the first die faces a frontside of the second die, and the backside of the first die is bonded onto the frontside of the second die by a metal-to-metal bonding and a dielectric-to-dielectric bonding.
(L) Claim 15 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein a frontside of the first die faces a frontside of the second die, and the frontside of the first die is bonded onto the frontside of the second die by a metal-to-metal bonding and a dielectric-to-dielectric bonding.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights