DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1, 2, 5-6, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by TAKAHASHI et al., US 2008/0277705 A1.
Claims 1, 5-6. TAKAHASHI et al., disclose a semiconductor die (such as the one in fig. 10), comprising:
-a device region (chip region I, fig. 10);
-a dicing region (scribe region II), laterally surrounding the device region;
-and a seal ring region (item SL, fig. 10), laterally disposed between the device region and the dicing region, wherein the semiconductor die has a wavy edge in a cross-sectional view in the dicing region (this limitation would read through in the structure of fig. 10, [0177], wherein is disclosed the regions I.sub.p and II have planar shapes in the form of islands corresponding to each of an electrode pad), wherein the wavy edge is at least defined by a dielectric material (item 54) and the wavy edge is separated from a seal ring of the seal ring region by the dielectric material (this limitation would read through in the structure of fig. 10, [0087], wherein is disclosed the metal laminated film is patterned by photolithography and etching to form first layer metal wirings 41a on the first interlayer insulating film 35 in the circuit forming region IC and the first ring-shaped conductor pattern 41b on the first fence-shaped conductive plug 40c in the peripheral region I.sub.p).
Claim 2. TAKAHASHI et al., disclose the semiconductor die of claim 1, wherein the wavy edge has at least one wave crest and at least one wave trough connected to each other (this limitation would read through in the structure of fig. 10, [0177], wherein is disclosed the regions I.sub.p and II have planar shapes in the form of islands corresponding to each of an electrode pad).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
5. Claim(s) 3-4, is/are rejected under 35 U.S.C. 103 as being unpatentable over TAKAHASHI et al., US 2008/0277705 A1, in view of Kurimoto et al., US 2003/0218254 A1.
Claims 3-4. TAKAHASHI et al., disclose the semiconductor-die of claim 1, above.
TAKAHASHI et al., appear to not specify “wherein the semiconductor die has four edges and four corners in a top view, and all of the four edges have wavy sides”, and “wherein all of the four corners comprise flat sides, are sides, or wavy sides”. However, fig. 1A of Kurimoto et al., shows a chip area outer periphery region, that has four edges and four corners in a top view, and all of the four edges have wavy sides. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device’ structure of TAKAHASHI et al., with the feature as taught by Kurimoto et al., because the structure in FIG. 1A of Kurimoto et al., because a semiconductor die with four edges and four corners (typically rectangular or square) is the industry standard because it maximizes manufacturing efficiency, packaging reliability, and design simplicity. While wafers are circular, cutting them into four-sided dies (or "chips") enables high-density packaging and optimized material usage.
6. Claim(s) 7, 10-13, 15-16, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al., US 2023/0343764 A1.
Claims 7, 11. Chuang et al., disclose a package structure (such as the one in fig. 1F), comprising:
-a first die (item 20) and a second die (item 30) bonded together;
-a first encapsulant (item 22), laterally encapsulating the first die;
-and a second encapsulant (item 38), laterally encapsulating the second die.
Chuang appears to not specify exactly “wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane”. However, [0038] of Chuang indicates that the top-view shapes of the conductive through vias 72 may be circles, rectangles, squares, hexagons, or the like. Further, [0051] discloses the UBMs 92 and the electrical connectors 94 will be referred to as a wafer level package, which may be a composite wafer with a round top-view shape. Therefore, Applicant has not presented persuasive evidence that the claimed shape is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed shape). Also, the applicant has not shown that the claimed shape produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. It has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (in re Aller); similarly, it is not inventive to discover the optimum shape by routine experimentation (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984); MPEP 2144.04).
Claim 10. Chuang et al., disclose the package structure of claim 7, wherein the second interface is free of metal material (this limitation would read through [0019], wherein is disclosed a semiconductor-to-dielectric bonding interface such as silicon-to-nitride (Si—SiN.sub.x) bonding interface may be formed between the bonding dielectric layer 18a and the carrier C1).
Claim 12. Chuang et al., disclose the package structure of claim 11, wherein the first interface is free of metal material (this limitation would read through [0019], wherein is disclosed a semiconductor-to-dielectric bonding interface such as silicon-to-nitride (Si—SiN.sub.x) bonding interface may be formed between the bonding dielectric layer 18a and the carrier C1).
Claim 13. Chuang et al., disclose the package structure of claim 7, further comprising: a third die disposed side by side with the second die and disposed over the first die, wherein the second encapsulant laterally encapsulates the third die, and a third interface of the third die in contact with the second encapsulant is a wavy interface in the cross-sectional plane (this limitation would read through the structure of fig. 1F, items 22, 38 20, 12, 30, 32).
Claim 15. Chuang et al., disclose the package structure of claim 7, wherein a backside of the first die faces a frontside of the second die, and the backside of the first die is bonded onto the frontside of the second die by a metal-to-metal bonding and a dielectric-to-dielectric bonding (this limitation would read through the structure of fig. 1F, [0023], items 26b/36b, and 26a/36a).
Claim 16. Chuang et al., disclose the package structure of claim 7, wherein a frontside of the first die faces a frontside of the second die, and the frontside of the first die is bonded onto the frontside of the second die by a metal-to-metal bonding and a dielectric-to-dielectric bonding. (this limitation would read through the structure of fig. 1F, [0023], items 26b/36b, and 26a/36a).
7. Claim(s) 8-9, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al., US 2023/0343764 A1, in view of Kurimoto et al., US 2003/0218254 A1.
Claims 8-9. Chuang et al., disclose the semiconductor-die of claim 7, above.
Chuang appears to not specify “wherein the semiconductor die has four edges and four corners in a top view, and all of the four edges have wavy sides”, and “wherein all of the four corners comprise flat sides, are sides, or wavy sides”. However, fig. 1A of Kurimoto et al., shows a chip area outer periphery region, that has four edges and four corners in a top view, and all of the four edges have wavy sides.
The Applicant has not presented persuasive evidence that the claimed shape is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed shape). Also, the applicant has not shown that the claimed shape produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. It has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (in re Aller); similarly, it is not inventive to discover the optimum shape by routine experimentation (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984); MPEP 2144.04).
8. Claim(s) 14, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al., US 2023/0343764 A1, in view of Chen et al., US 9,922,964 B1.
Claim 14. Chuang et al., disclose the semiconductor-die of claim 13, above.
Chuang appears to not specify “wherein the third die is a dummy die”.
However, in the same field of endeavor, Chen discloses a package structure includes a dummy die formed over the substrate and adjacent to the device die (see abstract). It would have been prima facie obvious to have practiced well-known techniques from Chuang to fabricate a package structure to incorporate dummy dies as taught by Chen to enhance performance, reliability, and manufacturing efficiency. These dummy dies, which lack active circuitry, serve various purposes, including managing thermal stress, improving mechanical stability, and simplifying packaging processes. They are frequently used in stacked chip configurations or when a uniform surface is needed for subsequent processing steps.
Response to Arguments
9. As to claim 7, Applicant contends that “Chuang does not teach or disclose, for example, the wavy interface as claimed, and the claimed wavy interface can produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art (i.e., Chuang).
This argument is not persuasive. However, [0038] of Chuang indicates that the top-view shapes of the conductive through vias 72 may be circles, rectangles, squares, hexagons, or the like. Further, [0051] discloses the UBMs 92 and the electrical connectors 94 will be referred to as a wafer level package, which may be a composite wafer with a round top-view shape. As noted, a "wavy interface" in the context of devices can refer to two very different concepts depending on whether it describes the physical, structural, or visual (software) aspect of a device. In this case, Applicant does not provide that the claimed shape is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed shape). Also, the applicant has not shown that the claimed shape produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, examiner believe that Chuang meets this limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899