DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 6, 2025 was filed after the mailing date of the Notice of Allowance on September 19, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Prosecution on the merits of this application is reopened on claims 33-35 considered unpatentable for the reasons indicated in the rejection detailed below.
The indicated allowability of claim 33-35 is withdrawn in view of the newly discovered reference to Gardner et al. (US 2022/0102492 A1). Rejections based on the newly cited reference follow.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 33-35 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner et al. (US 2022/0102492 A1).
Regarding claim 33, Gardner et al. teaches a method for manufacturing a semiconductor structure, comprising:
forming a semiconductor stack over a substrate, wherein the semiconductor stack comprises a top first semiconductor material layer, a second semiconductor material layer and a bottom first semiconductor material layer (epitaxial multi-layer stacks (examples N+/intrinsic/P+ or P+/intrinsic/P+) are grown in openings (e.g., first/second/third epi layers shown at FIG. 4 and FIG. 15). See ¶¶[0051]–[0054], ¶¶[0070]–[0072]; FIGs. 4, 15);
forming a mask layer over the semiconductor stack (hardmask and photoresist patterned over the dielectric/epi regions for subsequent etch/patterning. See ¶¶[0048]–[0049], ¶¶[0069]–[0070]; FIGs. 3, 14);
forming a spacer layer adjacent to the mask layer (after the masked etch a ring/sidewall structure (stack of dielectric layers) remains along the epi sidewalls—functionally a spacer/sidewall. See ¶¶[0054]–[0056], ¶¶[0072]–[0073]; FIGs. 5, 16);
removing the mask layer to form an opening, wherein the top first semiconductor material layer is exposed by the opening (mask/photoresist removal followed by exposure of the top S/D epi; selective deposition/processing on the exposed top epi is described (mask removal → selective dielectric / processing on top P+). See ¶¶[0073], ¶¶[0055]–[0056]; FIGs. 6, 17);
replacing the top first semiconductor material layer with a top S/D structure (subsequent silicide/metal formation and interconnect processing create completed S/D structures (silicide layer 3402 and downstream interconnects). See ¶¶[0094]–[0096], ¶¶[0098]–[0100]; FIGs. 34–35);
and removing a portion of the second semiconductor material layer to form a channel layer, wherein the channel layer is below the top of the S/D structure (Gardner teaches “dividing the vertical channel into a lower channel and an upper channel” by forming an isolation that replaces an intermediate layer and “extends through the intrinsic layer of the vertical channel.” That operation necessarily removes/replaces portion(s) of the intrinsic (second) layer and leaves channel material beneath the top S/D. See ¶¶[0025]–[0026], ¶¶[0089]–[0091]; FIG. 30 (division/isolation) and FIGs. 9, 15 (vertical stack showing channel layer below top S/D).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention, because Gardner teaches the overall multi-layer vertical device fabrication flow and discloses the specific operations above. Any remaining details about etch chemistry, exact etch depths, or best-mode ordering are routine process choices or inherent in Gardner’s disclosed flows (Gardner expressly notes manufacturing steps can be performed in any suitable order, ¶[0006]). Selecting process parameters or etch steps to remove a portion of the intrinsic layer to form the shown isolation/channel structure is routine optimization of known result-effective variables and would have been obvious to one of ordinary skill in view of Gardner’s explicit disclosure of dividing the vertical channel by introducing the isolation through the intrinsic layer. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (selection/optimization of process variables obvious absent evidence of criticality).
Regarding claim 34, Garner teaches the method for forming the semiconductor structure as claimed in claim 33, further comprising:
forming a liner layer adjacent to the semiconductor stack (sidewall/liner dielectric rings formed along epi stack sidewalls after mask-and-etch (sidewall structures 502/504, 1602/1604). (¶¶[0054]–[0056], ¶¶[0072]–[0073]; Figs. 5–6, 16);
forming an isolation structure adjacent to the liner layer (3D isolation formed by replacing an intermediate sidewall layer and extending the isolation through the epi (isolation 420/1520/2620). (¶[0057]; ¶¶[0074]–[0075]; ¶¶[0089]–[0091]; Fig. 7, Fig. 18, Fig. 30); and
removing a top portion of the isolation structure to expose the second semiconductor material layer before forming the channel layer (etch-back/removal of selected dielectric layers after isolation to open/expose the intrinsic/channel region, then selective high-k/gate processing (removal of sidewall dielectric to expose channel; high-k deposition). (¶¶[0091]; Fig. 31).
Regarding claim 35, Garner teaches the method for forming the semiconductor structure as claimed in claim 33, further comprising:
removing a portion of the top first semiconductor material layer and a portion of the second semiconductor material layer to form a notch (teaches masked etches, localized etchbacks and selective removal around the top S/D and intrinsic layers (mask removal, selective dielectric deposition, isolation through channel, dielectric removal to open channel) — these steps encompass forming local recesses/notches at the top S/D and adjacent channel. (¶¶[0055]–[0056], ¶[0073], ¶¶[0089]–[0091]; Figs. 6, 17, 30–31); and
forming a top inner spacer layer in the notch, wherein a height of the top inner spacer layer is higher than a height of the top S/D structure (discloses filling openings and gaps with dielectric materials (selective dielectric/high-k depositions, ILD fills, etc.), and shows sidewall/inner dielectric placement around channel/S/D. While Gardner does not verbatim state “inner spacer taller than top S/D,” filling a notch with dielectric (inner spacer) and selecting spacer height relative to adjacent S/D is a routine processing choice in the disclosed flows (dielectric fill, spacer/sidewall engineering). (¶¶[0054]–[0056], ¶¶[0091]; Figs. 5, 31, 34).
Allowable Subject Matter
Claims 16-32 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 16, the claims requires (i) forming the channel layer, top S/D and surrounding gate, and top S/D contact, and then (ii) removing the substrate to form a recess under the already formed channel/top S/D, forming a bottom S/D in that recess beneath the channel, and forming a bottom S/D contact below the bottom S/D. Gardner discloses vertical multi layer epitaxial stacks in which a bottom doped epi (bottom S/D), the intrinsic channel, and the top doped epi (top S/D) are formed by upward epitaxy (see e.g., Gardner ¶¶[0051]–[0054], FIG. 4; ¶¶[0070]–[0072], FIG. 15). Gardner also discloses gate formation around the channel and top side silicide/contacts (¶¶[0058]–[0061]; ¶¶[0094]–[0096]; FIGs. 9, 34–35).
However, Gardner does not disclose or suggest the claimed sequence of fabricating the channel/top S/D/gate and then, as a later distinct step, removing the substrate (backside removal/thinning) to create a recess beneath the already formed channel and subsequently forming a bottom S/D and a bottom contact underneath that bottom S/D. Gardner’s bottom S/D regions are formed by initial epitaxy prior to channel and gate formation, not by later substrate removal and bottom side S/D deposition in a recess. This difference in process sequence and the resulting structural relationship (i.e., forming the bottom S/D after substrate removal beneath an already completed channel/gate stack) is not disclosed by Gardner and is not rendered obvious by Gardner’s teachings.
Regarding claim 26, the claim recites forming the three layer semiconductor stack, replacing the top first semiconductor material layer with a top S/D structure, removing part of the middle (second) layer to form the channel below the top S/D, forming a surrounding gate, and then replacing the bottom first semiconductor material layer with a bottom S/D structure so that the top and bottom S/Ds lie on opposite sidewall surfaces of the channel. Gardner discloses stacked epi S/D–channel–S/D arrangements and conversion of top epi into S/D/contact structures (e.g., selective processing, silicide and interconnects; ¶¶[0051]–[0054], ¶¶[0094]–[0096]; FIGs. 9, 15, 34). Gardner also discloses dividing the vertical channel via an isolation that replaces part of the intermediate layer (¶¶[0025]–[0026]; ¶¶[0089]–[0091]; FIG. 30), and forming gate stacks surrounding the channel (¶¶[0058]–[0061]; FIG. 31).
Critically, however, Gardner’s bottom S/D is provided as an epitaxial doped layer formed during initial stack growth rather than being “replaced” or formed as a distinct bottom S/D replacement step after formation of the top S/D/channel/gate. If claim 26 is given its reasonable meaning that the bottom first semiconductor material layer is later replaced/converted (i.e., a distinct bottom replacement step rather than mere initial epitaxy), Gardner does not disclose or suggest that post channel/gate replacement of the bottom layer. This sequencing and manufacture of the bottom S/D as a later replacement (or as a distinct conversion step performed after channel/gate formation) imposes process and structural differences that Gardner does not teach, and that are not suggested by Gardner’s epitaxial first approach. Because Gardner neither discloses nor renders obvious the claimed post channel/gate replacement of the bottom layer to form a bottom S/D on the opposite side of the channel, claim 26 is allowable over Gardner.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630.
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/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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