DETAILED ACTION
This Office action responds to the application filed on 02/24/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species 3, reading on figure 12, in the reply filed on November 21, 2025 is acknowledged. Applicant cancels claims 1-16, adds claims 21-36, and indicates that claims 17-36 read on the elected species. The examiner disagrees.
The limitations “a first gate pad” & “a second gate pad” recited in claim 27 in lines 2-4 read on elements 1411 & 2411 in figure 1 of non-elected species 1.
The limitation “the first gate structure has a first gate width in the second direction, the second gate structure has a second gate width in the second direction, and each of the first drain pad and the second drain pad has a pad width in the first direction which is not less than each of the first gate width and the second gate width” recited in claim 32 in lines 6-8 reads on figure 7 of non-elected species 2.
The limitations “a first gate pad” & “a second gate pad” recited in claim 33 in lines 10 & 17 read on elements 1411 & 2411 in figure 1 of non-elected species 1.
Although applicant elected claims 28-30 & 34, said claims depend on now-withdrawn claims 27, 32, & 33, and as such, is de facto withdrawn from examination by virtue of dependency to a withdrawn claim. Accordingly, claims 27-30 & 32-34 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claims 17-26, 31, 35, & 36 will be examined in the present Office Action.
Claim Objections
Claim 24 is objected to because of the following informalities:
“a first main unit is disposed on the a front surface of first substrate” in line 4.
In order to further examination, an interpretation of claim 24 is construed as such: “a first main unit is disposed on a front surface of the first substrate.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 32 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 32 recites the limitation "each of the first drain pad and the second drain pad" in line 8. There is insufficient antecedent basis for this limitation in the claim. In order to furth examination, an interpretation of the limitation is construed as such: “each of a first drain pad and a second drain pad”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai (US 20190157333).
Regarding Claim 17, Tsai (see, e.g., fig. 8, annotated figure 8) shows a method for forming a semiconductor structure, comprising:
forming a first device assembly which includes
a first substrate 110 (see, e.g., para.0013),
a first main unit 100 (see, e.g., para.0029) disposed on the first substrate
and including at least one first device 112 (see, e.g., para.0029),
a first dielectric unit 122 & 130 (see, e.g., para.0013, para.0032)
disposed on the first main unit opposite to the first substrate
and having a first interconnecting surface opposite to the first substrate 110 (see, e.g., annotated figure 8),
and a first electrically conductive routing ST1, 124, 140/142 (see, e.g., para.013, para.0032)
which is disposed in the first dielectric unit
and which is electrically connected to the at least one first device (see, e.g., para.0032),
the first electrically conductive routing including
a first end portion 142 which is exposed from the first interconnecting surface (see, e.g., fig. 9, para.0018);
forming a second device assembly which includes a second substrate 210 (see, e.g., para.0030),
a second main unit 200 (see, e.g., para.0030) disposed on the second substrate
and including at least one second device 212,
a second dielectric unit 222 & 230 (see, e.g., para.0013, para.0032)
disposed on the second main unit opposite to the second substrate
and having a second interconnecting surface which is opposite to the second substrate 210 (see, e.g., annotated figure 8),
and a second electrically conductive routing ST2, 224, 240/242 (see, e.g., para.0013, para.0032)
which is disposed in the second dielectric unit
and which is electrically connected to the at least one second device (see, e.g., para.0032),
the second electrically conductive routing including
a second end portion 242 (see, e.g., fig. 9, para.0018) which is exposed from the second interconnecting surface;
and bonding the first interconnecting surface and the second interconnecting surface to each other,
so as to bring the first end portion of the first electrically conductive routing into a direct contact with the second end portion of the second electrically conductive routing (see, e.g., para.0020).
Regarding Claim 18, Tsai (see, e.g., fig. 9, annotated figure 8, para.0019) shows the method of claim 17,
wherein: the first interconnecting surface and the second interconnecting surface are bonded to each other by a dielectric bonding process (see, e.g., fig. 9, annotated figure 8, para.0019);
and the first electrically conductive routing and the second electrically conductive routing are each made of a metal material (see, e.g., para.0019, para.0032)
such that during the dielectric bonding process of the first interconnecting surface and the second interconnecting surface, the first end portion and the second end portion are bonded to each other by a metal bonding process (see, e.g., para.0019).
Regarding Claim 19, Tsai (see, e.g., figs. 1-7) shows the method of claim 17,
wherein formation of the first device assembly and formation of the second device assembly are performed in a parallel manner (see, e.g., figs. 1-7).
Under broadest reasonable interpretation, Examiner can interpret the claim limitation “a parallel manner” to mean either; the steps of formation happen positionally in parallel or the steps of formation happen simultaneously. Tsai (see, e.g., figs. 1-7) shows the formation of the first device assembly and the formation of the second device assembly performed both positionally in parallel and simultaneous. Thus, Tsai anticipates claim 19.
Regarding Claim 20, Tsai (see, e.g., fig. 9, para.0034) shows method of claim 17,
wherein before the first interconnecting surface and the second interconnecting surface are bonded to each other,
the first end portion of the first electrically conductive routing 142 is brought into alignment with the second end portion of the second electrically conductive routing 242 (see, e.g., fig. 9, para.0034)
so as to permit the first end portion to be in direct contact with the second end portion.
Claims 21-26, & 31 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chuang (US 20210358891).
Regarding Claim 21, Chuang (see, e.g., fig. 1, fig. 46, annotated figures 46a-b) a method for forming a semiconductor structure, comprising:
forming a first device assembly (U) (upper half of device 300d, see, e.g., annotated figure 46a) which includes
a first substrate 136 (U) (see, e.g., fig. 46),
a first main unit 200aii (U)
disposed on a front surface of the first substrate (see, e.g., annotated figure 46b)
and including a first dummy portion 92 & 112 (U) (see, e.g., para.0066) and at least one first device (upper nano-fet comprising 100, 102, 54a-c, 90, & 92),
a first dielectric unit 106 & 124 (U) (see, e.g., para.0062, para.0069)
disposed on the first main unit opposite to the first substrate
and having a first interconnecting surface opposite to the first substrate (see, e.g., annotated figure 46b),
and a first electrically conductive routing 112, 114, & 122 (U) (see, e.g., para.0072)
which is disposed in the first dielectric unit
and which is electrically connected to the first main unit (see, e.g., para.0065),
the first electrically conductive routing including a first end portion 122 (U) which is exposed from the first interconnecting surface;
forming a second device assembly which includes
a second substrate 136 (L) (see, e.g., fig. 46),
a second main unit 200aii (L)
disposed on a front surface of the second substrate (see, e.g., annotated figure 46b)
and including a second dummy portion 92 & 112 (L) (see, e.g., para.0066) and at least one second device (lower nano-fet comprising 100, 102, 54a-c, 90, & 92),
a second dielectric unit 106 & 124 (L) (see, e.g., para.0062, para.0069)
disposed on the second main unit opposite to the second substrate
and having a second interconnecting surface which is opposite to the second substrate (see, e.g., annotated figure 46b),
and a second electrically conductive routing 112, 114, & 122 (L) (see, e.g., para.0072)
which is disposed in the second dielectric unit
and which is electrically connected to the second main unit (see, e.g., para.0065),
the second electrically conductive routing including a second end portion 122 (L) which is exposed from the second interconnecting surface;
and bonding the first interconnecting surface and the second interconnecting surface to each other, so as to bring the first end portion of the first electrically conductive routing into a direct contact with the second end portion of the second electrically conductive routing (see, e.g., para.0097).
Chuang labels the various “first” and “second” elements with the same number. Examiner distinguishes between first and second by using the annotations (U) & (L) hereinafter to indicate the upper first device assembly and the lower second device assembly’s elements respectively.
Regarding Claim 22, Chuang (see, e.g., fig. 46) shows the method of claim 21,
wherein the at least one first device includes first devices,
the at least one second device includes second devices,
each of the first devices and the second devices includes
a channel structure 54a-c (see, e.g., para.0055),
a gate structure 100 & 102 (see, e.g., para.0056-0058) which includes
a gate dielectric layer 100 disposed on the channel structure,
and a gate electrode 102 disposed on the gate dielectric layer,
and a source feature and a drain feature 92 (see, e.g., para.0050)which are respectively disposed at two opposite sides of the gate structure such that the channel structure extends between the source feature and the drain feature,
the first end portion of the first electrically conductive routing includes a first interconnecting pad 122 (U),
the second end portion of the second electrically conductive routing includes a second interconnecting pad 122 (L),
the first electrically conductive routing further includes
a connecting via 112 (U) (see, e.g., para.0075) which is disposed in a manner such that the first interconnecting pad 122 (U) is electrically connected to the first dummy portion by the connecting via,
and first active vias 114 (U) which are disposed in a manner such that the interconnecting pad is electrically connected to the first devices respectively through the first active vias (see, e.g., para.0072),
the second electrically conductive routing further includes
second active vias 112 (L) which are disposed in a manner such that the second interconnecting pad is electrically connected to the second devices respectively through the second active vias (see, e.g., para.0072),
and the method further comprises:
forming an input via 130 (see, e.g., para.0085) which extends from a back surface of the first substrate (see, e.g., annotated figure 46b) into the first substrate so as to reach the first dummy portion,
such that after the first interconnecting surface and the second interconnecting surface are bonded to each other (see, e.g., para.0097),
the first interconnecting pad and the second interconnecting pad are in direct contact with each other so as to permit an input signal from the input via to be transmitted to the first devices and the second device (see, e.g., para.0092),
the back surface of the first substrate being opposite to the front surface of the first substrate (see, e.g., annotated figure 46b).
Regarding Claim 23, Chuang (see, e.g., fig. 46) shows the method of claim 22,
wherein the input via 130 extends to reach an electrically conductive portion of the first dummy portion 92 (see, e.g., para.0066),
the connecting via extends to reach the electrically conductive portion of the first dummy portion,
each of the first active vias is electrically connected to one of the gate electrode, the drain feature and the source feature of a corresponding one of the first devices,
and each of the second active vias is electrically connected to one of the gate electrode, the drain feature and the source feature of a corresponding one of the second devices.
Regarding Claim 24, Chuang (see, e.g., fig. 1, fig. 46, annotated figure 46a) shows a method for forming a semiconductor structure, comprising:
forming a first device assembly (U) (upper half of device 300d, see, e.g., annotated figure 46a) which includes
a first substrate 136 (U) (see, e.g., fig. 46),
a first main unit 200aii (U) disposed on a front surface of the first substrate and including at least one first device (upper nano-fet comprising 100, 102, 54a-c, 90, & 92),
a first dielectric unit 106 & 124 (U) (see, e.g., para.0062, para.0069) disposed on the first main unit opposite to the first substrate and having a first interconnecting surface opposite to the first substrate (bottom surface of 120, see, e.g., annotated figure 46a),
and a first electrically conductive routing 112, 114, & 122 (U) (see, e.g., para.0072) which is disposed in the first dielectric unit and which is electrically connected to the at least one first device (see, e.g., para.0065),
the first electrically conductive routing including a first end portion 122 (U) which is exposed from the first interconnecting surface;
forming a second device assembly (L) (lower half of device 300d, see, e.g., annotated figure 46a) which includes
a second substrate 136 (L) (see, e.g., fig. 46),
a second main unit 200aii (L) disposed on a front surface of the second substrate and including at least one second device (lower nano-fet comprising 100, 102, 54a-c, 90, & 92),
a second dielectric unit 106 & 124 (L) (see, e.g., para.0062, para.0069) disposed on the second main unit opposite to the second substrate and having a second interconnecting surface which is opposite to the second substrate (upper surface of 120, see, e.g., annotated figure 46a),
and a second electrically conductive routing 112, 114, & 122 (L) (see, e.g., para.0072) which is disposed in the second dielectric unit and which is electrically connected to the at least one second device (see, e.g., para.0065),
the second electrically conductive routing including a second end portion 122 (L) which is exposed from the second interconnecting surface;
aligning the first dielectric unit and the second dielectric unit with each other such that the first end portion and the second end portion are aligned with each other (see, e.g., para.0097, fig. 46);
and performing a hybrid bonding process such that
the first dielectric unit and the second dielectric unit are bonded to each other and the first end portion and the second end portion are bonded to each other (see, e.g., para.0097),
the first electrically conductive routing and the second electrically conductive routing being located between the first main unit and the second main unit (see, e.g., fig. 46).
Chuang labels the various “first” and “second” elements with the same number. Examiner distinguishes between first and second by using the annotations (U) & (L) hereinafter to indicate the upper first device assembly and the lower second device assembly’s elements respectively.
Regarding Claim 25, Chuang (see, e.g., annotated figure 46a) shows the method of claim 24,
wherein after the bonding process, the first end portion of the first electrically conductive routing 122 (U) overlaps with the second end portion of the second electrically conductive routing 122 (L).
Regarding Claim 26, Chuang (see, e.g., fig. 46) shows the method of claim 24,
wherein the at least one first device includes
a first channel structure 54a-c (U) (see, e.g., para.0055),
a first gate structure 100 & 102 (U) (see, e.g., para.0056-0058) which is disposed on the first channel structure,
and which includes a first gate electrode 102 (U) and a first gate dielectric layer 100 (U) disposed between the first gate electrode and the first channel structure,
and a first source feature and a first drain feature 92 (U) (see, e.g., para.0050) which are respectively disposed at two opposite sides of the first gate structure such that the first channel structure extends between the first source feature and the first drain feature (see, e.g., fig. 46),
and the at least one second device includes
a second channel structure 54a-c (U) (see, e.g., para.0055),
a second gate structure 100 & 102 (L) (see, e.g., para.0056-0058) which is disposed on the second channel structure,
and which includes a second gate electrode and a second gate dielectric layer disposed between the second gate electrode and the second channel structure,
and a second source feature 92 (L) and a second drain feature 92 (L) (see, e.g., para.0050) which are respectively disposed at two opposite sides of the second gate structure such that the second channel structure extends between the second source feature and the second drain feature (see, e.g., fig. 46).
Regarding Claim 31, Chuang (see, e.g., annotated figure 46b) shows the method of claim 26,
wherein after the bonding process,
the first gate electrode 102 (U) is in alignment with the second gate electrode 102 (L) in a first direction (vertical direction) normal to the front surface of the first substrate 136 (U) and the front surface of the second substrate 136 (L),
the first drain feature 92 (U) being in alignment with the second source feature 92 (L) in the first direction (vertical direction),
the first source feature 92 (U) being in alignment with the second drain feature 92 (L) in the first direction (vertical direction).
Allowable Subject Matter
Claims 35 & 36 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814