DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/174,293, application filed on 02/24/2023 and Preliminary Amendment subsequently filed on 02/24/2023.
3. In the Preliminary Amendment, claims 1-18 are cancelled by Applicant, and claims 22, 24-28, 32 and 34-38 are amended by Applicant. Claims 19-38 are currently pending in this application.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 04/12/2023 and 04/12/2023, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 19-38 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Song et al. (US PG Pub No. 2016/0335384).
7. With respect to independent claims 19 and 29, Song teaches:
generating a transfer function (pattern transferred to material under photo-resist, para 22; pattern transfer process, para 23; computational lithography, targeted/re-targeted patterns, modifying re-targeted patterns in pattern transfer, para 5; objective function for pattern transfer, para 26; computational process and function for etch lithography improvement, para 41) that relates segments on lithography photomasks to features produced by photolithography and etching using said segments (see segments in post-development patterns and post-etch patterns, computing improvements to etch, modifying etch process in computational lithography, para 37), the method comprising:
(a) receiving after development inspection metrology results (see post development patterns 106, Fig 1, para 28) produced from one or more first test substrates on which resist was applied and patterned using a set of design layout segments (see post-development patterns transferred to substrate, para 29; post-development resist profile data, para 29-30; see test patterns 102 which lead to post-development patterns 106 as shown in Fig 1; see segments in post-development patterns and post-etch patterns, computing improvements to etch, modifying etch process in computational lithography, para 37);
(b) receiving after etch inspection metrology results produced from one or more second test substrates which were etched after resist was applied and patterned using said set of design layout segments (see post-etch patterns 110 in second set of substrates which stem from test patterns 102, as shown in Fig 1, para 29-30; see post-development resist profile data, see post etch CD data, Fig 1, para 25-32; see segments in post-development patterns and post-etch patterns, computing improvements to etch, modifying etch process in computational lithography, para 37); and
(c) generating the transfer function using the set of design layout segments together with corresponding after development inspection metrology results and corresponding after etch inspection metrology results (calibrating 3D resist profiles for aware etch-bias model for improved transfer of patterns to substrate, Fig 1, 132, para 32-37; pattern transferred to material under photo-resist, para 22; pattern transfer process, para 23; computational lithography, targeted/re-targeted patterns, modifying re-targeted patterns in pattern transfer, para 5; objective function for pattern transfer, para 26; computational process and function for etch lithography improvement, para 41; see segments in post-development patterns and post-etch patterns, computing improvements to etch, modifying etch process in computational lithography, para 37).
8. With respect to claims 20 and 30, Song teaches:
calibrating a computational resist model using the after development inspection metrology results (calibrating 3D resist profiles for aware etch-bias model for improved transfer of patterns to substrate, Fig 1, 132, para 32-37; pattern transferred to material under photo-resist, para 22; pattern transfer process, para 23).
9. With respect to claims 21 and 31, Song teaches:
wherein generating the transfer function comprises running the computational resist model multiple times to provide a set of predicted after development resist profiles (computational lithography process using resist model, fitting parameters until uncalibrated model matches CD of resist profile predicted by 3D lithography model, para 30).
10. With respect to claims 22 and 32, Song teaches:
calibrating a computational etch model using the after etch inspection metrology results (calibrating 3D resist profiles for aware etch-bias model for improved transfer of patterns to substrate, Fig 1, 132, para 32-37; pattern transferred to material under photo-resist, para 22; pattern transfer process, para 23).
11. With respect to claims 23 and 33, Song teaches:
wherein generating the transfer function comprises running the computational etch model multiple times to provide a set of predicted etch feature profiles (computational lithography process using resist model, fitting parameters until uncalibrated model matches CD of resist profile predicted by 3D lithography model, para 30).
12. With respect to claims 24 and 34, Song teaches:
wherein the after development inspection metrology results and/or the after etch inspection metrology results are provided in three dimensions (see 3D resist-profile and post-etch/etch-bias model, Fig 1, 132, para 22-36).
13. With respect to claims 25 and 35, Song teaches:
wherein the after development inspection metrology results and/or the after etch inspection metrology results are provided as x-y contours using CD-SEM (see x-y 2D contours, para 24; see use of SEM/TEM on wafer, para 28).
14. With respect to claims 26 and 36, Song teaches:
wherein the after development inspection metrology results and/or the after etch inspection metrology results are provided as x-z profiles using a TEM or CD-SAXS technique (see x-y 2D contours, para 24; see use of SEM/TEM on wafer, para 28).
15. With respect to claims 27 and 37, Song teaches:
wherein the set of design layout segments includes clips or gauges provided in a GDS format (see layout segments, para 37-38; see format for data for lithography improvement, para 24-26, 34-36).
16. With respect to claims 28 and 38, Song teaches:
applying an inverse of the transfer function to determine a design layout for a lithography mask (see inverse data, inverse of predicted values to optimize CDs of patterns, para 42).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851