DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species 4 (claims 9-11, 15-24, and 26-32) in the reply filed on March 24, 2026 is acknowledged.
Information Disclosure Statement
The references cited within the IDS document (dated June 20, 2024) have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9, 10, 29, 11, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo (US 8,652,931 B1).
As to claim 9, Luo teaches a method (see figures 1-6), comprising:
providing a semiconductor substrate (see figure 1; see column 4, lines 12 et seq.) having a first region (right side of substrate) and a second region (left side of substrate) separated from the first region;
performing an ion implantation process (see figure 2) to selectively form a doped layer in the first region;
performing a first etching process (figure 5) to selectively remove the doped layer;
performing a second etching process (figure 6) to remove portions of the semiconductor substrate in the first region and the second region, wherein at least one of the first etching process and the second etching process forms a first trench (120) having a first depth in the first region and a second trench (110) having a second depth in the second region, wherein the first depth is greater than the second depth (shown in figure 6); and
forming a first isolation structure to fill the first trench and a second isolation structure to fill the second trench (see column 6, lines 18 et seq.).
As to claim 10, Luo teaches forming a hard mask layer (3, SiN) over the semiconductor substrate before (figure 1) performing the ion implantation process (figure 2).
As to claim 29, Luo teaches patterning the hard mask layer (see figures 4 and 5) to form a first opening in the first region and a second opening in the second region.
As to claim 11, Luo teaches the first etching process (figure 5) is performed before performing the second etching process (figure 6).
As to claim 15, Luo teaches performing the ion implantation process includes doping the semiconductor substrate with an n-type dopant (column 4, lines 34 et seq.).
As to claim 16, Luo teaches performing the first etching process includes applying an etchant that includes bromine (i.e. HBr, see column 5, lines 42-60).
Claims 21, 22, and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liang (US 5,776,817).
As to claim 21, Liang teaches a method (see figures 2A-2I), comprising:
providing a semiconductor substrate (200) having a first region and a second region (see annotated figure below) separated from the first region;
performing one or more etching processes (see figures 2B, 2D, 2G) to form a first trench having a first depth in the first region and a second trench having a second depth in the second region, the first depth being greater than the second depth (see e.g. figure 2G); and
forming a first isolation structure (208) in the first trench (207a) and a second isolation structure (208) in the second trench (207b), wherein the first isolation structure has the first depth and the second isolation structure has the second depth.
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As to claim 22, Liang teaches performing an ion implantation process to selectively form a doped layer (210) in the first region. See also column 3, line 63 et seq.
As to claim 28, Liang teaches performing the ion implantation process comprises doping the semiconductor substrate with an n-type dopant. See also column 3, line 63 et seq.
Claims 21, 22, and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 2009/0302413 A1).
As to claim 21, Kang teaches a method (see figures 2A-2G), comprising:
providing a semiconductor substrate (201) having a first region (HV region) and a second region (LV region) separated from the first region;
performing one or more etching processes (see e.g. figures 2C and 2G) to form a first trench (215) having a first depth in the first region and a second trench (216) having a second depth in the second region, the first depth being greater than the second depth (see figure 2G); and
forming a first isolation structure in the first trench and a second isolation structure in the second trench (see paragraphs 0019-0020), wherein the first isolation structure has the first depth and the second isolation structure has the second depth.
As to claim 22, Kang teaches performing an ion implantation process (figure 2E) to selectively form a doped layer (213) in the first region.
As to claim 28, Liang teaches performing the ion implantation process comprises doping the semiconductor substrate with an n-type dopant (see paragraph 0018).
Allowable Subject Matter
Claims 17-20 are allowable.
The following is an examiner’s statement of reasons for allowability.
The prior art of record does not teach or suggest the disclosed invention regarding a method, particularly characterized by comprising the steps of:
performing a dry etching process to form a first trench and a second trench separated from one another in a substrate, the first trench and the second trench each having a first depth;
performing an ion implantation process to a bottom portion of the first trench;
performing a chemical etching process to selectively extend the first trench to a second depth that is greater than the first depth, as recited within claim 17.
Claims 18-20 depend from claim 17.
Claims 23, 26, and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not teach or suggest the disclosed invention regarding wherein the one or more etching processes comprise: a first etching process to selectively remove the doped layer; and a second etching process to remove portions of the semiconductor substrate in the first region and the second region, as recited in claim 23.
The prior art of record does not teach or suggest the disclosed invention regarding forming a hard mask layer over the semiconductor substrate before performing the ion implantation process, as recited in claim 26.
The prior art of record does not teach or suggest the disclosed invention regarding forming a patterned mask layer to fill the second opening, such that the ion implantation process is performed on the semiconductor substrate through the first opening, as recited in claim 30.
Claims 24, 27, 31, and 32 are also objected to as being dependent upon objected claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
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/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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