Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 05/13/2026. Currently, claims 10-24 and 26-29 are pending in the application. Claims 1-9 and 25 have been cancelled from consideration.
Claim Objections
Claim 21 is objected to because of the following informalities: Where it recites “forming, through the first opening, a second opening in the barrier layer” in line 8 should be “forming, through a first opening, a second opening in the barrier layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-14, 17, 21-24 and 29 are rejected under 35 U.S.C. 103 as being obvious over LEI et al (US 20220140096 A1) in view of Saunier et al (US 20140001478 A1).
Regarding claim 10, Figure 2 of LEI discloses a process for manufacturing a HEMT device, comprising:
forming a source region (106, [0028]) and a drain region (108, [0028]) each extending into a heterostructure including a channel layer (104, [0029]) and a barrier layer (114, [0029]) on the channel layer;
forming, on the barrier layer of the heterostructure, an insulation layer (116, [0031]) having a vertical thickness and covering the source region and the drain region;
forming a first opening (in 116) in the insulating layer exposing a top surface of the barrier layer (114);
forming, through the first opening, a second opening (in 114, Figure 2B) in the barrier layer, the first opening having a first width, the second opening having a second width less than the first width; and
forming a gate region (110), wherein the gate region includes a first portion in first opening extending through the insulation layer, and having the first width, and a second portion extending partially into the barrier layer (114) in the second opening and having the second width.
LEI does not teach that the second opening (in 114) in the barrier layer extending partially through a thickness of the barrier layer without exposing the channel layer (104).
However, Saunier is a pertinent art which teaches a HEMT device in Figures 1-2, wherein Figure 1 of Saunier teach that the gate electrode does not completely penetrates a barrier layer 106 without reaching a channel layer 104, wherein the thickness T may be configured to inhibit formation of the 2DEG at a gate region of the channel disposed between a gate terminal (hereinafter "gate 118") and the buffer layer 104 while allowing 2DEG formation to occur in access regions of the channel between the gate region and the source 112 and drain 114. In some embodiments, a thickness and/or aluminum content of the barrier layer 106 may be selected to ensure that all of the 2DEG in the gate region is removed for an IC device 100 that is either a Schottky gate device or a MIS gate device. In other embodiments, the IC device 100 may be a Depletion-mode (D-mode) device, which uses a negative gate voltage with respect to source voltage in order to pinch-off current flow in the IC device 100 ([0025]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the process for manufacturing a HEMT device of LEI such that the second opening (in 114) in the barrier layer extending partially through a thickness of the barrier layer without exposing the channel layer (104) for forming the gate without reaching to channel layer according to the teaching of Saunier for forming a Depletion-mode (D-mode) device ([0025] of Saunier).
Regarding claim 11, Figure 2 of LEI discloses that the manufacturing process according to claim 10, wherein forming the gate region (110) includes: forming a window (trench in Figure 2B) in the insulation layer (116); forming a recess (opening in 114) in the heterostructure, at the window; and depositing at least one conductive layer (110, [0033]) in the window.
Regarding claim 12, Figure 2 of LEI discloses that the manufacturing process according to claim 10, wherein the heterostructure includes a channel layer (104) and a barrier layer (114) on the channel layer, the insulation layer (116) being positioned on the barrier layer, the second portion (bottom region of 110) of the gate region extending in the barrier layer (114).
Regarding claim 13, Figure 2 of LEI discloses that the manufacturing process according to claim 12, wherein the second portion (bottom portion) of the gate region (recess shown in the Figure 2B) extends partially through the barrier layer (114, [0033]) and ends in the barrier layer.
Regarding claim 14, Figure 2 of LEI discloses that the manufacturing process according to claim 12, wherein the width of the first portion (lower portion in 114) of the gate region (recess region in 114and 116) is greater than the width of the second portion (upper portion in 116) of the gate region.
Regarding claim 17, Figure 2 of LEI discloses a method, comprising:
forming a heterostructure of an HEMT device including a channel layer (104, [0028]) and a barrier layer (114, [0028]) on the channel layer;
forming a source region (106, [0028]) and a drain region (108, [0028]) extending into the heterostructure;
depositing an insulating layer (116, [0032]) on the barrier layer and over the source region and the drain region;
forming a first opening (in Figure 2B) in the insulating layer between the source region and the drain region and exposing the a top surface of the barrier layer (114);
forming, through the first opening in the insulating layer, a second opening (bottom portion of the opening in 114 is 114) in the barrier layer, the first opening having a first width, the second opening having a second width smaller than the first width; and
forming a gate electrode (110, [0034]) having a first portion in the first opening extending through the insulation layer (116) and having the first width, a second portion extending partially into the barrier layer (114) in the second opening and having the second width, and a third portion (upper portion of 110) on a top surface of the insulating layer.
LEI does not teach that the second opening (in 114) in the barrier layer extending partially through a thickness of the barrier layer without exposing the channel layer (104).
However, Saunier is a pertinent art which teaches a HEMT device in Figures 1-2, wherein Figure 1 of Saunier teach that the gate electrode does not completely penetrates a barrier layer 106 without reaching a channel layer 104, wherein the thickness T may be configured to inhibit formation of the 2DEG at a gate region of the channel disposed between a gate terminal (hereinafter "gate 118") and the buffer layer 104 while allowing 2DEG formation to occur in access regions of the channel between the gate region and the source 112 and drain 114. In some embodiments, a thickness and/or aluminum content of the barrier layer 106 may be selected to ensure that all of the 2DEG in the gate region is removed for an IC device 100 that is either a Schottky gate device or a MIS gate device. In other embodiments, the IC device 100 may be a Depletion-mode (D-mode) device, which uses a negative gate voltage with respect to source voltage in order to pinch-off current flow in the IC device 100 ([0025]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the process for manufacturing a HEMT device of LEI such that the second opening (in 114) in the barrier layer extending partially through a thickness of the barrier layer without exposing the channel layer (104) for forming the gate without reaching to channel layer according to the teaching of Saunier for forming a Depletion-mode (D-mode) device ([0025] of Saunier).
Regarding claim 21, Figure 2 of LEI discloses a method of forming an HEMT device, comprising:
forming a channel layer (104, [0028]);
forming a barrier layer (114, [0028]) on the channel layer;
forming a source region (106, [0030]) extending through the barrier layer;
forming a drain region (108, [0030]) extending into the barrier layer;
forming, on the barrier layer, an insulation layer (116, [0032]) and covering the source region and the drain region;
forming, through a first opening (in 116), a second opening (in 114) in the barrier layer, the first opening having a first width, the second opening having a second width less than the first width;
forming a gate region (110, [0034]) including a first portion in the first opening extending through the insulation layer on a top surface of the barrier layer and having the first width and a second portion extending partially into the barrier layer in the second opening and having the second width.
LEI does not teach that the second opening (in 114) in the barrier layer extending partially through a thickness of the barrier layer without exposing the channel layer (104).
However, Saunier is a pertinent art which teaches a HEMT device in Figures 1-2, wherein Figure 1 of Saunier teach that the gate electrode does not completely penetrates a barrier layer 106 without reaching a channel layer 104, wherein the thickness T may be configured to inhibit formation of the 2DEG at a gate region of the channel disposed between a gate terminal (hereinafter "gate 118") and the buffer layer 104 while allowing 2DEG formation to occur in access regions of the channel between the gate region and the source 112 and drain 114. In some embodiments, a thickness and/or aluminum content of the barrier layer 106 may be selected to ensure that all of the 2DEG in the gate region is removed for an IC device 100 that is either a Schottky gate device or a MIS gate device. In other embodiments, the IC device 100 may be a Depletion-mode (D-mode) device, which uses a negative gate voltage with respect to source voltage in order to pinch-off current flow in the IC device 100 ([0025]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the process for manufacturing a HEMT device of LEI such that the second opening (in 114) in the barrier layer extending partially through a thickness of the barrier layer without exposing the channel layer (104) for forming the gate without reaching to channel layer according to the teaching of Saunier for forming a Depletion-mode (D-mode) device ([0025] of Saunier).
Regarding claim 22, Figure 2 of LEI discloses that the method of claim 21, wherein the insulation layer (116) has a thickness along a second direction and covering the source region (106) and the drain region (108, [0032]).
Regarding claim 23, Figure 2 of LEI discloses that the method of claim 22, wherein the first portion (top portion of the opening in 116 in the Figure 2B) of the gate region is surrounded by the insulation layer (116, [0031]).
Regarding claim 24, Figure 2 of LEI discloses that the method of claim 23, wherein the second portion (bottom portion of the opening in 114) of the gate region extends partially through the barrier layer (114, [0029]) and ends in the barrier layer.
Regarding claim 29, Figure 2 of LEI discloses that the method of claim 23, wherein the gate region includes an insulating layer (112, [0028]) and a conductive layer (110, [0030]), the insulating layer extending between the heterostructure and the conductive layer.
Claims 15-16, 18-20 and 26-28 are rejected under 35 U.S.C. 103 as being obvious over LEI et al (US 20220140096 A1) in view of Saunier et al (US 20140001478 A1), and further in view of Sheppard et al (US 20130252386 A1).
Regarding claims 15-16, 20 and 26-28, Figure 2 of LEI does not teach that the manufacturing process according to claim 12, wherein the barrier layer includes a first barrier portion of a first material and a second barrier portion of a second material different from the first material, the first barrier portion extending between the channel layer and the second barrier portion, wherein the second portion of the gate region extends in the second barrier portion up to an interface between the first barrier portion and the second barrier portion. Or
The method of claim 17, wherein barrier layer has a first sub-layer and a second sub-layer, wherein forming the second opening includes etching through the second sub-layer and utilizing the first sub-layer as an etch-stop. Or
The method of claim 23, wherein the barrier layer includes a first barrier portion of a first material and a second barrier portion of a second material different from the first material, the first barrier portion extending between the channel layer and the second barrier portion, wherein the second portion of the gate region extends in the second barrier portion up to an interface between the first barrier portion and the second barrier portion. Or
The method of claim 23, wherein the gate region includes conductive material in direct electrical contact with the barrier layer.
However, Sheppard is a pertinent art which teaches semiconductor devices and in particular relates to transistors, such as high electron mobility transistors (HEMT), that incorporate nitride-based active layers and a recessed gate structure, and methods of fabricating same. Sheppard teaches that cap layer (second barrier layer, 24 Figures 3-4) on a first barrier layer (22) to achieve high breakdown voltage and protecting the barrier layer during etching ([0010] and [0055]-[0056]). Sheppard, further, teaches that the gate (32) of the device can be in contact with the first buffer layer (22) ([0051] and [0055]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of LEI according to the teaching of Sheppard as claimed above in order to a HEMT with high breakdown voltage and schottky contact HEMT device and protecting the barrier layer from damage during fabrication ([0010]-[0011] of LEI).
Regarding claims 18-19, Figure 2 of LEI does not teach that the method of claim 17, wherein forming the second opening includes: forming a mask layer on the insulating layer and in the first opening; patterning the mask layer to expose a portion of the heterostructure in the first opening; and forming the second opening by etching the exposed portion of the heterostructure, and comprising forming the gate electrode after removing the mask layer.
However, Sheppard is a pertinent art which teaches semiconductor devices and in particular relates to transistors, such as high electron mobility transistors (HEMT), that incorporate nitride-based active layers and a recessed gate structure, and methods of fabricating same. Figures 1A-1H of Sheppard teach of forming a mask layer (42) on dielectric layers (26/28) and patterning the mask layer to expose a portion of the heterostructure (22+20) in the opening; and forming the trench (36) by etching the exposed portion of the heterostructure, comprising forming the gate electrode (32) after removing the mask layer in method of forming the HEMT with improved method for high breakdown voltage and protecting the layers from etching ([0010]-[0011]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of LEI according to the teaching of Sheppard as claimed above in order to a HEMT with high breakdown voltage and a schottky contact HEMT device, and protecting the barrier layer from damage during fabrication ([0010]-[0011] of LEI).
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claims 10-24 and 26-29, filed on 05/13/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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