DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 April 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Nuotio (US Publication 20230068223) in view of Chew et al (US Publication 20220415857).
Regarding claim 1, Nuotio teaches a microelectronic package comprising:
an upper direct bonded metal (DBM) substrate (Fig. 4, 41, para 30);
a lower DBM substrate aligned with and spaced apart from the upper DBM substrate (Fig. 4, 44, para 30), the lower DBM substrate and the upper DBM substrate defining an interior of the microelectronic package between the lower DBM substrate and the upper DBM substrate (Fig. 4, package 10 with substrate 41 and 44 including elements between them),
an upper set of dies coupled the upper DBM substrate in the interior of the microelectronic package (para 40, Fig. 4, 130, Fig. 5 130 with multiple dies 200);
a lower set of dies coupled to the lower DBM substrate in the interior of the microelectronic package (para 47, Fig. 4, 110, Fig. 6 110 with multiple dies 200); and
Nuotio does not specifically teach:
a lead frame extending from outside the interior of the microelectronic package to inside the interior of the microelectronic package; the lead frame including:
a signal tab being a unibody metal structure that includes a tab extending from the interior of the microelectronic package, a plurality of upward clips bent towards the upper DBM substrate, and a plurality of downward clips bent towards the lower DBM substrate, wherein the plurality of upward clips are coupled to the upper set of dies and [[a]]the plurality of downward clips are coupled to the lower set of dies; and
an output tab having a bidirectional clip coupled to the upper DBM substrate and the lower DBM substrate.
It is noted that the primary limitation not specifically taught by Nuotio is the lead frame including a signal tab being a unibody metal structure interpreted as the lead frame also having a unibody structure.
Chew teaches:
a lead frame extending from outside the interior of the microelectronic package to inside the interior of the microelectronic package (Fig. 20, lead frame 122); the lead frame including:
a signal tab being a unibody metal structure (Fig. 20, 128 known in the field of endeavor to be a metal structure) that includes a tab extending from the interior of the microelectronic package (Fig. 20, leads 128), a plurality of upward clips bent towards the upper DBM substrate (Fig. 20, 134 and 136), and a plurality of downward clips bent towards the lower DBM substrate (Fig. 20, 146 and 148), wherein the plurality of upward clips are coupled to the upper set of dies (Fig. 20, 134 and 136 coupled to 130 and 132) and [[a]]the plurality of downward clips are coupled to the lower set of dies (Fig. 20, 146 and 148 coupled to 142 and 144); and
an output tab having a bidirectional clip coupled to the upper DBM substrate and the lower DBM substrate (Fig. 20, leads 128 with spacers 138 and 140 coupling substrates 124 and 126, para 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Nuotio to include the lead frame and associated clips as taught by chew since they are both from the same field of endeavor and in order to improve the operability and reliability of the device.
Regarding claim 2, Nuotio as modified teaches the limitations of claim 1 upon which claim 2 depends.
Nuotio does not specifically teach wherein the plurality of upward clips and the plurality of downward clips are configured to space the upper DBM substrate and the lower DBM substrate substantially equally on either side of the signal tab so that the signal tab approximately bisects the interior of the microelectronic package.
Chew teaches wherein the plurality of upward clips and the plurality of downward clips are configured to space the upper DBM substrate and the lower DBM substrate substantially equally on either side of the signal tab so that the signal tab approximately bisects the interior of the microelectronic package (Fig. 20, 134/136 and 146/148 space 126 and 124 equally on either side of 128).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Nuotio to include the lead frame and associated clips as taught by chew since they are both from the same field of endeavor and in order to improve the operability and reliability of the device.
Regarding claim 3, Nuotio as modified teaches the limitations of claim 1 upon which claim 3 depends.
Nuotio teaches wherein the upper set of dies and the lower set of dies are substantially identical metal oxide semiconductor field effect transistors (para 25, die 200 MOSFET).
Regarding claim 4, Nuotio as modified teaches the limitations of claim 3 upon which claim 4 depends.
Nuotio teaches wherein the substantially identical metal oxide semiconductor field effect transistors are silicon carbide (SiC) (para 26, silicon carbide)
Regarding claim 5, Nuotio as modified teaches the limitations of claim 1 upon which claim 5 depends.
Nuotio teaches wherein: the upper set of dies is an upper set of transistor-dies (Fig. 4, dies 200, para 25, MOSFET); the lower set of dies is a lower set of transistor-dies (Fig. 4, dies 200, para 25, MOSFET); the upper DBM substrate includes an upper high-side conductor and an upper low-side conductor, which are electrically isolated by an upper gap (Fig. 5, 520 and 510 separated by gap); and the lower DBM substrate includes a lower high-side conductor and a lower low-side conductor that are electrically isolated by a lower gap (Fig. 6, 620 and 610 separated by gap).
Regarding claim 6, Nuotio as modified teaches the limitations of claim 5 upon which claim 6 depends.
Nuotio teaches wherein: the upper set of transistor-dies are transistor dies of a low-side transistor and are coupled to the upper DBM substrate by sinter or solder connections between drain pads and the upper low-side conductor of the upper DBM substrate; and the lower set of transistor-dies are transistor dies of the low-side transistor and are coupled to the lower DBM substrate by sinter or solder connections between drain pads and the lower low-side conductor of the lower DBM substrate (para 33, bonding layers 450a and 450b for plurality of transistors 400a and 400b, Fig. 4).
Regarding claim 7, Nuotio as modified teaches the limitations of claim 5 upon which claim 7 depends.
Nuotio teaches wherein: the upper set of transistor-dies are transistor dies of a high-side transistor and are coupled to the upper DBM substrate by sinter or solder connections between drain pads and the upper high-side conductor of the upper DBM substrate; and the lower set of transistor-dies are transistor dies of the high-side transistor and are coupled to the lower DBM substrate by sinter or solder connections between drain pads and the lower high-side conductor of the lower DBM substrate (para 33, bonding layers 450a and 450b for plurality of transistors 400a and 400b, Fig. 4).
Regarding claim 8, Nuotio as modified teaches the limitations of claim 5 upon which claim 8 depends.
Nuotio teaches wherein the bidirectional clip is soldered between the upper low-side conductor and the lower low-side conductor (para 58, external busbars with welding bond).
Regarding claim 9, Nuotio as modified teaches the limitations of claim 8 upon which claim 9 depends.
Nuotio does not specifically teach wherein the bidirectional clip is a first bidirectional clip and the lead frame further includes: a power tab having a second bidirectional clip that is soldered between the upper high-side conductor and the lower high-side conductor, wherein the first bidirectional clip and the second bidirectional clip are configured to space the upper DBM substrate and the lower DBM substrate apart to define the interior of the microelectronic package between the lower DBM substrate and the upper DBM substrate.
Chew teaches wherein the bidirectional clip is a first bidirectional clip and the lead frame further includes: a power tab having a second bidirectional clip that is soldered between the upper high-side conductor and the lower high-side conductor, wherein the first bidirectional clip and the second bidirectional clip are configured to space the upper DBM substrate and the lower DBM substrate apart to define the interior of the microelectronic package between the lower DBM substrate and the upper DBM substrate (Fig. 20, 124 and 126 spaced apart by left and right sides of 122 including 128 and 138/140, para 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Nuotio to include the lead frame and associated clips as taught by chew since they are both from the same field of endeavor and in order to improve the operability and reliability of the device.
Regarding claim 10, Nuotio as modified teaches the limitations of claim 1 upon which claim 10 depends.
Nuotio teaches wherein: the upper set of dies and the lower set of dies are transistor-dies that each include: a first side including a drain pad; and a second side, opposite to the first side, that includes a gate pad and a source pad (Fig. 2, drain pad 210, gate pad 230, source pad 220).
Regarding claim 11, Nuotio as modified teaches the limitations of claim 10 upon which claim 11 depends.
Nuotio teaches wherein the signal tab of the lead frame is configured to electrically connect all gate pads of the transistor-dies in parallel (Fig. 5 and 6, signal tabs 505a and 605a).
Regarding claim 12, Nuotio as modified teaches the limitations of claim 10 upon which claim 12 depends.
Nuotio teaches wherein: the transistor-dies of the upper set of dies are coupled to the signal tab by sinter or solder connections (para 33-35) between the gate pad of each transistor-die and an upward clip of the plurality of upward clips (Fig. 5 and 6, signal pad connectors 560b, 570b, 580b, 590b, 660b, 670b, 680b, 690b); and the transistor-dies of the lower set of dies are coupled to the signal tab by solder connections (par 33-35) between the gate pad of each transistor-die and a downward clip of the plurality of upward clips (Fig. 5 and 6, signal pad connectors 560b, 570b, 580b, 590b, 660b, 670b, 680b, 690b).
Regarding claim 13, Nuotio as modified teaches the limitations of claim 1 upon which claim 13 depends.
Nuotio teaches wherein: the upper DBM substrate includes an upper low-side conductor and an upper high-side conductor that are electrically separated by an upper gap, the lower DBM substrate includes a lower low-side conductor and a lower high-side conductor that are electrically separated by a lower gap (Fig. 5 and 6, 520/620 and 510/610 separated by gap); and the bidirectional clip (Fig. 7, 505d/605d) of the output tab is sintered or soldered to the upper low-side conductor on the upper DBM substrate and the lower low-side conductor on the lower DBM substrate (para 58, external busbars with welding bond).
Regarding claim 14, Nuotio teaches a half-bridge circuit comprising: a package including:
an upper direct bonded copper (DBC) substrate (Fig. 4, 41, para 30) including an upper high-side conductor and an upper low-side conductor (Fig. 5, 505a and 505b);
a lower DBC substrate (Fig. 4, 44, para 30) including a lower high-side conductor and a lower low-side conductor (Fig. 6, 605a and 605b),
a high-side transistor including:
a first group of transistor-dies, wherein a first portion of the first group of transistor- dies are directly connected to the upper high-side conductor and a second portion of the first group of transistor-dies are directly connected to the lower high-side conductor (Fig. 4-6, dies 400a and 400b, attached to 520/620 and 510/610); and
a low-side transistor including:
a second group of transistor-dies, wherein a first portion of the second group of transistor-dies are directly connected to the upper low-side conductor and a second portion of the second group of transistor-dies are directly connected to the lower low-side conductor (Fig. 4-6, dies 400a and 400b, attached to 520/620 and 510/610).
Nuotio does not specifically teach:
an output tab including a tab for electrical connection to external circuitry and a first bidirectional clip including a downward bend towards a lower step for connection to the lower DBC substrate and an upper bend towards an upper step for connection to the upper DBC substrate, the first bidirectional clip spacing the upper DBC substrate apart from the lower DBC substrate, and electrically connecting the upper low-side conductor and the lower low-side conductor to the tab
a power tab including a second bidirectional clip that supports and positions the upper DBC substrate apart from the lower DBC substrate, the second bidirectional clip electrically connecting the upper high-side conductor and the lower high-side conductor to the power tab.
Chew teaches
an output tab including a tab for electrical connection to external circuitry (Fig. 1-22, lone large tab on signal side of lead frame 34/110/122) and a first bidirectional clip including a downward bend towards a lower step for connection to the lower DBC substrate and an upper bend towards an upper step for connection to the upper DBC substrate (Fig. 3, downward and upward bend in lone large tab on signal side of lead frame), the first bidirectional clip spacing the upper DBC substrate apart from the lower DBC substrate, and electrically connecting the upper low-side conductor and the lower low-side conductor to the tab (Fig. 20, 124 and 126 spaced apart by and electrically connected to lead frame 122).
PNG
media_image1.png
503
364
media_image1.png
Greyscale
a power tab including a second bidirectional clip that supports and positions the upper DBC substrate apart from the lower DBC substrate, the second bidirectional clip electrically connecting the upper high-side conductor and the lower high-side conductor to the power tab (Fig. 16 and 20, 128);
PNG
media_image2.png
370
545
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Nuotio to include output and power tabs as taught by chew since they are both from the same field of endeavor and in order to improve the operability and reliability of the device.
Regarding claim 15, Nuotio as modified teaches the limitations of claim 14 upon which claim 15 depends.
Nuotio teaches wherein the first group of transistor dies and the second group of transistor dies are each a metal oxide semiconductor field effect transistor (MOSFET) (para 25, die 200 MOSFET) that includes: a drain pad on a first side; and a gate pad and a source pad on a second side, the second side opposite the first side (Fig. 2, drain pad 210, gate pad 230, source pad 220).
Regarding claim 16, Nuotio as modified teaches the limitations of claim 15 upon which claim 16 depends.
Nuotio teaches wherein: each MOSFET of the first portion of the first group of transistor-dies is sintered or soldered at drain pads to the upper high-side conductor; each MOSFET of the second portion of the first group of transistor dies is sintered or soldered at drain pads to the lower high-side conductor ; each MOSFET of the first portion of the second group of transistor-dies is sintered or soldered at drain pads to the upper low-side conductor; and each MOSFET of the second portion of the second group of transistor dies is sintered or soldered at drain pads to the lower low-side conductor (Fig. 4, dies 400a and 400b, bond layers 450a and 450b para 33, and clad layers 415 and 445).
Regarding claim 17, Nuotio as modified teaches the limitations of claim 16 upon which claim 17 depends.
Nuotio teaches further including: a first gate tab extending between the upper high-side conductor and the lower high-side conductor, the first gate tab including: a plurality of upward clips coupled to the gate pads of each MOSFET sintered or soldered to the upper high-side conductor; and a plurality of downward clips coupled to the gate pads of each MOSFET sintered or soldered to the lower high-side conductor; and a second gate tab extending between the upper high-side conductor and the lower high-side conductor, the second gate tab including: a plurality of upward clips coupled to the gate pads of each MOSFET sintered or soldered to the upper low-side conductor; and a plurality of downward clips coupled to the gate pads of each MOSFET sintered or soldered to the lower low-side conductor (Fig. 4-6, gate pads 230, gate tabs first 505a and second 605a via cladding 520/620, plurality of upward and downward clips 440a/440b para 35).
Regarding claim 18, Nuotio as modified teaches the limitations of claim 15 upon which claim 18 depends. Nuotio teaches wherein the MOSFET is silicon carbide (SiC) (para 26, silicon carbide).
Regarding claim 21, Nuotio as modified teaches the limitations of claim 1 upon which claim 21 depends.
Nuotio teaches the upper DBM substrate includes an upper conductor covering the upper DBM substrate, the upper conductor divided into an upper high-side conductor and an upper low-side conductor by an upper gap (Fig. 5, 520 and 510 separated by gap); and
the lower DBM substrate includes a lower conductor covering lower DBM substate, the lower conductor divided into a lower high-side conductor and a lower low-side conductor by a lower gap (Fig. 6, 620 and 610 separated by gap).
Regarding claim 22, Nuotio as modified teaches the limitations of claim 14 upon which claim 22 depends.
Nuotio teaches the upper DBM substrate includes an upper conductor covering the upper DBM substrate, the upper conductor divided into an upper high-side conductor and an upper low-side conductor by an upper gap (Fig. 5, 520 and 510 separated by gap); and
the lower DBM substrate includes a lower conductor covering lower DBM substate, the lower conductor divided into a lower high-side conductor and a lower low-side conductor by a lower gap (Fig. 6, 620 and 610 separated by gap).
Response to Arguments
Applicant’s arguments, filed 16 April 2026, with respect to the rejection(s) of claim 1 and 14 under 35 U.S.C. 102(a)(2) have been fully considered and are persuasive as to the primary reference, Nuotio, lacking the amended limitations. However, upon further consideration, for claims 1 and 14, a new ground(s) of rejection is made using Nuotio in view of a newly found prior art reference to Chew et al (US Publication 20220415857).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights