DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s response filed 11/12/2025 has been fully considered.
The cancellation of claim 3 overcomes the previously raised objection.
Applicant’s amendments and the accompanying arguments, with respect to the rejection of claim 1 under 35 U.S.C. 102 as anticipated by Ahn, particularly, filling the groove with a first filler and performing a back etch to the first filler in the top sub-groove without etching the first filler in the bottom sub-groove (point 1 on page 7 of the remarks), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Applicant’s arguments, with respect to the rejection of claims under 35 U.S.C. 103 as obvious over Applicant’s admitted prior art (AAPA) in view of Ahn, Huang, and Chen, have been fully considered but are not persuasive.
Applicant argued that Ahn does not teach performing an isotropic second etching to the top sub-groove to expand an opening width of the top sub-groove outward laterally, wherein the first filler prevents the isotropic second etching from etching the bottom sub-groove (point 2 on page 7 of the remarks).
However, Ahn clearly conducts an etch to the top sub-groove to expand an opening width of the top sub-groove outward laterally, wherein the first filler prevents the isotropic second etching from etching the bottom sub-groove as is seen in the progression from Figure 6 to Figure 7 and detailed in sidewalls 151 and 152 in Figure 8 and paragraph 34.
Applicant argued that Ahn does not teach removing the first filler from the bottom sub-groove before the third etching (point 3 on page 8 of the remarks).
However, Ahn clearly discloses removing the first filler 160 from the bottom sub-groove, Figure 9 and paragraph 40, before the third etching, Figure 10 and paragraph 41.
Applicant argued Chen and Huang do not cure the deficiencies of AAPA in view of Ahn.
However, Chen, for example teaches an analogous second etch step performed using an isotropic etching process. As is further addressed in detail below, the combination of references renders the invention as claimed obvious. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The rejection is therefore maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 6-11, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s admitted prior art in view of Ahn et al. (US 2012/0058616), Huang et al. (US 2015/0014765) and Chen et al. (US 2009/0045456).
In reference to claim 1, Applicant’s admitted prior art, hereafter “AAPA,” discloses a method for manufacturing a sigma-shaped groove in a silicon semiconductor substrate, comprising:
step 1: performing a first etching, wherein the first etching forms a groove, 108a in Figure 1A, in a selected area of the silicon semiconductor substrate, wherein the first etching is dry etching, and wherein the groove is configured to be U-shaped, paragraph 7 of Applicant’s specification; and
step 3: performing a third etching, Figure 1B, wherein the third etching adopts different etching rates on different crystal surfaces of the silicon semiconductor substrate, and expands side surface of the groove to have a sigma-shaped cross section, wherein an apex is formed by intersection of an upper side surface and a lower side surface, paragraph 16 of Applicant’s specification.
Applicant does not admit as prior art the groove comprises a top sub-groove and a bottom sub-groove under the top sub-groove;
step 2: filling the groove with a first filler and performing a back etch to the first filler in the top sub-groove without etching the first filler in the bottom sub-groove;
performing an isotropic second etching to the top sub-groove to expand an opening width of the top sub-groove outward laterally, wherein the first filler prevents the isotropic second etching from etching the bottom sub-groove,
removing the first filler from the bottom sub-groove,
performing a third etching to the top sub-groove and the bottom sub-groove, wherein the third etching expands side surfaces of the groove to have a sigma-shaped cross section wherein an upper side surface of the groove is expanded from the top sub-groove, a lower side surface of the groove is expanded from the bottom sub-groove, and an apex is formed by intersection of the upper side surface and the lower side surface.
Ahn discloses a method of making a semiconductor device including teaching performing a first etching, wherein the first etching forms a groove, 150 in Figure 5, in a selected area of the silicon semiconductor substrate, wherein the first etching is dry etching, and wherein the groove is configured to be U-shaped, and wherein the groove comprise a top sub-groove and a bottom sub-groove under the top sub-groove paragraph 31;
filling the groove with a first filler, paragraph 33,
performing a second etching to the top sub-groove, 155 in Figure 7, to expand an opening width of the top sub-groove outward laterally, wherein the first filler 160 prevents the second etching from etching the bottom sub-groove, paragraphs 33 and 34 and Figures 6-8.
removing the first filling layer from the bottom sub-groove, paragraph 40, and
performing a third etching to the top sub-groove and the bottom sub-groove, Figure 10, wherein the third etching adopts different etching rates on different crystal surfaces of the silicon semiconductor substrate and expands side surfaces of the groove to have a sigma-shaped cross section wherein an upper side surface of the groove is expanded from the top sub-groove, a lower side surface of the groove is expanded from the bottom sub-groove, and an apex is formed by intersection of the upper side surface and the lower side surface, Figure 10 and paragraphs 41 and 42.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the method to include the groove comprising a top sub-groove and a bottom sub-groove under the top sub-groove;
step 2: filling the groove with a first filler;
performing a second etching to the top sub-groove to expand an opening width of the top sub-groove outward laterally, wherein the first filler prevents the isotropic second etching from etching the bottom sub-groove,
removing the first filler from the bottom sub-groove, and
performing the third etching to the top sub-groove and the bottom sub-groove, wherein the third etching expands side surfaces of the groove to have a sigma-shaped cross section wherein an upper side surface of the groove is expanded from the top sub-groove, a lower side surface of the groove is expanded from the bottom sub-groove, and an apex is formed by intersection of the upper side surface and the lower side surface.
One would have been motivated to do so in order to form the tip of an epitaxial layer closer to the channel region in order to increase the stress applied to the channel region, paragraph 35.
AAPA in view of Ahn does not disclose performing a back etch to the first filler in the top sub-groove without etching the first filler in the bottom sub-groove, or
the second etching is an isotropic etching.
Huang et al. (US 2015/0014765), hereafter “Huang,” discloses a method of making a semiconductor device including teaching filling the groove with a first filler, 9 in Figure 2(k), and performing a back etch to the first filler in the top sub-groove without etching the first filler, 9 in Figure 2(l), in the bottom sub-groove, paragraph 31.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to fill the groove with a first filler and perform a back etch to the first filler in the top sub-groove without etching the first filler in the bottom sub-groove.
To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one film forming method for another.
Chen et al. (US 2009/0045456), hereafter “Chen,” discloses a method of making a semiconductor device including teaching a second etching comprises isotropic etching, Figures 2 to 3 and paragraphs 58-60. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second etching to comprise isotropic etching. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one etching condition for another as suggested by Chen, paragraph 59.
In reference to claim 2, AAPA discloses step 1 comprises following steps: step 11: forming a hard mask layer; step 12: performing patterning on the hard mask layer to open a forming area of the groove; and step 13: performing the first etching on the patterned hard mask layer to form the groove, paragraphs 11, 12, and 15 of Applicant’s specification.
In reference to claim 4, Ahn discloses the first filling layer is formed by adopting a coating process, paragraph 32.
In reference to claim 6, AAPA discloses the silicon semiconductor substrate is a silicon substrate, wherein the top surface of the silicon semiconductor substrate is a (100) crystal surface; wherein in step 3, the etching rates of the third etching on a (110) surface, a (100) surface and a (111) crystal surface decrease sequentially, and wherein after the third etching is completed, both the upper side surface and the lower side surface of each side surface of the sigma-shaped groove are (111) crystal surfaces, paragraph 16 of Applicant’s specification.
In reference to claim 7, AAPA discloses the third etching is wet etching and a wet etching solution for the third etching comprises TMAH, paragraph 16 of Applicant’s specification.
In reference to claim 8, AAPA discloses the groove is located between two sides of gate structures, Figure 1A.
In reference to claim 9, AAPA discloses a PMOS and an NMOS are formed in an integrated process on the silicon semiconductor substrate, and wherein the groove is located between two sides of gate structures of the PMOS; wherein the sigma-shaped groove provides a space for an embedded silicon germanium epitaxial layer, and wherein the vertical first spacing constitutes the apex-gate height, paragraphs 8 and 16 of Applicant’s specification.
In reference to claim 10, AAPA discloses the hard mask layer, 107 in Figure 1A, is disposed on side surfaces and top surfaces of the gate structures and on surfaces of outer sides of the gate structures.
In reference to claim 11, AAPA discloses step 12 further comprises performing a first photolithography process to form a first photoresist pattern, wherein an opening of the first photoresist pattern is located in a forming area of the groove and a forming area of the PMOS; and performing etching on the hard mask layer by using the first photoresist pattern to remove the hard mask layer from the surface of the silicon semiconductor substrate in the forming area of the groove, paragraphs 12 and 13 of Applicant’s specification.
In reference to claim 13, AAPA disclose in step 12, the opening width of the first photoresist pattern is more than a width of a spacing area between the gate structures and the spacing area between the gate structures is opened; and wherein after the hard mask layer is etched, in the spacing area between the gate structures, the hard mask layer on side surfaces of the gate structures on the two sides of the groove is retained, and the hard mask layer is removed from a top of the groove, Figure 1A.
In reference to claim 16, AAPA discloses each of the gate structures comprises a gate dielectric layer and a polysilicon gate stacked sequentially, and wherein side walls are formed on side surfaces of the polysilicon gate, paragraph 8 of the specification.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s admitted prior art in view of Ahn et al. (US 2012/0058616), Huang et al. (US 2015/0014765) and Chen et al. (US 2009/0045456) as applied above and further in view of Wang (US 2020/0105537).
In reference to claim 5, AAPA in view of Ahn does not disclose a material of the first filling layer comprises photoresist, BARC, SOC, ODL, of DUO.
Ahn teaches a material of the first filling layer comprises oxide and Huang teaches a material of the first filling layer comprises silicon nitride. Wang (US 2020/0105537) discloses a method of making a semiconductor device including teaching silicon oxide or silicon nitride as a BARC, paragraph 19.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the material of the filling layer to comprise BARC. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s admitted prior art in view of Ahn et al. (US 2012/0058616), Huang et al. (US 2015/0014765), and Chen et al. (US 2009/0045456) as applied to claim 11 above and further in view of Hu et al. (US 2015/0021695).
In reference to claim 12, AAPA discloses wherein in the first photolithography process, the first photoresist pattern is formed by exposing and developing a first photoresist layer; in a spacing area between the gate structures, paragraphs 13 and 14 of Applicant’s specification.
AAPA does not disclose, before the first photoresist layer is coated, the method further comprises a step of coating a first organic anti-reflective coating layer, wherein the first organic anti-reflective coating layer fills a spacing area between the gate structures and extends to the hard mask layer on top of the gate structures; wherein the first photoresist layer is coated on a surface of the first organic anti-reflective coating layer; and after the first photoresist pattern is formed, the first organic anti-reflective coating layer is etched first and then the hard mask layer is etched.
Hu et al. (US 2015/0021695), hereafter “Hu,” discloses a method of making a semiconductor device including teaching patterning a hardmask layer including, before the first photoresist layer, ArF photoresist 124 in Figure 4, is coated, the method further comprises a step of coating a first organic anti-reflective coating layer, anti-reflective coating layer (not shown), wherein the first organic anti-reflective coating layer fills a spacing area between the gate structures 112 and extends to the hard mask layer 120 on top of the gate structures; wherein the first photoresist layer is coated on a surface of the first organic anti-reflective coating layer paragraph 32; and after the first photoresist pattern is formed, the first organic anti-reflective coating layer is etched first and then the hard mask layer is etched, Figures 4 and 5 and paragraph 33.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for, before the first photoresist layer is coated, the method to further comprise a step of coating a first organic anti-reflective coating layer, wherein the first organic anti-reflective coating layer fills a spacing area between the gate structures and extends to the hard mask layer on top of the gate structures; wherein the first photoresist layer is coated on a surface of the first organic anti-reflective coating layer; and after the first photoresist pattern is formed, the first organic anti-reflective coating layer is etched first and then the hard mask layer is etched.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, patterning the hardmask taught by AAPA with the patterning technique taught by Hu.
Claims 14, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s admitted prior art in view of Ahn et al. (US 2012/0058616), Huang et al. (US 2015/0014765), and Chen et al. (US 2009/0045456) as applied to claim 10 above and further in view of Murthy et al. (US 6,541,343).
In reference to claim 14, AAPA discloses the spacing area between the gate structures as addressed above in reference to claim 8.
AAPA in view of Ahn and Huang does not disclose step 2 further comprises filling a first filling layer in a spacing area between the gate structures and wherein the first filling layer extends to the gate structures to cover the hard mask layer on top of the gate structures.
Murthy et al. (US 6,541,343), hereafter “Murthy,” discloses a method of making a semiconductor device including teaching filling a first filling layer, 402, 403 in Figure 4, in a spacing area beside the gate structure and wherein the first filling layer extends to the gate structure to cover a hard mask layer 204 on top of the gate structures col. 6 lines 46-56.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of AAPA in view of Huang to fill the first filling layer in a spacing area between the gate structures, wherein the first filling layer extends to the gate structures to cover the hard mask layer on top of the gate structures.
One would have been motivated to do so in order to cover the top surface of the gate during subsequent processing, col. 7 lines 18-35.
In reference to claim 15, Murthy discloses a thickness of the first filling layer is in a range of 500Å-4000Å, col. 7 lines 8-9.
In reference to claim 18, Ahn discloses in step 24, after removing the first filling layer, the method further comprises a step of performing cleaning, paragraph 40.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s admitted prior art in view of Ahn et al. (US 2012/0058616) Huang et al. (US 2015/0014765), and Chen et al. (US 2009/0045456) as applied to claim 1 above and further in view of Lin et al. (US 2023/0050300).
In reference to claim 17, Ahn discloses the opening width of the top sub-groove is larger than an opening width of the top area of the groove before the second etching, paragraph 34.
AAPA in view of Ahn does not disclose the opening width of the top sub-groove is in a range of 5Å-200 Å.
Lin et al. (US 2023/0050300) discloses an analogous method of making a semiconductor device including teaching a width, w2 in Figure 3F (width w2 expanded from width w1), in a range of 5Å-200 Å, (width w1 is 10-35 nm (100-350 Å), paragraph 36, spacers 242 are 3-10 nm (30-100 Å) thick, paragraph 28, w2 < s + (2t1 – 2pi), s = w1, paragraph 36, pi is 5-8 nm (50-80 Å, paragraph 39). Where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the opening width of the top sub-groove to be in a range of 5Å-200 Å.
To do so would have merely been to apply a known technique to improve similar methods in the same way, KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. C. In this case, applying the method of AAPA in view of Ahn to the device scaled as taught by Lin.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sriraman et al. (US 7,303,999), Li et al. (US 2016/0240672), Kim (US 2015/0079740), Wei et al. (US 2013/0017661), and He et al. (US 2012/0309152) disclose related methods of etching source/drain recesses.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897
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