Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 11/11/2025. Currently, claims 1-9, 11-17 and 19-21 are pending in the application. Claims 10, 18 and 22-71 have been withdrawn from Consideration and have been cancelled.
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-9, 11-17 and 19-21, in the reply filed on 11/11/2025 is acknowledged. However, Applicant’s traversal with arguments is moot since the claims have been cancelled from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 11-14 and 20-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jessen (US 20240063292 A1).
Regarding claim 1, Figures 1B and 9-13 of Jessen disclose a semiconductor device, comprising:
a nitrogen polar (N-polar) Group III-nitride semiconductor structure (100B, Figure 1B, [0067]), the N-polar Group III-nitride semiconductor structure having a first surface (top surface of 100B in the Figure 1B) and a second surface (bottom surface of 100B in the Figure 1B) opposing the first surface;
an electrode (170, gate electrode in Figures 7-8, it is applicable to the N-polar Group III-nitride semiconductor structure in Figures 9-13, [0117]-[0118]);
a low-k dielectric layer (160, Figures 7-8) located between the first surface of the N-polar Group III-nitride semiconductor structure and at least a portion of the electrode; and
wherein the low-k dielectric layer (160, [0097], considering silicon oxide) has a dielectric constant of less than about 3.9 (silicon oxide whose typical dielectric constant is 3.9 or less).
Regarding claim 2, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the dielectric constant of the low-k dielectric layer (160, [0097]) is greater than 1.
Regarding claim 3, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the low-k dielectric layer ([0097]) comprises one or more of a doped silicon dioxide, a porous silicon dioxide, an organic material, or a silicon-based polymeric material (considering silicon oxide having some porosity as the porosity is not specific in the claim on a broadest reasonable interpretation).
Regarding claim 4, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the electrode (170) comprises a first portion (bottom portion of 170) on the N-polar Group III-nitride semiconductor structure and a second portion (top portion of 170) on the first portion, the first portion extending generally perpendicular to the first surface of the N-polar Group III-nitride semiconductor structure and the second portion extending generally parallel to the first surface of the N-polar Group III-nitride semiconductor structure (T-shape gate 170 meets the limitation).
Regarding claim 5, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 4, wherein the first portion (vertical bottom portion of 170, Figures 7-8) of the electrode extends into the N-polar Group III-nitride semiconductor structure.
Regarding claim 6, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 4, the second portion (horizontal top portion of 170, Figures 7-8) of the electrode is spaced apart from the first portion of the N-polar Group III-nitride semiconductor structure.
Regarding claim 7, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 6, wherein the low-k dielectric layer (160) contacts (in Figure 7) the second portion of the electrode (170).
Regarding claim 8, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 6, wherein the low-k dielectric layer (160, Figure 7) fills a space defined between the first surface of the N-polar Group III-nitride semiconductor structure and the second portion of the electrode.
Regarding claim 9, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the electrode (170, [0099]) is a gate contact, wherein the gate contact is a T-gate contact or a gamma-gate contact.
Regarding claim 11, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the semiconductor device further comprises a second dielectric layer (150, Figure 7) between the low-k dielectric layer (160) and the N-polar Group III-nitride structure (100B).
Regarding claim 12, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 11, wherein the second dielectric layer (150, Figure 7) comprises silicon nitride ([0072]).
Regarding claim 13, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 11, wherein the low-k dielectric layer (160, Figure 7) fills a space defined between the second dielectric layer (150) and at least portion of the electrode (170).
Regarding claim 14, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the Group III-nitride semiconductor structure comprises a barrier layer (130, Figure 12B, [0054]), a channel layer (120), and one or more cap layers (141 and 140, [0068]), wherein the Group III-nitride semiconductor structure comprises a trench (153B or 154B, [0105]) extending at least partially into the one or more cap layers (141 and 140).
Regarding claim 19, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the semiconductor device comprises a silicon carbide substrate ([0029]).
Regarding claim 20, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the semiconductor device is a high electron mobility transistor device ([0035]).
Regarding claim 21, Figure 1B and 9-13 of Jessen disclose a transistor device, comprising:
a nitrogen polar (N-polar) Group III-nitride semiconductor structure (100B, Figure 1B, [0067]), the N-polar Group III-nitride semiconductor structure comprising:
a barrier layer (130, [0067]);
a channel layer (120, [0067]) on the barrier layer; and
one or more cap layers (141+140, [0067]) on the channel layer; and
wherein the transistor device comprises a trench (153, [0105], Figure 12, applies to Figure 1B) extending at least partially into the one or more cap layers (140 and 141) of the N-polar Group III-nitride semiconductor structure (100B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-17 are rejected under 35 U.S.C. 103 as being obvious over Jessen (US 20240063292 A1) in view of Guidry et al (US 20200273974 A1).
Regarding claims 14-15, Figures 1B and 9-13 of Jessen disclose that the semiconductor device of claim 1, wherein the Group III-nitride semiconductor structure comprises a barrier layer (130, Figure 12B, [0054]), a channel layer (120), and one or more cap layers (141 and 140, [0068]).
Jessen does not tach wherein the Group III-nitride semiconductor structure comprises a trench extending at least partially into the one or more cap layers, wherein the trench has a lateral width extending between a gate contact and a drain contact.
However, Guidry is a pertinent art which teaches III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation. Figures 2-6 of Guidry teach such structure wherein there is recess in the cap layers (16 and 17, [0048]) in order to reduce channel charge density near the gate and reduce the peak electric field in drain-side access region, and increase the overall device breakdown voltage ([0043] and [0061]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Jessen, wherein the Group III-nitride semiconductor structure comprises a trench extending at least partially into the one or more cap layers, wherein the trench has a lateral width extending between a gate contact (170, Figure 8 of Jessen) and a drain contact (182, Figure 13 of Jessen) according to the teaching of Guidry in order to reduce channel charge density near the gate and reduce the peak electric field in drain-side access region, and increase the overall device breakdown voltage ([0043] and [0061] of Guidry).
Regarding claims 16-17, Jessen in view of Guidry do not explicitly teach that the semiconductor device of claim 15, wherein the lateral width is about 50% or greater of a distance between the gate contact and the drain contact. Or
The semiconductor device of claim 15, wherein the trench extends to a depth from the first surface of about 250 Angstroms to about 1000 Angstroms.
However, Figures 2-7 of Guidry teach that the trench width and depth is a result effective variable in order to increase the device breakdown voltage and also improve device performance by reducing charge density near the recess ([0043]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use the claimed width and the depth of the trench with routine experiment and optimization since these width and depth are result effective variable in order to improve the performance of the device according to the teaching of Guidry ([003]). In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813