DETAILED ACTION
Election/Restrictions
1. Applicant's election with traverse of Species I (claims 1-3, 8, 9, and 13) in paper filed 12/10/25 is acknowledged. The traversal is on the ground(s) that Species I should not be limited to the sealing resin body containing no filler and should include embodiments in which the sealing resin body contains filler. This is found persuasive and restriction is withdrawn. Claims 1-14 are under examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 thru 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lachner et al. US 2012/0156830 A1. Lachner discloses (see, for example, FIG. 3O) an element package 300 comprising a semiconductor element that includes a semiconductor substrate 10 having an element region (i.e. the active main surface of the semiconductor substrate 10), main electrode 11, pad 20, scribe region (i.e. region next to the semiconductor substrate 10), sealing resin body 14, redistribution layer 32/18, insulator 32, and wiring 18. The scribe region is the region directly to the right or left of the semiconductor substrate 10 wherein the semiconductor substrate 10 is surrounded by a sealing resin body 14 that is cut (i.e. scribed) and the scribe region includes any region around the cut that does not include the semiconductor substrate 10. The sealing resin 14 does not cover the main electrode 11 and the pad 20, and hence exposed from the sealing resin body 14. In FIG 3O, Lachner discloses the insulator 32 being in contact with the surface of the semiconductor substrate 10 over the element region, and the scribe region. In paragraph [0016], Lachner discloses the semiconductor chips including integrated circuits (i.e. element), and in paragraph [0018], discloses the semiconductor chip contains a semiconductor substrate.
Regarding claim 11, see, for example, paragraph [0016] wherein Lachner discloses power integrated circuits, which have switches such as transistors, etc.
Regarding claim 12, see, for example, FIG. 3P wherein Lachner discloses the signal wiring connected to the pad 20, and extending over the semiconductor substrate 10 and over the boundary 12 between the element region and the scribe region.
Allowable Subject Matter
Claims 1 thru 9, 13, and 14 are allowed. The references of record, either singularly or in combination, do not teach or suggest at least an element package comprising: the semiconductor substrate having an element region formed with an element and a scribe region disposed in a predetermined area from an end portion of the semiconductor substrate and surrounding the element region, the protective film being disposed above the element region on the surface of the semiconductor substrate so that the main electrode and the pad are exposed from the protective film; a sealing resin body that seals the semiconductor element so that the main electrode and the pad are exposed from the sealing resin body; a redistribution layer includes an insulator and a wiring disposed in the insulator; and an insulating portion that is disposed above the scribe region on the surface of the semiconductor element with a height that does not exceeds an outer peripheral edge portion of an upper surface of the protective film on the element region, wherein the redistribution layer is disposed to extend over the protective film and the insulating portion.
Regarding claim 13, the references of record, either singularly or in combination, do not teach or suggest at least a semiconductor device comprising: an element package; a heat dissipation member; and a signal terminal, wherein the element package includes: a semiconductor element that includes the semiconductor substrate having an element region formed with an element and a scribe region disposed in a predetermined area from an end portion of the semiconductor substrate and surrounding the element region, the protective film being disposed above the element region on the surface of the semiconductor substrate so that the main electrode and the pad are exposed from the protective film; a sealing resin body that seals the semiconductor element so that the main electrode and the pad are exposed from the sealing resin body; a redistribution layer that includes an insulator and a wiring disposed in the insulator; an insulating portion that is disposed above the scribe region on the surface of the semiconductor element with a height that does not exceed an outer peripheral edge portion of an upper surface of the protective film on the element region, wherein the redistribution layer is disposed to extend over the protective film and the insulator, the wiring includes a signal wiring connected to the pad, the signal wiring is disposed to extend over a boundary between the element region and the scribe region in a plan view in a thickness direction of the semiconductor substrate, the heat dissipation member is disposed to interpose the semiconductor element in the thickness direction, and the signal terminal is joined to a terminal portion of the signal wiring exposed from the insulator, and is electrically connected to the pad through the signal wiring.
Regarding claim 14, the references of record, either singularly or in combination, do not teach or suggest at least a semiconductor device comprising: the element package includes: the semiconductor substrate having an element region formed with an element and a scribe region disposed in a predetermined area from an end portion of the semiconductor substrate and surrounding the element region; a sealing resin body that seals the semiconductor element so that the main electrode and the pad are exposed from the sealing resin body; a redistribution layer includes an insulator and a wiring disposed in the insulator, wherein the insulator is in contact with the surface of the semiconductor substrate over the element region and the scribe region, the wiring includes a signal wiring connected to the pad, and the signal wiring is disposed to extend over a boundary between the element region and the scribe region in a plan view in a thickness direction of the semiconductor substrate, the heat dissipation member is disposed to interpose the semiconductor element in the thickness direction, and the signal terminal is joined to a terminal portion of the signal wiring exposed from the insulator, and is electrically connected to the pad through the signal wiring.
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Eugene Lee
January 29, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815