DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/13/2025 was filed after the mailing date of the Non-Final Office Action on 09/11/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Acknowledgment is made of the amendment filed 12/11/2025, in which: claims 1 and 17 are amended; claims 18-20 stand withdrawn; and the rejection of the claims are traversed. Claims 1-17 are currently pending an Office action on the merits as follows.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-11, 13-15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al. (KR Publication 20200138567/Machine Translation Document of 02/10/2026).
Regarding independent claim 1, Ko teaches a display panel (fig. 4a, 10) comprising:
a base substrate (100) having a hole (10H) defined therethrough;
a thin film transistor (fig. 8, TFT) on the base substrate, and spaced from the hole;
a light emitting element (OLED) comprising a pixel electrode (221) spaced from the hole, and connected to the thin film transistor (fig. 8);
a first insulating layer (211) between the base substrate and the pixel electrode, and having a groove pattern (G) defined therein between the pixel electrode and the hole in a plan view (fig. 8);
a first conductive pattern (fig. 9, L2) spaced from the pixel electrode, and comprising a tip portion defining a first pattern hole (L2-h) overlapping with the groove pattern (fig. 9); and
a second conductive pattern (L3) spaced from the pixel electrode, overlapping with the first conductive pattern in a plan view (fig. 9), and defining a second pattern hole (L3-h), wherein the second pattern hole overlaps with the first pattern hole (fig. 9).
Regarding dependent claim 2, Ko teaches the display panel of claim 1, wherein the second conductive pattern is at a same layer as that of the pixel electrode (fig. 8, bottom portion of pixel electrode 221 and second conductive pattern L3 are both in first insulation layer 211).
Regarding dependent claim 3, Ko teaches the display panel of claim 1, wherein the second conductive pattern (machine translation, page 13 paragraph 2, “the third layer (L3) is indium zinc oxide (IZO), indium tin oxide (ITO), zinc oxide (ZnO)”) comprises a same material as that of the pixel electrode (page 10 paragraph 2, “pixel electrode 221 is indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In.sub.2 O.sub.3)”).
Regarding dependent claim 4, Ko teaches the display panel of claim 1, wherein the second conductive pattern comprises a material different from a material of the first conductive pattern (machine translation, page 13 paragraph 3).
Regarding dependent claim 5, Ko teaches the display panel of claim 1, wherein the tip portion has a side surface defining the first pattern hole, and protruding more toward a center of the first pattern hole than an inner side surface of the first insulating layer defining the groove pattern (see figure below).
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Regarding dependent claim 6, Ko teaches the display panel of claim 5, wherein the first conductive pattern comprises a plurality of conductive layers (machine translation, page 12 paragraph 9, “the second layer (L2), and the third layer (L3) may be provided as a single layer or a plurality of layers, respectively”), and the side surface of the tip portion is defined by side surfaces of the conductive layers (fig. 9).
Regarding dependent claim 7, Ko teaches the display panel of claim 1, wherein the second pattern hole has a width (fig. 9, W3) greater than a width of the first pattern hole (W2) in a plan view (fig. 9, W3 is greater than W2).
Regarding dependent claim 8, Ko teaches the display panel of claim 1, wherein the groove pattern surrounds the hole in a plan view (fig. 7, machine translation page 4 paragraph 9, “first to third openings 10H, 40H, and 50H are positioned to correspond to the first area OA”).
Regarding dependent claim 9, Ko teaches the display panel of claim 1, further comprising a connection electrode (fig. 8, CM) connecting the thin film transistor to the pixel electrode (fig. 8), wherein the first conductive pattern is at a same layer as that of the connection electrode (fig. 8, top portion of L2 and bottom portion of CM lie on top a same layer 207).
Regarding dependent claim 10, Ko teaches the display panel of claim 9, wherein the first conductive pattern (machine translation, page 13 paragraph 2, “second layer L2… may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti)”) comprises a same material as that of the connection electrode (page 9 paragraph 7, “contact metal layer CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc.”).
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Regarding dependent claim 11, Ko teaches the display panel of claim 1, further comprising a pixel definition layer (fig. 8, 215) having a light emitting opening (see figure below) defined therethrough to expose at least a portion of the pixel electrode (fig. 8), and a first opening (see figure below) defined therethrough to expose at least a portion of the second conductive pattern.
Regarding dependent claim 12, Ko teaches the display panel of claim 11, wherein the second conductive pattern comprises one side surface (fig. 9, PT) defining the second pattern hole, and another side surface (see figure below) opposite to the one side surface, and
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wherein the one side surface is exposed through the first opening (fig. 9), and the other side surface is covered by the pixel definition layer (fig. 9, other side surface indirectly covered by pixel definition layer 215).
Regarding dependent claim 13, Ko teaches the display panel of claim 1, further comprising an encapsulation layer (fig. 8, 300) on the light emitting element, and comprising:
a plurality of inorganic layers (310 and 330); and
an organic layer (320) between the inorganic layers, wherein at least one of the inorganic layers covers an inner side surface of the first insulating layer that defines the groove pattern (fig. 8, 310 covers inner side surface of 211).
Regarding dependent claim 14, Ko teaches the display panel of claim 13, wherein the at least one of the inorganic layers covers a side surface of the tip portion that defines the first pattern hole (fig. 8, 311 covers side surface of tip portion).
Regarding dependent claim 15, Ko teaches the display panel of claim 13, wherein the groove pattern comprises a plurality of groove patterns (fig. 8, multiple Gs), at least one of the plurality of groove patterns overlaps with the organic layer (G overlaps with 320), and another of the plurality of groove patterns is spaced from the organic layer (other Gs spaced apart from 320).
Regarding independent claim 17, Ko teaches an electronic device (fig. 1, 1) comprising:
a base substrate (fig. 4a, 100) comprising:
a hole area (OA) having a hole (10H);
a display area (fig. 5, DA) surrounding at least a portion of the hole area in a plan view; and
a non-display area (PA) adjacent to the display area in a plan view;
a thin film transistor (fig. 8, TFT) on the base substrate, and spaced from the hole;
a light emitting element (OLED) comprising a pixel electrode (221) at the display area, and connected to the thin film transistor (fig. 8);
a first insulating layer (211) between the base substrate and the light emitting element, and having a groove pattern (G) defined therein and overlapping with the hole area (fig. 7);
a first conductive pattern (fig. 9, L2) on the first insulating layer, overlapping with the hole area (fig. 7, G which contains L2 overlaps with OA), and comprising a tip portion defining a first pattern hole (L2-h) overlapping with the groove pattern (fig. 9);
a second conductive pattern (L3) at a layer different from a layer of the first conductive pattern, overlapping with the first conductive pattern in a plan view (fig. 9),
an electronic module (fig. 2b, 20) overlapping with the hole area.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Kim et al. (US Publication 20210367000).
Regarding dependent claim 16, Ko teaches the display panel of claim 1.
Ko does not teach further comprising a second insulating layer between the pixel electrode and the first insulating layer, wherein the second insulating layer is between the first conductive pattern and the second conductive pattern, and has a second opening defined therethrough, and overlapping with the first pattern hole in a plan view.
Kim teaches further comprising a second insulating layer (fig. 12, IL3) between the pixel electrode (E1, see fig. 7) and the first insulating layer (BR and BF),
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wherein the second insulating layer is between the first conductive pattern (ELP) and the second conductive pattern (see figure below), and has a second opening (see figure below) defined therethrough, and overlapping with the first pattern hole in a plan view (see figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Ko and the second insulating layer of Kim in order to create dams disposed on the substrate between the grooves (Kim paragraph 0178).
Response to Arguments
Applicant’s arguments, see page, filed 12/11/2025, with respect to the specification have been fully considered and are persuasive. The objection of 12/11/2025 has been withdrawn.
Applicant’s arguments with respect to claims 1-17 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Applicant’s arguments filed 12/11/2025 have been fully considered but are not persuasive.
Applicant argues on page 10 of the instant Remarks: “However, the part of the second electrode E2 equated with the first conductive pattern does not appear to overlap with another part of the second electrode E2 equated with the second conductive pattern in a plan view as now recited in claims 1 and 17, and thus, the cited portions of Kim do not appear to disclose or even suggest at least "a second conductive pattern spaced from the pixel electrode, overlapping with the first conductive pattern in a plan view, and defining a second pattern hole, wherein the second pattern hole overlaps with the first pattern hole," as now recited in amended claim 1, and as similarly recited in amended claim 17.”
However, as stated above, Ko teaches a second conductive pattern (fig. 9, L3) spaced from the pixel electrode (fig. 8, 221), overlapping with the first conductive pattern (fig. 9, L2) in a plan view, and defining a second pattern hole (L3-h), wherein the second pattern hole overlaps with the first pattern hole (fig. 9). Therefore, claims 1 and 17, as well as their dependent claims, stand rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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