DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
5. Acknowledgment is made of applicant's claim for foreign priority based on an application filed in People’s Republic of China on 04/14/2022. It is noted, however, that applicant has not filed a certified copy of the CN202210394299 application as required by 37 CFR 1.55.
Response to Arguments
6. Applicant’s arguments, see Rejections under 35 USC § 103, filed 12/15/2025, with respect to the rejection of claim 1 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hsiung, Te-Chih et al. (Pub No. US 20220344206 A1) (hereinafter, Hsiung) in view of Cheng, Kangguo et al. (Pub No. US 10236364 B1) (hereinafter, Cheng).
7. Applicant's arguments filed 12/15/2025 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., Hsiung’s first contract structure 1100… is different from the metal zero layer of claim 1, which is directly formed in the region between the dummy gate structures before the removal of the dummy gate structure (Page 12, Paragraph 1, Remarks)) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
8. In response to applicant's arguments against the references individually (i.e. Pages 12-13, Remarks), one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
9. In response to applicant's argument that “The oxide-based layer 1300 in Hsiung’s Figure 13 does not have a function related to removing the dummy gate structure as in the claimed method (Page 13, Paragraph 1, Remarks)), a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
10. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., A key to the claimed method is to place the step of forming the second gate structure after the formation of the metal zero layer… (Page 13, Paragraph 4, Remarks)) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Further, step 5 of claim 1 is anticipated by Hsiung although the order of process steps is reversed. (See MPEP 2144.04 (IV)(C))
11. Applicant’s arguments, see Objections to the Specification, filed 12/15/2025, with respect to the objection of the title have been fully considered and are persuasive. The objection of the title has been withdrawn.
12. Applicant’s arguments, see Objections to the Claims, filed 12/15/2025, with respect to objection of claim 17 been fully considered and are persuasive. The objection of claim 17 has been withdrawn.
13. Applicant’s arguments, see Rejections under 35 USC § 112b, filed 12/15/2025, with respect to rejection under 35 USC 112(b) of claim 1 have been fully considered and are persuasive. The rejection under 35 USC 112(b) of claim 1 has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
14. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
15. Claims 1-2 and 8-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiung, Te-Chih et al. (Pub No. US 20220344206 A1) (hereinafter, Hsiung) and further in view of Cheng, Kangguo et al. (Pub No. US 10236364 B1) (hereinafter, Cheng).
Hsiung, Fig 7: Forming dummy gate structures over front end of line
PNG
media_image1.png
531
558
media_image1.png
Greyscale
Re Claim 1, (Currently Amended) Hsiung teaches a method for manufacturing a metal zero layer, comprising the following steps:
step 1, providing a semiconductor substrate (Substrate and/or semiconductor layers; 302/304/306; Figs 6-7; ¶[0021]) that undergoes a source and drain formation process (Forming source/drain regions 704; Fig 7; ¶[0043]) of a front end of line (Around bottom of substrate 302; Fig 7),
wherein source and drain regions (Source/drain recesses; 704; Fig 7; ¶[0043]) are formed on two sides of a dummy gate structure (600; Fig 7; ¶[0035]),
a spacer (Gate spacers; 700; Fig 7; ¶[0040]) is formed on a side surface (Side surfaces of 600; Fig 7) of the dummy gate structure, a hard mask layer (Mask; 604; Fig 7; ¶[0039]) is formed on a top (Top surface of 600; Fig 7) of the dummy gate structure,
a plurality of the dummy gate structures (Plurality of dummy gate structures; 600; Fig 7; ¶[0041]) are formed on the semiconductor substrate, and an inter-gate trench (Trenches (not labelled) between dummy gates; Fig 8B) is formed in an area between the dummy gate structures;
Hsiung, Fig 9: Forming cut-off layer in metal zero layer area
PNG
media_image2.png
526
572
media_image2.png
Greyscale
step 2, forming a cut-off layer (Interlayer dielectric; 910; Fig 9; ¶[0047]) in a selected area (Within an area of trenches between dummy gates; Fig 9) of the inter-gate trench,
the cut-off layer being composed of a dielectric layer (Interlayer dielectric 910 is a dielectric layer; ¶[0051]);
Hsiung, Fig 11A: Forming metal zero layer in inter-gate trench
PNG
media_image3.png
541
585
media_image3.png
Greyscale
step 3, forming a metal zero layer (First contact structure; 1100; Fig 11A; ¶[0067]) in the inter-gate trench outside of the cut-off layer,
Hsiung, Fig 13: Forming oxide layer of metal zero layer
PNG
media_image4.png
550
589
media_image4.png
Greyscale
step 4, forming a second oxide layer (Oxide-based layer; 1300; Fig 13; ¶[0074]), the second oxide layer fully filling (Completes the filling of the inter-gate trenches; Fig 13) the inter-gate trench on the top surface (Oxide layer 1300 is on a top surface of first contact structure 1100; Fig 13) of the metal zero layer,
Hsiung, Fig 10: Removing dummy gate structure
PNG
media_image5.png
546
589
media_image5.png
Greyscale
and removing the hard mask layer (Removing mask 604 via CMP process; Figs 9-10; ¶[0051]) on the top surface of the dummy gate structure; and
step 5, removing (¶[0055]) the dummy gate structure, and forming a second gate structure (Active gate structure; 1000; Fig 10; ¶[0055]) in an area where the dummy gate structure is removed,
the second gate structure being formed by stacking a gate dielectric layer (Gate dielectric layer (not separately shown); ¶[0055]) and a metal gate (Gate metal (not separately shown); ¶[0055]).
However, Hsiung does not teach wherein the inter-gate trench outside of the cut-off layer remains in a trench structure;
wherein the cut-off layer used to cut off the metal zero layer,
etching back the metal zero layer to make the top surface of the metal zero layer lower than the top surface of the dummy gate structure; and
performing a planarization process to make a top surface of the second oxide layer level with the top surface of the dummy gate structure.
In the same field of endeavor, Cheng teaches wherein the inter-gate trench (Trenches, 44; Fig 6; Col 5 ln 55) outside of the cut-off layer (Oxide layer; 42; Fig 6; Col 5 ln 51) remains in a trench structure (Referring to Fig 6, the trenches 44 remain while oxide 42 is deposited);
wherein the cut-off layer used to cut off (CMP process is performed to remove any remaining conductive material from top surface of Fig. 7; Col 7 ln 43 – 50) the metal zero layer (Source contacts; 62S; Fig 7; Col 7 ln 20),
Cheng, Figs 6-7: Forming central oxide cut-off layer and subsequently forming contacts
PNG
media_image6.png
468
366
media_image6.png
Greyscale
etching (Etching included during CMP process; Figs 6-7; Col 7 ln 43-50) back the metal zero layer to make the top surface (Top surface of 62S; Fig 7) of the metal zero layer lower than the top surface (Top surface of dummy gate; Fig 7) of the dummy gate structure (Dummy gates; Fig 7; Col 7 ln 5-6); and
performing a planarization process (Planarization process performed on insulator caps 60S; Col 7 ln 50-57) to make a top surface (Top surface of 60S; Fig 7) of the second oxide layer level (Insulator caps; 60S; Fig 7; Col 7 ln 51) with the top surface of the dummy gate structure.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have the inter-gate trench outside of the cut-off layer remaining in a trench structure, wherein the cut-off layer used to cut off the metal zero layer, etching back the metal zero layer to make the top surface of the metal zero layer lower than the top surface of the dummy gate structure and performed a planarization process to make the top surface of the second oxide layer level with the top surface of the dummy gate structure, as taught by Cheng for the method of manufacturing a metal zero layer as taught by Hsiung.
One would have been motivated to do this with a reasonable expectation of success because the metal zero layer requires a protection layer on its upper surface for the subsequent planarization process in order to prevent corrosion and contamination of etchants. Further, the cut-off layer would be used to cut off the metal zero layer of Hsiung given additional metal zero layer material was scattered over the upper surfaces of the surrounding materials in order to ensure only the trench region contains metal zero layer material.
Re Claim 2, (Currently Amended) Hsiung teaches the method for manufacturing the metal zero layer according to claim 1,
wherein in step 2, the dielectric layer (Interlayer dielectric 910 is a dielectric layer; ¶[0051]) is a low-temperature oxide layer (Silicon oxide layer which may deposited by a low-temperature method such as PECVD or FCVD; ¶[0051]).
Hsiung, Fig 16A: Forming zero layer via above gate and metal zero layer
PNG
media_image7.png
547
596
media_image7.png
Greyscale
Re Claim 8, (Currently Amended) Hsiung teaches the method for manufacturing the metal zero layer according to claim 1, after step 5, further comprising:
forming a third oxide layer (Second oxide-based layer; 1410; Fig 16A; ¶[0076]);
etching the third oxide layer in the selected area to form an opening (Opening (not labelled) above contact structure 1100; Fig 16A) of a zero layer via (Second/Third contact structure; 1500/1600; Fig 16A; ¶[0085]),
the opening of the zero layer via being located at a top (Area on top of 1100; Fig 16A) of the selected area on the top surface of the metal zero layer (First contact structure; 1100; Fig 16A; ¶[0067]) and being located at the top of the selected area on the top surface of the second gate structure (Middle active gate structure; 1000; Fig 16A; ¶[0052]); and
filling the opening of the zero layer via with a metal (Per ¶[0089] metal may be tungsten, other material materials, such as copper (Cu), gold (Au), cobalt (Co), Ruthenium (Ru)) to form the zero layer via, the metal zero layer being in contact with the top zero layer via, and the metal gate being in contact with the top zero layer via (Second/third contact structures contact top surface of gate structure 1000 and contact structure 1100; Fig 16A).
Re Claim 9, (Currently Amended) Hsiung teaches the method for manufacturing the metal zero layer according to claim 8, wherein before formation of the third oxide layer (Second oxide-based layer; 1410; Fig 16A; ¶[0076]), further comprising a step of forming a cap layer (Etch stop layer; 1400; Fig 14; ¶[0077]), the cap layer being used to protect the metal zero layer and prevent the metal zero layer from oxidation and loss (Per ¶[0077] etch stop layer 1400 may comprise of silicon oxynitride (SiON) or silicon nitride (SiN) which may prevent oxidation and loss);
wherein in a process of forming the opening of the zero layer via, after etching of the third oxide layer, the cap layer is etched (Recess formed through etch stop layer 1400; Fig 16A; ¶[0081]) so that the opening of the zero layer via exposes a bottom metal zero layer or the top surface of the metal gate (Exposes top surface of metal gate 1000; Fig 16A).
Re Claim 10, (Original) Hsiung teaches the method for manufacturing the metal zero layer according to claim 9, wherein a material of the cap layer (Etch stop layer; 1400; Fig 14; ¶[0077]) is silicon nitride (Per ¶[0077] etch stop layer 1400 may comprise of silicon oxynitride (SiON) or silicon nitride (SiN) which may prevent oxidation and loss).
Re Claim 11, (Currently Amended) Hsiung teaches the method for manufacturing the metal zero layer according to claim 8, wherein a metal material (Material of second/third contact structure 1500/1600; ¶¶[0083, 0089]) of the zero layer via (Second/Third contact structure; 1500/1600; Fig 16A; ¶[0085]) comprises tungsten (Per ¶¶[0083, 0089] contact structures 1500/1600 may be Tungsten (W)).
Re Claim 12, (Original) Hsiung teaches the method for manufacturing the metal zero layer according to claim 1, wherein in step 5, the gate dielectric layer (Gate dielectric layer (not separately shown); ¶[0055]) comprises a high dielectric constant material layer (High-k dielectric material; ¶[0061]) ; and
the metal gate (Gate metal (not separately shown); ¶[0055]) comprises a metal work function layer (P-type or n-type work function layer; ¶[0062]) and a metal conductive material layer (Fill metal; ¶[0056]) which are stacked in sequence.
Re Claim 13, (Original) Hsiung teaches the method for manufacturing the metal zero layer according to claim 12, wherein the semiconductor substrate (Substrate and/or semiconductor layers; 302/304/306; Figs 6-7; ¶[0021]) comprises a silicon substrate (May be silicon; ¶[0022]).
Re Claim 14, (Original) Hsiung teaches the method for manufacturing the metal zero layer according to claim 13, wherein in step 1, the source and drain formation process (Forming source/drain regions 704 comprising of epitaxial structures 900; Fig 7; ¶[0043]) further comprises a step of forming an embedded epitaxial layer (Epitaxial structures embedded in recesses 704; 900; Fig 9; ¶[0047]), and the source and drain regions (Source/drain regions; 900; Fig 9; ¶[0048]) are formed in the embedded epitaxial layer.
Re Claim 16, (Original) Hsiung teaches the method for manufacturing the metal zero layer according to claim 15, wherein in step 5, a thermal process (PVD and heating silicon wafer to react with silicon and metal to form metallic silicide; ¶[0068]) in a process (Process of forming gate structures 1000 and silicide layer 1102; Fig 12; ¶[0068]) of forming the second gate structure (Active gate structure; 1000; Fig 10; ¶[0055]) is used to achieve a silicification reaction (Reaction between silicon and a metal film; ¶[0068]) between the metal zero layer (First contact structure; 1100; Fig 11A; ¶[0067]) and bottom silicon (Silicon wafer (not shown); ¶[0068]) and form a metal silicide (Silicide layer; 1102; Fig 12; ¶[0068]).
Re Claim 17, (Currently Amended) Hsiung teaches the method for manufacturing the metal zero layer according to claim 1, wherein in step 1, a material of the spacer (Gate spacers; 700; Fig 7; ¶[0040]) comprises a low dielectric constant material (Low-k spacers; ¶[0041]);
a process (Chemical vapor deposition (CVD); ¶[0041]) of forming the spacer comprises: growing a material layer (Layer of suitable dielectric material; ¶[0041]) of the spacer by means of atomic layer deposition (ALD) (Chemical vapor deposition (CVD) wherein ALD is a sub-type and suitable deposition method; ¶[0041]) ; and
etching (Etching gate spacers 700 via RIE, chemical oxide removal (COR); ¶[0054]) the material layer of the spacer to form the spacer in a self-aligned manner (Such as to align gate spacers 700 in z-direction; ¶[0054]) on the side surface of the dummy gate structure (600; Fig 7; ¶[0035])
wherein a thickness (Thickness of spacer 700 in y-direction; ¶[0041]) of the spacer is controlled by an ALD growth process (Per ¶[0041]) CVD, e.g. ALD may be used to form gate spacers having a thickness in y-direction between 1 nm to 12 nm), and a width (Width on y-direction) of the metal zero layer (First contact structure; 1100; Fig 11A; ¶[0067]) is controlled by the thickness of the spacer (Per ¶¶[0041,0067] the contact structure 1100 has dimensions defined by the recess with a width formed by the spacer(s) 700/702, therefore its width is controlled by the thickness of the spacer).
16. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiung, Te-Chih et al. (Pub No. US 20220344206 A1) (hereinafter, Hsiung) in view of Cheng, Kangguo et al. (Pub No. US 10236364 B1) (hereinafter, Cheng) as applied to claim 1 above, and further in view of Wu, Jyun-De et al. (Pub No. US 20220406653 A1) (hereinafter, Wu).
Re Claim 6, (Original) Hsiung teaches the method for manufacturing the metal zero layer according to claim 1,
wherein in step 3, a material (Cobalt (Co); ¶[0067]) of the metal zero layer (First contact structure; 1100; Fig 11A; ¶[0067]) is Co;
the metal zero layer is formed by means of an electroplating process (May be formed by electroplating; ¶[0067]); and
However, Hsiung in view of Cheng does not teach a step of forming a first barrier layer and a second seed layer is performed before formation of the metal zero layer, the first barrier layer being used to block Co diffusion of the metal zero layer.
In the same field of endeavor, Wu teaches a step of forming a first barrier layer (Barrier layer (not shown) may be included in contact plugs 122 along sidewall and bottom surface of contact openings; Fig 10; ¶[0061]) and a second seed layer (Seed layers (not shown) may be included in contact plugs 122; Fig 10; ¶[0061]) is performed before formation of the metal zero layer (Contact plugs; 122; Fig 10; Per ¶[0063] contact plugs 122 may comprise of metal bulk layers including Cobalt (Co)),
the first barrier layer being used to block Co diffusion (Prevent diffusion of cobalt from contact plug 122 from diffusing into dielectric material; ¶[0061]) of the metal zero layer.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a step of forming a first barrier layer and a second seed layer is performed before formation of the metal zero layer, the first barrier layer being used to block Co diffusion of the metal zero layer, as taught by Wu, for the method of manufacturing the metal zero layer as taught by Hsiung in view of Cheng. One would have been motivated to do this with a reasonable expectation of success because the metal zero layer may be optimized by a barrier layer and seed layer to prevent diffusion of contaminants and reduce resistance, as suggested by Wu (¶[0061]).
Re Claim 7, (Original) Hsiung teaches the method for manufacturing the metal zero layer according to claim 6, wherein the metal zero layer (First contact structure; 1100; Fig 11A; ¶[0067]) is etched back by means of a wet etching process (Chemical Mechanical Planarization (CMP Process), which includes a slurry or pure wet etch on the material during the chemical phase; ¶[0067]);
However, Hsiung in view of Cheng does not teach wherein the metal zero layer, the first barrier layer, and the second seed layer are etched back.
In the same field of endeavor, Wu teaches wherein the metal zero layer (Contact plugs; 122; Fig 10; Per ¶[0063] contact plugs 122 may comprise of metal bulk layers including Cobalt (Co)), the first barrier layer (Barrier layer (not shown) may be included in contact plugs 122 along sidewall and bottom surface of contact openings; Fig 10; ¶[0061]), and the second seed layer (Seed layers (not shown) may be included in contact plugs 122; Fig 10; ¶[0061]) are etched back (Etched during planarization process; ¶[0060]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the etching process of a metal zero layer, first barrier layer, and seed layer, as taught by Wu, with the wet etching process of the metal zero layer as taught by Hsiung in view of Cheng. One would have been motivated to do this with a reasonable expectation of success because the metal zero layer may be optimized by a barrier layer and seed layer to prevent diffusion of contaminants and reduce resistance (Wu, ¶[0061]) wherein the optimal materials for a barrier and seed layer may require a wet etching process.
17. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiung, Te-Chih et al. (Pub No. US 20220344206 A1) (hereinafter, Hsiung) in view of Cheng, Kangguo et al. (Pub No. US 10236364 B1) (hereinafter, Cheng) as applied to claim 14, and further in view of Lu, Bo-Cyuan et al. (Pub No. US 20230114191 A1) (hereinafter, Lu).
Re Claim 15, (Original) Hsiung teaches the method for manufacturing the metal zero layer according to claim 14, wherein in an area (One of the epitaxial structures 900; Fig 9) for forming a PMOS (P-type transistor with p-doped epitaxial structures 900; ¶[0049]), a material (SiGe; ¶[0048]) of the embedded epitaxial layer comprises SiGe; and in an area (One of the epitaxial structures 900; Fig 9) for forming an NMOS (N-type transistor with n-doped epitaxial structures 900; ¶[0049]).
However, Hsiung does not teach a material of the embedded epitaxial layer comprises SiP.
In the same field of endeavor, Lu teaches a material (Silicon phosphide (SiP); ¶[0020]) of the embedded epitaxial layer (Epitaxy regions; 42; Fig 8C; ¶[0020]) comprises SiP.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a material of the embedded epitaxial layer comprising of SiP, as taught by Lu, with the method of manufacturing the metal zrero layer as taught by Hsiung. One would have been motivated to do this with a reasonable expectation of success because the silicon phosphide epitaxial source/drain regions of Lu would produce tensile stress which would complement the stress of silicon germanium source/drain regions of Hsiung, inducing compressive strain in the p-type transistors to improve hole mobility.
Allowable Subject Matter
18. Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the closest prior art Hsiung, Te-Chih et al. (Pub No. US 20220344206 A1) (hereinafter, Hsiung) and Liao, Chih-Teng (Pub No. US 20190006465 A1) (hereinafter, Liao) either singularly or in combination fails to anticipate or render obvious the limitations
“The method for manufacturing the metal zero layer according to claim 2, wherein in step 2, sub-steps of forming a patterned structure of the cut-off layer comprise:
step 21, performing a first photolithography process, the first photolithography process comprising: sequentially applying a spin on carbon layer and a photoresist, the spin on carbon layer fully filling the inter-gate trench, and performing exposure and development to pattern the photoresist;
step 22, performing a first etching process, the first etching process fully removing the spin on carbon layer in an open area of the patterned photoresist and fully consuming the photoresist;
step 23, forming the low-temperature oxide layer to fully fill the inter-gate trench in an area where the spin on carbon layer is removed; and
step 24, performing a second etching process to remove the carbon coating in the inter-gate trench outside the low-temperature oxide layer,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, Hsiung teaches step 21 of claim 3, however, Hsiung in view of Liao does not teach step 22-24 of claim 3. Liao teaches a second etching process in which a photoresist layer is fully consumed, contrary to the applicant’s claim of a photoresist layer being fully consumed in the first etching process.
Due to the photoresist being fully consumed during a second etching process of Liao, but not a first etching process, it would not be rendered obvious as to why the applicant would combine Hsiung and Liao to fully consume the photoresist during a different etching process.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817