Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-17, 19 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0001281 A1 to Corsi et al. (hereinafter “Corsi” – previously cited reference).
Regarding claim 15, Corsi discloses a wafer, having a first surface and a second surface opposite to the first surface, wherein the first surface of the wafer has a first etching pattern recessed from the first surface (wafer with first and second opposing surfaces and having removal profiles 820, 830 such that the first surface has a concave shape formed by using a chemical etchant; Fig. 8; paragraphs [0027], [0053]), wherein an area of the first etching pattern occupies less than 100% of a total area of the first surface (Figs. 2, 4 and 8).
Corsi fails to disclose wherein an area of the first etching pattern occupies 25% to 85% of a total area of the first surface.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Corsi in this manner in order to potentially provide reduced geometric warpage, improved handling and yield, and enhanced process control and compatibility, particularly given paragraph [0035] of Corsi discloses varying the diameter of the floor 172 within a range that would reduce the near 100% coverage of the etching pattern to a coverage closer to 85%.
Regarding claim 16, Corsi discloses the wafer according to claim 15, wherein the second surface has a convex pattern protruding outwards from the second surface, and a position of the convex pattern corresponds to a position of the first etching pattern of the first surface (second surface has a convex shape corresponding to the concave etching shape of the first surface; Fig. 8; paragraphs [0027], [0053]).
Regarding claim 17, Corsi discloses the wafer according to claim 15, wherein the first etching pattern comprises one or more circles, ellipses, arcs, straight lines, rings, spirals, semicircles, polygons, irregular shapes, or a combination thereof (concave etching shape has an arc; Fig. 8).
Regarding claim 19, Corsi discloses the wafer according to claim 15, wherein an etching depth of the first etching pattern is 1 μm to 1000 μm (chemical etching performed to remove about 1 micron of material; paragraph [0027]).
Regarding claim 23, Corsi discloses the wafer according to claim 15, wherein a position of the first etching pattern corresponds to a stress concentration place of the wafer (concave etching causes structural corner shapes to be formed which correspond to high stress concentrations within the wafer; Fig. 8).
Claims 21-22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0047750 A1 to Kido et al. (hereinafter “Kido” – previously cited reference).
Regarding claim 21, Kido discloses a wafer, having a first surface and a second surface opposite to the first surface, wherein the first surface of the wafer has a convex pattern protruding outwards from the first surface (wafer 100 having first and second opposing surface with convex protrusion on first surface; Fig. 1d; paragraph [0042]), wherein an area of the convex pattern occupies less than 100% of a total area of the first surface (grinding convex surface 100b to flat mirror surface 100d provides an intermediate shape during this process such that the convex surface 100b occupies less than 100% of the total area of the surface 100b; Fig. 1e; paragraph [0047]).
Kido fails to explicitly disclose wherein an area of the convex pattern occupies 25% to 85% of a total area of the first surface.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kido in this manner in order to potentially provide reduced geometric warpage, improved handling and yield, and enhanced process control and compatibility, particularly given Fig. 1e and paragraph [0047] of Kido disclose grinding the convex surface 100b (i.e. 100% coverage) down to a flat surface 100d (i.e. 0% coverage) which necessarily means the surface 100b will occupy all of the range of 25% to 85% of a total area of the surface 100b at various stages of the grinding process. Since Kido arguably discloses this limitation outright, it would be obvious for a person having ordinary skill in the art to cease the grinding process of Kido early to yield the predictable result of the surface 100b occupying between 25% to 85% of a total area of that surface.
Regarding claim 22, Kido discloses the wafer according to claim 21, wherein the second surface has an inward concave pattern recessed from the second surface, and a position of the inward concave pattern corresponds to a position of the convex pattern of the first surface (wafer 100 having concave recess on second surface corresponding to the position of convex protrusion on first surface; Fig. 1d; paragraph [0042]).
Regarding claim 24, Kido discloses the wafer according to claim 21, wherein a position of the convex pattern corresponds to a stress concentration place of the wafer (convex shape of wafer 100 comprises corner shapes to be formed which correspond to high stress concentrations within the wafer 100; Fig. 1d).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Corsi in further view of US 2018/0047614 A1 to Usenko (hereinafter “Usenko” – previously cited reference).
Regarding claim 18, Corsi discloses the wafer according to claim 15. Corsi fails to disclose wherein a ratio of an overall thickness of the wafer to an etching depth of the first etching pattern is 1:0.01 to 1:0.1.
However, Usenko discloses wherein a ratio of an overall thickness of the wafer to an etching depth of the first etching pattern is 1:0.01 to 1:0.1 (wafer thickness of between 250 to 1500 microns and an etching depth of 0.1 to 50 microns, thereby providing ratio of 1:0.01 to 1:0.1; paragraphs [0029]-[0030], [0039]).
Corsi and Usenko are both considered to be analogous to the claimed invention because they are in the same field of wafer etching techniques. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Corsi to incorporate the teaching of Usenko in order to potentially provide effective defect and contaminant removal and preservation of wafer integrity and material efficiency.
Response to Arguments
Applicant's arguments filed December 23, 2025 have been fully considered. Applicant presents substantive amendments to claims 15 and 21 and corresponding arguments. Applicant argues that paragraph [0053] and Fig. 8 of Corsi means that “Corsi only discloses polishing 100% area of the wafer.” Examiner points to Figs. 2 and 4 of Corsi which each show flat edges at the ends of the floor 172 which implies less than 100% coverage of the etching pattern over the first surface and so would lead a person having ordinary skill in the art to contemplate coverage of the etching pattern to a coverage closer to 85%. Further, Applicant does not substantively dispute Examiner’s assertion that paragraph [0035] of Corsi discloses varying the diameter of the floor 172 within a range that would reduce the near 100% coverage of the etching pattern to a coverage closer to 85%, but rather only points to paragraph [0053] and Fig. 8 of Corsi which is not persuasive. Additionally, as described above, Kido arguably discloses outright the limitation at issue which provides clear motivation for a person having ordinary skill in the art to create a wafer with the claimed parameters. Applicant does not provide any specific arguments regarding Kido in this regard. Finally, this feature is not novel in the art generally as illustrated by US 2004/0075073 A1 to Claydon et al., US 2013/0217185 A1 to Wisotzki et al., and US 2016/0101499 A1 to Sventek et al. Moreover, while Applicant provides a statement of unexpected effects regarding new claims 23-24, Corsi and Kido disclose these limitations given the structural corners formed by the concave and convex shapes disclosed therein inherently have higher stress concentrations within the wafers.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818