DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 27, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0001281 A1 to Corsi et al. (hereinafter “Corsi” – previously cited reference).
Regarding claim 15, Corsi discloses a wafer, having a first surface and a second surface opposite to the first surface, wherein the first surface of the wafer has a first etching pattern and a second etching pattern recessed from the first surface (wafer with first and second opposing surfaces and having removal profiles 820, 830 such that the first surface has an outer concave shape and an inner concave shape formed by using a chemical etchant; Fig. 8; paragraphs [0027], [0053]), wherein an area of the first etching pattern occupies less than 100% of a total area of the first surface (Figs. 2, 4 and 8), and wherein an etching depth of the first etching pattern is different from an etching depth of the second etching pattern (inner concave shape has different depth relative outer concave shape; Fig. 8).
Corsi fails to disclose wherein an area of the first etching pattern occupies 25% to 85% of a total area of the first surface.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Corsi in this manner in order to potentially provide reduced geometric warpage, improved handling and yield, and enhanced process control and compatibility, particularly given paragraph [0035] of Corsi discloses varying the diameter of the floor 172 within a range that would reduce the near 100% coverage of the etching pattern to a coverage closer to 85%.
Regarding claim 16, Corsi discloses the wafer according to claim 15, wherein the second surface has a convex pattern protruding outwards from the second surface, and a position of the convex pattern corresponds to a position of the first etching pattern of the first surface (second surface has a convex shape corresponding to the concave etching shape of the first surface; Fig. 8; paragraphs [0027], [0053]).
Regarding claim 17, Corsi discloses the wafer according to claim 15, wherein the first etching pattern comprises one or more circles, ellipses, arcs, straight lines, rings, spirals, semicircles, polygons, irregular shapes, or a combination thereof (concave etching shape has an arc; Fig. 8).
Regarding claim 19, Corsi discloses the wafer according to claim 15, wherein the etching depth of the first etching pattern is 1 μm to 1000 μm (chemical etching performed to remove about 1 micron of material; paragraph [0027]).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0047750 A1 to Kido et al. (hereinafter “Kido” – previously cited reference).
Regarding claim 21, Kido discloses a wafer, having a first surface and a second surface opposite to the first surface, wherein the first surface of the wafer has a convex pattern protruding outwards from the first surface (wafer 100 having first and second opposing surface with convex protrusion on first surface; Fig. 1d; paragraph [0042]), wherein the second surface has a first inward concave pattern and a second inward concave pattern recessed from the second surface (second surface having outer concave shape and inner concave shape; Fig. 1d), wherein an area of the convex pattern occupies less than 100% of a total area of the first surface (grinding convex surface 100b to flat mirror surface 100d provides an intermediate shape during this process such that the convex surface 100b occupies less than 100% of the total area of the surface 100b; Fig. 1e; paragraph [0047]), and wherein an etching depth of the first inward concave pattern is different from an etching depth of the second inward concave pattern (outer concave shape has different depth relative inner concave shape; Fig. 1d).
Kido fails to explicitly disclose wherein an area of the convex pattern occupies 25% to 85% of a total area of the first surface.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Kido in this manner in order to potentially provide reduced geometric warpage, improved handling and yield, and enhanced process control and compatibility, particularly given Fig. 1e and paragraph [0047] of Kido disclose grinding the convex surface 100b (i.e. 100% coverage) down to a flat surface 100d (i.e. 0% coverage) which necessarily means the surface 100b will occupy all of the range of 25% to 85% of a total area of the surface 100b at various stages of the grinding process. Since Kido arguably discloses this limitation outright, it would be obvious for a person having ordinary skill in the art to cease the grinding process of Kido early to yield the predictable result of the surface 100b occupying between 25% to 85% of a total area of that surface.
Regarding claim 22, Kido discloses the wafer according to claim 21, wherein the second surface has an inward concave pattern recessed from the second surface, and a position of the inward concave pattern corresponds to a position of the convex pattern of the first surface (wafer 100 having concave recess on second surface corresponding to the position of convex protrusion on first surface; Fig. 1d; paragraph [0042]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Corsi in further view of US 2018/0047614 A1 to Usenko (hereinafter “Usenko” – previously cited reference).
Regarding claim 18, Corsi discloses the wafer according to claim 15. Corsi fails to disclose wherein a ratio of an overall thickness of the wafer to an etching depth of the first etching pattern is 1:0.01 to 1:0.1.
However, Usenko discloses wherein a ratio of an overall thickness of the wafer to an etching depth of the first etching pattern is 1:0.01 to 1:0.1 (wafer thickness of between 250 to 1500 microns and an etching depth of 0.1 to 50 microns, thereby providing ratio of 1:0.01 to 1:0.1; paragraphs [0029]-[0030], [0039]).
Corsi and Usenko are both considered to be analogous to the claimed invention because they are in the same field of wafer etching techniques. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Corsi to incorporate the teaching of Usenko in order to potentially provide effective defect and contaminant removal and preservation of wafer integrity and material efficiency.
Response to Arguments
Applicant's arguments filed May 27, 2026 have been fully considered. Applicant presents substantive amendments to claims 15 and 21 and corresponding arguments. Applicant again asserts that Corsi only discloses polishing 100% area of the wafer. Examiner again points to Figs. 2 and 4 of Corsi which each show flat edges at the ends of the floor 172 which implies less than 100% coverage of the etching pattern over the first surface and so would lead a person having ordinary skill in the art to contemplate coverage of the etching pattern to a coverage closer to 85%. In response to Examiner’s assertion that paragraph [0035] of Corsi discloses varying the diameter of the floor 172 within a range that would reduce the near 100% coverage of the etching pattern to a coverage closer to 85%, Applicant asserts that “Corsi fails to disclose or teach that the diameter of the wafer W can be larger than that of the floor 172.” By Applicant’s same logic, Examiner notes that Corsi fails to disclose or teach that the diameter of the wafer W is equal to or lesser than that of the floor 172. To support this, Examiner points to Applicant’s statement that according to Fig. 1 of Corsi “the diameter of the wafer W plus the width of the retaining ring 120 is approximately equal to the diameter of the floor.” This provides more support for Corsi suggesting less than 100% coverage of the etching pattern over the first surface. Additionally, regarding Applicant’s assertion that the mirror surface of Kido’s wafer means that those skilled in the art would have no motivation to cease grinding to less than 100% coverage. However, the mirror surface disclosed by Kido does not contemplate a surface area coverage of the wafer. Examiner again notes that Kido arguably discloses outright the limitation at issue which provides clear motivation for a person having ordinary skill in the art to create a wafer with the claimed parameters. Finally, Applicant again notes that this feature is not novel in the art generally as illustrated by US 2004/0075073 A1 to Claydon et al., US 2013/0217185 A1 to Wisotzki et al., and US 2016/0101499 A1 to Sventek et al. Regarding the amendments to claims 15 and 21, each of Corsi and Kido can be interpreted to have a first and second etching pattern defined by different portions (e.g. outer and inner) of the concave surface of each wafer which provides for different etching depths. Examiner suggests amending these limitations further to differentiate between the scope of the current claim language and the disclosure of Corsi and Kido.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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