Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on October 20, 2025. Claims 16-35 are examined below.
Claim Objections
Claim 16 is objected to because of the following informalities:
The amended part of claim 16 should be: “wherein the epitaxial layers are in direct contact with the first inner spacers”, which will correct a typo in the claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) in view of Shin et al. (US-20210257499-A1 referred as Shin).
Regarding claim 16. Huang discloses a method for manufacturing a semiconductor structure, comprising:
alternately stacking first semiconductor material layers and second semiconductor material layers to form a semiconductor stack over a substrate ([0077], figure 1a, alternately stacking first semiconductor material layers #106 and second semiconductor material layer #108 to form a semiconductor stack over a substrate #102);
patterning the semiconductor stack to form a fin structure ([0094], figure 1b, patterning the semiconductor stack to form a fin structure #104);
forming a dummy gate structure across the fin structure ([0032], figure 1d, forming a dummy gate structure #118 across the fin structure #104);
forming source/drain trenches in the fin structure at opposite sides of the dummy gate structure ([0040-0041], figure 1e to figure 2a-2b, it is noted that figure 2a and onwards are side views of figure 1e, etching the fin structure #104 at opposite sides of the dummy gate structure #118 to form a source/drain trench #130);
recessing the first semiconductor material layers from the source/drain trenches to form notches between the second semiconductor material layers ([0044], figure 2c, recessing the first semiconductor material layer #106 to form notches #132 between the second semiconductor material layers #108);
forming first inner spacers covering inner sidewalls of the notches ([0046], figure 2d, forming inner spacers covering the inner sidewalls of the notches #132);
Huang lacks forming epitaxial layers laterally grown from the second semiconductor material layers, wherein the epitaxial layers in direct contact with the first inner spacers; and forming second inner spacers in the notches after the epitaxial layers are formed.
Shin discloses forming epitaxial layers laterally grown from the second semiconductor material layers ([0076], figure 14, forming epitaxial layers #200 laterally grown from the second semiconductor material layer #124), wherein the epitaxial layers in direct contact with the first inner spacers ([0081], figure 16, wherein the epitaxial layers #200 are in direct contact with the first inner spacers #290. As described in [0028], the first inner spacers #290 are the first to be formed which is seen having direct contact with the epitaxial layer #200); and forming second inner spacers in the notches after the epitaxial layers are formed ([0081], figure 16, forming second inner spacers #300 in the notches #270 after the epitaxial layers #200 are formed. Please note the second inner spacer #300 is formed after the formation of the first inner spacer #290 and the epitaxial layer #200 is formed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang to include the epitaxial layers and second inner spacers as taught by Shin in order to enhance durability for high stress components, increase device lifetime, and to reduce manufacturing costs.
Regarding claim 17. Huang as modified lacks forming porous material cores in the notches after forming the epitaxial layers and before forming the second inner spacers.
Shin discloses forming porous material cores in the notches after forming the epitaxial layers ([0081] [0027], figure 14 and figure 16, forming porous material cores #300 (fig 16) in the notches #270 after forming the epitaxial layer #200 in figure 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include forming the porous material cores after forming the epitaxial layers as taught by Shin in order to enhance compactness of the device, increase the structural integrity, and to offer greater device versatility.
Shin still lacks specifically forming porous material cores in the notches before forming the second inner spacers.
Shin as modified does disclose forming the porous material cores and the second inner spacers, just not in a specific order ([0081] [0027], figure 14 and figure 16, although not illustrated- it is specified that the porous material cores #300 and the second inner spacers #290 would be formed in a sequential matter).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Shin to include forming the porous material cores before forming the second inner spacers in order to reduce the dielectric constant within the structure which is influenced by the porous material, and also to reduce warping during the deposition phase which allows enhancing the structural integrity of the device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) and Shin et al. (US-20210257499-A1 referred as Shin) as applied to claim 16, in further view of Yang et al. (US-20200052086-A1).
Regarding claim 18. Huang as modified lacks wherein an air gap is embedded in the second inner spacers.
Yang et al. discloses wherein an air gap is embedded in the second inner spacers ([0054], figure 1a-1c, the air gap #37 is embedded in the second inner spacer #33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include air gap is embedded in the second inner spacers as taught by Yang et al. in order to reduce materials in manufacturing, manufacturing costs, and to enhance signal integrity.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) and Shin et al. (US-20210257499-A1 referred as Shin) as applied to claim 16, in further view of Kim et al. (US-20220085028-A1 referred as Kim).
Regarding claim 19. Huang as modified lacks forming a first inner spacer layer covering the notches, the source/drain trenches, and the dummy gate structure;
partially removing the first inner spacer layer to form the first inner spacers in the notches;
forming a second inner spacer layer in the notches and covering the epitaxial layers, the source/drain trenches, and the dummy gate structure; and
partially removing the second inner spacer layer to form the second inner spacers in the notches.
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Kim discloses forming a first inner spacer layer covering the notches, the source/drain trenches, and the dummy gate structure ([0096], figure 7-8 annotated above, forming a first inner spacer layer #151p covering the notches #136t, the source drain trenches #S/D-Trench, and the dummy gate structure #134);
partially removing the first inner spacer layer to form the first inner spacers in the notches ([0104], figure 10-11, the first inner spacer layer #151p is partially removed to form the first inner spacers #151);
forming a second inner spacer layer in the notches and covering the epitaxial layers, the source/drain trenches, and the dummy gate structure ([0110], figure 12-13, forming the second inner spacer layer #154p in the notches #136t and #140t covering the epitaxial layers #141); and
partially removing the second inner spacer layer to form the second inner spacers in the notches ([0113], figure 13-14, partially removing the second inner spacer layer #154p to form the second inner spacers #154 in the notches #136t and #140t).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include the process of depositing and partially removing the first inner spacer and the second inner spacer as taught by Kim in order to reduce the total weight of the device, reduce manufacturing costs, and to enhance the compactness of the device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) and Shin et al. (US-20210257499-A1 referred as Shin) as applied to claim 16, in further view of Do et al. (US-20100155847-A1 referred as Do).
Regarding claim 20. Huang as modified discloses removing the dummy gate structure and the first semiconductor material layers to form a gate trench, wherein the first inner spacers are exposed by the gate trench ([0064], figure 2g and figure 2i, removing the dummy gate structure #118 and the first semiconductor material layer #106 to form a gate trench of #148 and #150, wherein the first inner spacers #134 are exposed by the gate trench); and
forming a gate structure in the gate trench ([0066], figure 2J, forming a gate structure #152 in the gate trench #148 and #150).
Huang as modified lacks wherein the first inner spacers are laterally sandwiched between the gate structure and the second inner spacer.
Do discloses wherein the first inner spacers are laterally sandwiched between the gate structure and the second inner spacer ([0030], figure 1, the first inner spacers #144 are laterally sandwiched between the gate structure #152a and the second inner spacer #146).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include the first inner spacers laterally sandwiched between the gate structure and the second inner spacer as taught by Do in order to spread out the electrical isolation, reduce device failure, and to increase the devices lifetime.
Claims 21, and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) in view of Kim et al. (US-20220085028-A1 referred as Kim) and Shin et al. (US-20210257499-A1 referred as Shin).
Regarding claim 21. Huang discloses a method for manufacturing a semiconductor structure, comprising:
alternately stacking first semiconductor material layers and second semiconductor material layers to form a semiconductor stack over a substrate ([0077], figure 1a, alternately stacking first semiconductor material layers #106 and second semiconductor material layers #108 to form a semiconductor stack over a substrate #102);
patterning the semiconductor stack to form a fin structure extending in a first direction ([0094], figure 1b, patterning the semiconductor stack to form a fin structure #104 extending in a first direction);
forming an isolation structure around the fin structure, wherein the isolation structure interfaces an end portion of fin structure ([0030], figure 1c, the isolation structure #116 is formed around the fin structure #104, wherein the isolation structure #116 interfaces an end portion of the fin structure at #104b);
forming a dummy gate structure across the fin structure and extending in a second direction that is different from the first direction ([0032], figure 1d, the dummy gate structure #118 is formed across the fin structure #104 in a second direction that is different from the first direction);
forming a source/drain trench in the fin structure ([0040-0041], figure 1e to figure 2a-2b, it is noted that figure 2a and onwards are side views of figure 1e, forming source/drain trenches #130 in the fin structure #104);
recessing the first semiconductor material layers from the source/drain trench to form notches between the second semiconductor material layers ([0044], figure 2c, recessing the first semiconductor material layers #106 from the source/drain trench #130 to form notches #132 between the second semiconductor material layers #108); and
forming a source/drain structure in the source/drain trench ([0054], figure 2f, source/drain structure #142 is formed within the source/drain trench #130).
Huang lacks wherein the isolation structure has a non-planar top surface; and
forming a first inner spacer layer covering sidewalls of the first semiconductor material layers and sidewalls of the second semiconductor material layers;
removing the first inner spacer layer outside the notches to form first inner spacers in the notches so that a topmost portion of the first inner spacers is lower than a top surface of a topmost one of the second semiconductor material layers;
forming second inner spacers in the notches to cover the first inner spacers after removing the first inner spacer layer outside the notches.
Kim discloses wherein the isolation structure has a non-planar top surface ([0024], figure 7, the isolation structure #105 has a nonplanar top surface); and
forming a first inner spacer layer covering sidewalls of the first semiconductor material layers and sidewalls of the second semiconductor material layers ([0099], figure 8, forming a first inner spacer layer #151p covering sidewalls of the first semiconductor material layers #133 and the second semiconductor material layers #131);
removing the first inner spacer layer outside the notches to form first inner spacers in the notches ([0107], figure 11, removing the first inner spacer #151p outside the notches #136t to form first inner spacers #151 in the notches #136t);
forming second inner spacers in the notches to cover the first inner spacers after removing the first inner spacer layer outside the notches ([0113], figure 13, forming second inner spacers #154p in the notches #136t to cover the first inner spacer #151 after removing the first inner spacer layer #151p outside the notches).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang to include the process of depositing the modified first inner spacer, nonplanar isolation structure, and a second inner spacer as taught by Kim in order to reduce the total weight of the device, reduce manufacturing costs, and to enhance the compactness of the device.
Huang as modified by Kim still lacks a topmost portion of the first inner spacers is lower than a top surface of a topmost one of the second semiconductor material layers.
Shin discloses a topmost portion of the first inner spacers is lower than a top surface of a topmost one of the second semiconductor material layers ([0027], figure 16, a topmost portion of the first inner spacers #290 is lower than a top surface of a topmost one of the second semiconductor material layers #124).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang to include a topmost portion of the first inner spacers is lower than a top surface of a topmost one of the second semiconductor material layers as taught by Shin in order to enhance the compactness of the device, allow for additional elements in the device, and to reduce manufacturing materials.
Regarding claim 23. Huang as modified lacks forming epitaxial layers on sidewalls of the second semiconductor material layers after forming the first inner spacers and before forming the second inner spacers.
Shin discloses forming epitaxial layers on sidewalls of the second semiconductor material layers after forming the first inner spacers and before forming the second inner spacers ([0090-0091], figure 10 illustrates forming the first inner spacers first #185, figure 11 illustrates the epitaxial layers #200 formed on the sidewalls of the second semiconductor layer #124, figure 13 illustrates forming the second inner spacers #260).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to forming epitaxial layers on sidewalls of the second semiconductor material layers after forming the first inner spacers and before forming the second inner spacers as taught by Shin in order to enhance the structure in the device, increase protection, and optimize weight distribution.
Regarding claim 24. Huang as modified lacks wherein the epitaxial layers extend into the notches.
Kim discloses wherein the epitaxial layers extend into the notches ([0110], figure 11-12, the epitaxial layers #141 extend into the notches #136t).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include the epitaxial layers extend into the notches as taught by Kim in order to increase manufacturing speed, provide additional protection, and to distribute weight across the device.
Regarding claim 25. Huang as modified lacks forming a second inner spacer layer in the notches and covering the epitaxial layers; and partially removing the second inner spacer layer to form the second inner spacers in the notches.
Kim discloses forming a second inner spacer layer in the notches and covering the epitaxial layers; and partially removing the second inner spacer layer to form the second inner spacers in the notches ([0113], figure 13-14, forming second inner spacer layer #154p in the notches #136t and covering the epitaxial layers #141. And partially removing the second inner spacer layer #154p to form the second inner spacers #154 in the notches #136t).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include second inner spacers into the notches as taught by Kim in order to reduce materials in manufacturing, provide electrical insulation, and to distribute weight across the device.
Regarding claim 26. Huang as modified lacks wherein portions of the epitaxial layers extend into the second inner spacers.
Kim discloses wherein portions of the epitaxial layers extend into the second inner spacers ([0116], figure 15, portions of the epitaxial layers #142 extend into the second inner spacers #154).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include portions of the epitaxial layers extend into the second inner spacers as taught by Kim in order to provide additional electrical insulation, enhance reliability, and to provide thermal management.
Claims 22 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang), Kim et al. (US-20220085028-A1 referred as Kim) and Shin et al. (US-20210257499-A1 referred as Shin) as applied to claim 21 in further view of Yang et al. (US-20200052086-A1).
Regarding claim 22. Huang as modified lacks wherein a width of one of the inner spacers in the first direction is smaller than a width of one of the notches in the first direction.
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Yang et al. discloses wherein a width of one of the inner spacers in the first direction is smaller than a width of one of the notches in the first direction ([0120], figure 15a-16a annotated above illustrates the width of a notch #N1 in the first direction #X. figure 22a illustrates the elements inside the notch #N1 which includes a first inner spacer #35 which has a smaller width than the width of the notch #N1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include the inner spacers having a smaller width than one of the notches as taught by Yang et al. in order to provide additional room for other elements and to reduce materials in manufacturing.
Regarding claim 27. Huang as modified lacks wherein air gaps are embedded in the second inner spacers.
Yang et al. discloses wherein air gaps are embedded in the second inner spacers ([0120], figure 22a, there are airgaps #37 embedded in the second inner spacers #33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include air gaps are embedded in the second inner spacers as taught by Yang et al. in order to provide additional capacitance insulation in the device, reduce weight in the device, and to increase manufacturing speed.
Claims 28-31 and 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) in view of Shin et al. (US-20210257499-A1 referred as Shin) and Song et al. (US-20220254781-A1 referred as Song).
Regarding claim 28. Huang discloses a method for manufacturing a semiconductor structure, comprising:
forming a fin structure protruding from a substrate, the fin structure comprises alternately stacked first semiconductor material layers and second semiconductor material layers ([0094], figure 1a-1b, forming a fin structure #104 protruding from a substrate #102, the fin structure #104 comprises of alternating first semiconductor material #106 and second semiconductor material #108);
forming an isolation structure adjacent to the fin structure ([0030], figure 1c, the isolation structure #116 is formed adjacent to the fin structure by a common endpoint);
forming a dummy gate structure across the fin structure ([0032], figure 1d, the dummy gate structure #118 is formed across the fin structure #104);
forming gate spacers on sidewalls of the dummy gate structure ([0037], figure 1e, forming gate spacers #126 on sidewalls of the dummy gate structure #118);
etching the fin structure not covered by the dummy gate structure and the gate spacers to form a source/drain trench ([0040-0041], figure 1e to figure 2a-2b, it is noted that figure 2a and onwards are side views of figure 1e, etching the fin structure #104 not covered by the dummy gate structure #118 and gate spacers #126 to form a source/drain trench #130);
forming notches between the second semiconductor material layers of the fin structure and under the gate spacers ([0044], figure 2c, forming notches #132 between the second semiconductor material layers #108 of the fin structure #104 and under the gate spacers #126);
forming first inner spacers covering sidewalls of the first semiconductor material layers exposed by the notches ([0046], figure 2d, forming first inner spacers #134 covering sidewalls of the first semiconductor materials layers #106 exposed by the notches #132);
forming a source/drain structure in the source/drain trench, wherein the source/drain structure comprises first layers interfacing with the epitaxial layers ([0054], figure 2f, forming source/drain structure #142 in the source/drain trench #130 wherein the source/drain structure #142 comprises first layers #142 interfacing with the epitaxial layers #136);
forming a contact etch stop layer over the source/drain structure and the gate spacers ([0059], figure 2g, forming contact etch stop layer #144 over the source/drain structure #142 and gate spacers #126);
removing the dummy gate structure and the first semiconductor material layers to form a gate trench ([0064], figure 2i, removing the dummy gate structure #118 and the first semiconductor material layer #106 to form a gate trench #148 and #150);
forming a gate structure in the gate trench, wherein the gate structure comprises a gate dielectric layer extending over the second semiconductor material layers and the isolation structure, and the gate spacers are sandwiched between the gate dielectric layer and the contact etch stop layer ([0066], figure 2J, forming a gate structure #152 in the gate trench #148 and #150 wherein the gate structure comprises of a gate dielectric #156 extending over the second semiconductor material layers #108 and the isolation structure #116, and the gate spacers #126 are sandwiched between the gate dielectric layer #156 and the contact etch stop layer #144).
Huang lacks forming epitaxial layers on sidewalls of the second semiconductor material layers;
forming second inner spacers covering both the first inner spacers and the epitaxial layers; and wherein the source/drain structure comprises of second layers interfacing with the second inner spacers.
Shin discloses forming epitaxial layers on sidewalls of the second semiconductor material layers ([0065], figure 11, forming epitaxial layers #200 on the sidewalls of the second semiconductor material layers #124); forming second inner spacers in direct contact with both the first inner spacers and the epitaxial layers ([0028], figure 16, forming second inner spacers #290 in direct contact with both the first inner spacer #300 and the epitaxial layers #200);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang to include the epitaxial layers and second inner spacers with coverage on the second semiconductor material layers and the first inner as taught by Shin in order to enhance durability for high stress components, increase device lifetime, and to reduce manufacturing costs.
Huang as modified by Shin still lacks wherein the source/drain structure comprises of second layers interfacing with the second inner spacers.
Song discloses wherein the source/drain structure comprises of second layers interfacing with the second inner spacers ([0048], figure 10a, the source/drain structure #SD1 comprises of second layers #SEL1 interfacing the second inner spacers #GI which surrounds the first semiconductor layers #IGEa).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified by Shin to include a source/drain structure with a second layer as taught by Song in order to improve device performance, reduce power consumption, and enhance the durability of the device.
Regarding claim 29. Huang as modified lacks wherein the first layers and the second layers of the source/drain structure comprise different materials.
Song discloses wherein the first layers and the second layers of the source/drain structure comprise different materials ([0033-0034], figure 10a, the first layer #SEL2 and the second layer #SEL1 of the source/drain structure #SD1 may have an embodiment of #SEL2 containing Ge and #SEL1 containing Si which are different materials).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include a source/drain structure with a second layer as taught by Song in order to improve device performance, reduce power consumption, and enhance the durability of the device.
Regarding claim 30. Huang as modified discloses forming porous material cores after forming the epitaxial layers and before forming the second inner spacers ([0061], figure 2G, forming porous material cores #146 after forming the epitaxial layers #136 before forming the second inner spacers).
Regarding claim 31. Huang as modified lacks wherein the porous material cores are laterally sandwiched between the first inner spacers and the second inner spacers.
Shin discloses wherein the porous material cores are laterally sandwiched between the first inner spacers and the second inner spacers ([0028], figure 3, porous material cores #300 are laterally sandwiched between the first inner spacer #310 and the second inner spacer #290).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include porous material cores laterally sandwiched between the first inner spacers and the second inner spacers as taught by Shin in order to increase the device lifetime, offer greater device versatility, and to increase device protection.
Regarding claim 34. Huang as modified lacks wherein the first inner spacers and the gate dielectric layer have curved interface.
Shin discloses wherein the first inner spacers and the gate dielectric layer have curved interface ([0030], figure 3, the first inner spacers #310 and the gate dielectric layer #230 contain an interface which is curved).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include porous material cores laterally sandwiched between the first inner spacers and the second inner spacers as taught by Shin in order to increase the device lifetime, offer greater device versatility, and to increase device protection.
Regarding claim 35. Huang as modified lacks wherein portions of the second inner spacers are laterally sandwiched between the epitaxial layers and the first layers of the source/drain structure.
Shin discloses wherein portions of the second inner spacers are laterally sandwiched between the epitaxial layers and the first layers of the source/drain structure ([0032], figure 3, portions of the second inner spacer #290 are sandwiched between the epitaxial layer #200 and the first layer of source/drain structure #210 (the element #210 comes from #220 which is part of a source/drain layer)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include porous material cores laterally sandwiched between the first inner spacers and the second inner spacers as taught by Shin in order to increase the device lifetime, offer greater device versatility, and to increase device protection.
Claims 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang), Shin et al. (US-20210257499-A1 referred as Shin), and Song et al. (US-20220254781-A1 referred as Song), in further view of Huang et al. (US-20200006389-A1 referred as Huang #2).
Regarding claim 32. Huang as modified lacks wherein the second inner spacers are laterally sandwiched between the porous material cores and the second layers of the source/drain structure.
Huang #2 discloses wherein the second inner spacers are laterally sandwiched between the porous material cores and the second layers of the source/drain structure ([0037], figure 28a, the second inner spacer #118 is laterally sandwiched between the porous material cores #120 and the second layer of the source).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include the second inner spacers as sandwiched between the porous material cores and the second layers of the source/drain structure as taught by Huang #2 in order to increase the device lifetime, offer greater device versatility, and to increase device protection.
Regarding claim 33. Huang as modified lacks wherein the second layers of the source/drain structure interface with the gate spacers.
Huang #2 discloses wherein the second layers of the source/drain structure interface with the gate spacers ([0089], figure 28a, the second layers of the source/drain structure #146 includes an interface with the gate spacers #156).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include the second layers of the source/drain structure with an interface to the gate spacers as taught by Huang #2 in order to increase device integrity, distribute weight across the device, and to increase electrical insulation.
Response to Amendment
Applicant's arguments filed 03/13/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art to Huang et al. in combination with Shin et al. as already previously used. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below. Claim 21, was rejected with a different combination based on the amended subject matter, while in the interview this amendment appeared to overcome the cited prior art, upon further review and using broadest reasonable interpretation a different combination of the cited art appears to still read on the amended claim.
For claim 20 … "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Huang et al. in combination with newly cited reference to Do et al. has been presented with regard to claim 20."
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818