Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/25/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) in view of Shin et al. (US-20230253449-A1 referred as Shin, new reference cited).
Regarding claim 16. Huang discloses a method for manufacturing a semiconductor structure, comprising:
alternately stacking first semiconductor material layers and second semiconductor material layers to form a semiconductor stack over a substrate ([0077], figure 1a, alternately stacking first semiconductor material layers #106 and second semiconductor material layer #108 to form a semiconductor stack over a substrate #102);
patterning the semiconductor stack to form a fin structure ([0094], figure 1b, patterning the semiconductor stack to form a fin structure #104);
forming a dummy gate structure across the fin structure ([0032], figure 1d, forming a dummy gate structure #118 across the fin structure #104);
forming source/drain trenches in the fin structure at opposite sides of the dummy gate structure ([0040-0041], figure 1e to figure 2a-2b, it is noted that figure 2a and onwards are side views of figure 1e, etching the fin structure #104 at opposite sides of the dummy gate structure #118 to form a source/drain trench #130);
recessing the first semiconductor material layers from the source/drain trenches to form notches between the second semiconductor material layers ([0044], figure 2c, recessing the first semiconductor material layer #106 to form notches #132 between the second semiconductor material layers #108);
forming first inner spacers covering sidewalls of the first semiconductor material layers ([0046], figure 2d, forming inner spacers #134 covering the sidewalls of the first semiconductor material layers #106);
Huang lacks forming epitaxial layers laterally grown from the second semiconductor material layers after the first inner spacers are formed, wherein the epitaxial layers in direct contact with the first inner spacers; and forming second inner spacers in the notches after the epitaxial layers are formed.
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Shin discloses forming epitaxial layers laterally grown from the second semiconductor material layers after the first inner spacers are formed ([0234-0235, 0238], figure 34-35, forming epitaxial layers #350 laterally grown from the second semiconductor material layer #NS3); and forming second inner spacers in the notches after the epitaxial layers are formed ([0234-0235], figure 35 annotated above, forming second inner spacers #ISP1-GS3/ISP2-GS3/ISP3-GS3 in the notches seen in figure 34 after the epitaxial layers #350 are formed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang to include the epitaxial layers and second inner spacers as taught by Shin in order to enhance durability for high stress components, increase device lifetime, and to reduce manufacturing costs.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) and Shin et al. (US-20230253449-A1 referred as Shin) in further view of Shin et al. (US-20210257499-A1 referred as Shin #2).
Regarding claim 17. Huang as modified lacks forming porous material cores in the notches after forming the epitaxial layers and before forming the second inner spacers.
Shin #2 discloses forming porous material cores in the notches after forming the epitaxial layers ([0081] [0027], figure 14 and figure 16, forming porous material cores #300 (fig 16) in the notches #270 after forming the epitaxial layer #200 in figure 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include forming the porous material cores after forming the epitaxial layers as taught by Shin #2 in order to enhance compactness of the device, increase the structural integrity, and to offer greater device versatility.
Shin #2 still lacks specifically forming porous material cores in the notches before forming the second inner spacers.
Shin #2 as modified does disclose forming the porous material cores and the second inner spacers, just not in a specific order ([0081] [0027], figure 14 and figure 16, although not illustrated- it is specified that the porous material cores #300 and the second inner spacers #290 would be formed in a sequential matter).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Shin #2 to include forming the porous material cores before forming the second inner spacers in order to reduce the dielectric constant within the structure which is influenced by the porous material, and also to reduce warping during the deposition phase which allows enhancing the structural integrity of the device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) and Shin et al. (US-20230253449-A1 referred as Shin) as applied to claim 16, in further view of Yang et al. (US-20200052086-A1).
Regarding claim 18. Huang as modified lacks wherein an air gap is embedded in the second inner spacers.
Yang et al. discloses wherein an air gap is embedded in the second inner spacers ([0054], figure 1a-1c, the air gap #37 is embedded in the second inner spacer #33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include air gap is embedded in the second inner spacers as taught by Yang et al. in order to reduce materials in manufacturing, manufacturing costs, and to enhance signal integrity.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) and Shin et al. (US-20230253449-A1 referred as Shin) as applied to claim 16, in further view of Kim et al. (US-20220085028-A1 referred as Kim).
Regarding claim 19. Huang as modified lacks forming a first inner spacer layer covering the notches, the source/drain trenches, and the dummy gate structure;
partially removing the first inner spacer layer to form the first inner spacers in the notches;
forming a second inner spacer layer in the notches and covering the epitaxial layers, the source/drain trenches, and the dummy gate structure; and
partially removing the second inner spacer layer to form the second inner spacers in the notches.
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Kim discloses forming a first inner spacer layer covering the notches, the source/drain trenches, and the dummy gate structure ([0096], figure 7-8 annotated above, forming a first inner spacer layer #151p covering the notches #136t, the source drain trenches #S/D-Trench, and the dummy gate structure #134);
partially removing the first inner spacer layer to form the first inner spacers in the notches ([0104], figure 10-11, the first inner spacer layer #151p is partially removed to form the first inner spacers #151);
forming a second inner spacer layer in the notches and covering the epitaxial layers, the source/drain trenches, and the dummy gate structure ([0110], figure 12-13, forming the second inner spacer layer #154p in the notches #136t and #140t covering the epitaxial layers #141); and
partially removing the second inner spacer layer to form the second inner spacers in the notches ([0113], figure 13-14, partially removing the second inner spacer layer #154p to form the second inner spacers #154 in the notches #136t and #140t).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include the process of depositing and partially removing the first inner spacer and the second inner spacer as taught by Kim in order to reduce the total weight of the device, reduce manufacturing costs, and to enhance the compactness of the device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) and Shin et al. (US-20230253449-A1 referred as Shin) as applied to claim 16, in further view of Do et al. (US-20100155847-A1 referred as Do).
Regarding claim 20. Huang as modified discloses removing the dummy gate structure and the first semiconductor material layers to form a gate trench, wherein the first inner spacers are exposed by the gate trench ([0064], figure 2g and figure 2i, removing the dummy gate structure #118 and the first semiconductor material layer #106 to form a gate trench of #148 and #150, wherein the first inner spacers #134 are exposed by the gate trench); and
forming a gate structure in the gate trench ([0066], figure 2J, forming a gate structure #152 in the gate trench #148 and #150).
Huang as modified lacks wherein the first inner spacers are laterally sandwiched between the gate structure and the second inner spacer.
Do discloses wherein the first inner spacers are laterally sandwiched between the gate structure and the second inner spacer ([0030], figure 1, the first inner spacers #144 are laterally sandwiched between the gate structure #152a and the second inner spacer #146).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include the first inner spacers laterally sandwiched between the gate structure and the second inner spacer as taught by Do in order to spread out the electrical isolation, reduce device failure, and to increase the devices lifetime.
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US-20210202742-A1 referred as Huang) and Shin et al. (US-20230253449-A1 referred as Shin) in further view of More et al. (US-20210273099-A1 referred as More).
Regarding claim 36. Huang as modified lacks wherein the epitaxial layers cover sidewalls and partially cover bottom surfaces and top surfaces of the second semiconductor material layers.
More discloses wherein the epitaxial layers cover sidewalls and partially cover bottom surfaces and top surfaces of the second semiconductor material layers ([0036], figure 1a, the epitaxial layer #50 covers sidewalls and partially cover bottom surfaces and top surfaces of the second semiconductor material layers #25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Huang as modified to include wherein the epitaxial layers cover sidewalls and partially cover bottom surfaces and top surfaces of the second semiconductor material layers as taught by More in order to have an enhanced doping profiles, enhanced thermal management, and for additional flexibility in device design.
Allowable Subject Matter
Claims 21-23, 25-28, 30-33, 35, and 37-38 are allowed.
In regard to claim 21, the prior art does not teach or render obvious removing the first inner spacer layer outside the notches to form first inner spacers in the notches so that a topmost portion of the first inner spacers is lower than a top surface of a topmost one of the second semiconductor material layers, wherein sidewalls of the first inner spacers are indented from sidewalls of the second semiconductor material layers; forming second inner spacers in the notches to cover the first inner spacers after removing the first inner spacer layer outside the notches and in the combination as claimed.
Claims 22-23, and 25-27 further limit allowable claim 21, therefore, are also allowable.
In regard to claim 28, the prior art does not teach or render obvious forming first inner spacers covering sidewalls of the first semiconductor material layers exposed by the notches; forming epitaxial layers on sidewalls of the second semiconductor material layers, wherein the epitaxial layers comprise a first one of the epitaxial layers formed on a first one of the second semiconductor material layers and a second one of the epitaxial layers formed on a second one of the second semiconductor material layers, and the first one of the epitaxial layers is vertically spaced apart from the second one of the epitaxial layers; forming second inner spacers covering both the first inner spacers and the epitaxial layers and in the combination as claimed.
Claims 30-33, 35, and 37-38 further limit allowable claim 28, therefore, are also allowable.
Response to Amendment
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art to Huang et al. in combination with newly cited art of Shin et al.. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Regarding claim 16 in pages 10 – 11 of the arguments … "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Huang et al. in combination with newly cited reference to Shin et al. has been presented with regard to claim 16."
Regarding claims 21 and 28 in pages 12 – 16 of the arguments … "Applicant's amendments and arguments were persuasive. Upon further search and consideration, claim 21 and claim 28 are deemed allowable since they go around cited art."
Conclusion
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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