DETAILED ACTION
This application, 18/178,406, attorney docket P20222797US01, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Taiwan Semiconductor Manufacturing Company, Ltd., and has an effective filing date of 3/03/2023 based on application date.
Applicant's election with traverse of invention group I, claims 1-16 in the reply filed on 11/19/2025 is acknowledged. The traversal is on the ground(s) that examining both groups presents no undue burden on the examiner. This is not found persuasive because examiner determined that the inventions are distinct and will require searches in different databases and different subclasses. Each subclass may contain thousands of patents and may take several hours to review and examiner is given a limited time to prosecute each case. See MPEP §808.02. Where the inventions as claimed are shown to be independent or distinct under the criteria of MPEP § 806.05(c) - § 806.06, the examiner, in order to establish reasons for insisting upon restriction, must explain why there would be a serious burden on the examiner if restriction is not required. Thus, the examiner must show by appropriate explanation one of the following:
(A) Separate classification thereof: This shows that each invention has attained recognition in the art as a separate subject for inventive effort, and also a separate field of search. Patents need not be cited to show separate classification.
(B) A separate status in the art when they are classifiable together: Even though they are classified together, each invention can be shown to have formed a separate subject for inventive effort when the examiner can show a recognition of separate inventive effort by inventors. Separate status in the art may be shown by citing patents which are evidence of such separate status, and also of a separate field of search.
(C) A different field of search: Where it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s) (e.g., searching different classes/subclasses or electronic resources, or employing different search queries, a different field of search is shown, even though the two are classified together.
The indicated different field of search must in fact be pertinent to the type of subject matter covered by the claims. Patents need not be cited to show different fields of search. Here examiner has determined that the classification and field of search will not be the same. The requirement is affirmed as proper and is therefore made FINAL.
Claims 17-20 are withdrawn from examination. Claims 1-16 and 21-24 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 1 recites, “wherein a first number of the first nanostructures directly below the gate spacer layer is greater than a second number of the first nanostructures directly below the first gate structure.” There is no support for a greater number of nanosheets under the spacer than the gate, because when the nanosheet is partially removed as shown in figure 4B, the process forms a separate element under the spacers, which is the rectangle shown in some of the figures, which can no longer be construed as a nanostructure. Examiner notes that spacer 126 is defined as a separate element from inner spacers 134, even though they appear to be formed simultaneously. One skilled is a FET design engineer who would interpret the nanostructure to be a semiconductor layer that forms a channel.
Dependent claims include the same defect as the parent.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4 and 5 and 13 and 14 are rejected under 35 U.S.C. 112(b) second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4 and 13 recites, “a bottom surface of the continuous sidewall surface of the first gate structure.” A “surface” is two dimensional, and cannot have a bottom surface.
Dependent claims include the same defect as the parent.
Drawings
The drawings are objected to because figures in series 3 view -3 c1-c1’ show a top nanostructure that is cut and disappears, but reappears without explanation. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9 and 21-14 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Metha et al. (U.S. 2023/0402520).
As for claim 1,
Mehta teaches in figure 16C, a semiconductor structure, comprising:
first nanostructures (108) formed over a substrate along a first direction (across the page;
a first gate structure (140) formed over the first nanostructures along a second direction (into the page); and
a gate spacer layer (128) formed adjacent to the first gate structure,
wherein a first number of the first nanostructures directly below the gate spacer layer is greater than a second number of the first nanostructures directly below the first gate structure. (elements 108 above 118 are portions of nanosheets 108).
As for claim 2,
Mehta teaches the semiconductor structure as claimed in claim 1, and teaches a source/drain (S/D) structure (130) formed adjacent to the first gate structure (140, below 118) ;
and an inner spacer layer (129) between the S/D structure and the first gate structure,
wherein a topmost surface of the inner spacer layer is higher than a top surface of the S/D structure. (120 below 118 is higher than 130)
As for claim 3,
Mehta teaches the semiconductor structure as claimed in claim 2, and teaches an S/D contact structure (156) formed over the S/D structure, wherein the topmost surface of the inner spacer layer is higher than a bottom surface of the S/D contact structure. (Shown in figure 16c).
As for claim 4,
Mehta teaches the semiconductor structure as claimed in claim 1, wherein the first gate structure has a continuous sidewall surface in direct contact with the gate spacer layer, and a bottom surface of the continuous sidewall surface of the first gate structure is lower than a bottom surface of the gate spacer layer.
As for claim 5,
Mehta teaches the semiconductor structure as claimed in claim 4, wherein the continuous sidewall surface of the first gate structure is in direct contact with a topmost first nanostructure of the first nanostructures. (108 shown in figure 12c)
As for claim 6,
Mehta teaches the semiconductor structure as claimed in claim 1, fand teaches
an S/D structure formed adjacent to the nanostructures, wherein a top surface of the S/D structure is lower than a top surface of the topmost first nanostructure of the first nanostructures.(shown in figure 16C).
As for claim 9,
Mehta teaches the semiconductor structure as claimed in claim 1, and teaches in figure 16C that the topmost first nanostructure of the first nanostructures comprises two portions separated from each other by the first gate structure, and the two portions are in direct contact with the gate spacer layer.
As for claim 21,
Mehta teaches in figure 13C a semiconductor structure, comprising:
a stack of nanostructures comprising a topmost nanostructure defining an opening therein (at 108);
a source/drain structure (130) adjacent the stack of nanostructures;
a gate structure (140) on the nanostructures and extending through the opening; a source/drain contact (156) overlying the source/drain structure;
and a gate spacer (129/150) layer separating gate structure from the source/drain contact, the gate spacer layer overlying the topmost nanostructure.
As for claim 22,
Metha teaches the semiconductor structure of claim 21, and teaches a second nanostructure of the stack of nanostructures defines a second opening therein underlying the opening, and the gate structure extends through the second opening. (the stack includes multiple openings above layer 118)
As for claim 23,
Metha teaches the semiconductor structure of claim 21, wherein the gate structure comprises a gate electrode layer; and a gate dielectric layer between the gate electrode layer and the stack of nanostructures, the gate dielectric layer having a sidewall contiguous with a sidewall of the topmost nanostructure. (Not shown, but inherent in a HKMG taught in [0074]. High-k refers to the dielectric, and metal refers to the gate conductor material.)
As for claim 24,
Metha teaches the semiconductor structure of claim 21, and teaches in figure 13C, the uppermost surface of the source/drain structure ( 130) lower than a bottommost surface of the topmost nanostructure (108 above 118).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Mehta in view of Liang et al (U.S. 2017/0170331).
As for claim 7,
Mehta teaches the semiconductor structure as claimed in claim 1, but does not teach a topmost surface of the first gate structure is lower than a top surface of the gate spacer layer.
However, Liang teaches in figure 16C, a recessed gate layer GE3.
It would have been obvious to one skilled in the art at the effective filing date of this application to add a recessed gate taught by Liang to the device of Mehta so allow for a gate cap that protects the gate metal from damage or contamination during later processes. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 8,
Mehta teaches the semiconductor structure as claimed in claim 1, and teaches second nanostructures (shown separated in figure 6C) adjacent to the first nanostructures, wherein each of the first nanostructures has a first width along the second direction, each of the second nanostructures has a second width along the second direction,
But Mehta does not teach that the first width is smaller than the second width.
However, Liang teaches forming nanostructure channels (NS2) having different widths (W1 and W2) in figures 2A and 2B.Liang [0083].
It would have been obvious to one skilled in the art at the effective filing date of this application to vary the width of channels between transistors to allow the Device Vt to be tuned Liang [0008]) One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 10 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Mehta in view of Lee et al. (U.S. 2022/0238678).
As for claim 10,
Mehta teaches in figure 16C semiconductor structure, comprising:
first channel layers (108, left stack) formed over a first region of a substrate along a first direction;
second channel layers (140 center stack) adjacent to the first channel layers and over a second region of the substrate;
a first gate structure (140) formed over the first channel layers along a second direction, wherein a topmost first channel layer of the first channel layers comprises two portions separated from each other by the first gate structure (shown cut in figure 11C); and
a second gate structure (140, center) formed over the second channel layers along the second direction.,
Metha does not teach a first number of the first channel layers directly below the first gate structure is smaller than a second number of the second channel layers directly below the second gate structure.
However, Lee teaches in figures 2J and 2k forming adjacent transistor with a different number of nanostructure channels (208).
It would have been obvious to one skilled in the art at the effective filing date of this application to vary the number of channels between transistors to allow the devices to be tuned Lee [0028]) One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 12,
Mehta in view of Lee makes obvious the semiconductor structure as claimed in claim 10,
And in the combination, Mehta teaches a third channel layers (108, right side of figure 13C) adjacent to the second channel layers and over a third region of the substrate, and in the combination, Lee makes obvious that the second number of the second channel layers is smaller than a third number of the third channel layers as discussed above.
As for claim 13,
Mehta in view of Lee makes obvious the semiconductor structure as claimed in claim 10, and in the combination, Mehta teaches a gate spacer layer (128) adjacent to the first gate structure, wherein the first gate structure has a continuous sidewall surface in direct contact with the gate spacer layer, and a bottom surface of the continuous sidewall surface of the first gate structure is lower than a bottom surface of the gate spacer layer. (Shown in figure 16C).
As for claim 14,
Mehta in view of Lee makes obvious the semiconductor structure as claimed in claim 13, and Matha teaches a first source/drain structure (130) formed adjacent to the first channel layers (140, below 118), wherein a top surface of the first S/D structure is lower than a top surface of the topmost first channel layer (shown in figure 13C).
As for claim 15,
Mehta in view of Lee makes obvious the semiconductor structure as claimed in claim 14, and Mehta teaches a second S/D structure (130, center) formed adjacent to the second channel layers, wherein a top surface of the second S/D structure is higher than the top surface of the first S/D structure. (Shown in 13C).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Mehta in view of Lee and further in view of Liang.
As for claim 11,
Mehta in view of Lee makes obvious the semiconductor structure as claimed in claim 10, wherein each of the first channel layers has a first width along the second direction, each of the second channel layers has a second width along the second direction.
But the combination does not teach that the first width is smaller than the second width.
However, Liang teaches forming nanostructure channels (NS2) having different widths (W1 and W2) in figures 2A and 2B.Liang [0083].
It would have been obvious to one skilled in the art at the effective filing date of this application to vary the width of channels between transistors to allow the Device Vt to be tuned Liang [0008]) One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Mehta in view of Lee and further in view of Ching et al. (DE 102013109635, translation attached).
As for claim 16,
Mehta in view of Lee makes obvious the semiconductor structure as claimed in claim 10, further comprising:
But does not teach that a top surface of the first gate structure is lower than a top surface of the second gate structure.
However, Ching teaches in figure 11, a top surface of the first gate structure (706) is lower than a top surface of the second gate structure (1102).
It would have been obvious to one skilled in the art at the effective filing date of this application to form the gate heights differently because the NMOS and PMOS transistor are formed separately and because the PMOS requires a gate work function metal and with its associated CMP polish which reduces height. Ching [paragraph 21 of the detailed description]. One skilled in the art would have combined these elements with a reasonable expectation of success.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893