DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species 9 in the reply filed on 03/19/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11-13 and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 03/19/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2, 5-10, 14 and 15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Zhang et al. (US20190371888A1).
Regarding claim 1, Fig.19 of Zhang teaches a semiconductor device, comprising:
a substrate 200 (para.0022);
a channel layer 270/280 (para.0078), disposed over the substrate 200;
a gate structure 218/219 (para.0092), disposed over the substrate 200;
source/drain regions 207/208 (para.0050), disposed over the substrate 200 and disposed at two opposite sides of the channel layer 270/280; and
an insulating layer 205/206 (para.0045), disposed between the channel layer 270/280 and the source/drain regions 207/208.
Regarding claim 2, Zhang further teaches the semiconductor device of claim 1, wherein the channel layer 270/280 (para.0078) is disposed between the substrate 200 (para.0022) and the gate structure 218/219 (para.0092), and the gate structure 218/219 is disposed between the source/drain regions 207/208 (para.0050).
Regarding claim 5, Zhang further teaches the semiconductor device of claim 1, wherein the gate structure 218/219 (para.0092) is disposed between the substrate 200 (para.0022) and the channel layer 270/280 (para.0078), and the channel layer 270/280 is disposed between the gate structure 218/219 and the source/drain regions 207/208 (para.0050).
Regarding claim 6, Zhang further teaches the semiconductor device of claim 5, wherein outer surfaces of the source/drain regions 207/208 (para.0050) are in contact with the insulating layer 205/206 (para.0045).
Regarding claim 7, Zhang further teaches the semiconductor device of claim 6, wherein the insulating layer 205/206 (para.0045) and the source/drain regions 207/208 (para.0050) penetrate through the channel layer 270/280 (para.0078).
Regarding claim 8, Zhang further teaches the semiconductor device of claim 1, wherein a material of the channel layer 270/280 (para.0078) includes a low-dimensional material (wherein a low-dimensional material includes nanowires), and a material of the insulating layer 205/206 (para.0045) includes an oxide material (para.0041, wherein the first sidewall spacers 205 may be made of any appropriate material, such as silicon oxide).
Regarding claim 9, Zhang further teaches the semiconductor device of claim 1, further comprising a gate dielectric layer 216 (para.0084) located between the gate structure 218/219 (para.0092) and the channel layer 270/280 (para.0078).
Regarding claim 10, Fig.19 of Zhang teaches a semiconductor device, comprising:
a substrate 200 (para.0022);
a plurality of channels 270/280 (para.0078), vertically stacked over the substrate 200 and separated from each other;
a plurality of source/drain regions 207/208 (para.0050), disposed over the substrate 200 and at two opposite sides of each of the plurality of channels 270/280;
a plurality of insulating layers 205/206 (para.0045), respectively interposed between the plurality of source/drain regions 207/208 and the plurality of channels 270/280; and
a gate structure 218/219 (para.0092), engaging the plurality of channels 270/280 and interposing the plurality of source/drain regions 207/208.
Regarding claim 14, Zhang further teaches the semiconductor device of claim 10, wherein in a cross-section of the semiconductor device, the plurality of channels 270/280 (para.0078) are interposed between the plurality of source/drain regions 207/208 (para.0050) along a horizontal direction.
Regarding claim 15, Zhang further teaches the semiconductor device of claim 14, wherein the plurality of insulating layers 205/206 (para.0045) are disposed between the plurality of source/drain regions 207/208 (para.0050) and the plurality of channels 270/280 (para.0078) along the horizontal direction and are disposed between the plurality of source/drain regions 207/208 and the gate structure 218/219 (para.0092) along the horizontal direction, wherein outer surfaces of the plurality of source/drain regions 207/208 are in contact with the plurality of insulating layers 206, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US20190371888A1) in view of Cheng et al. (US11038044B2).
Regarding claim 3, Zhang further teaches the semiconductor device of claim 2, wherein the insulating layer 205/206 (para.0045) and the source/drain regions 207/208 (para.0050) penetrate through the channel layer 270/280 (para.0078).
Zhang does not teach wherein a bottom surface and a sidewall connecting to the bottom surface of the source/drain regions are in contact with the insulating layer.
Fig.1A of Cheng teaches a gate-all-around (GAA) FET that includes a dielectric layer 60 made of the same material as the dielectric inner spacers 62 and the dielectric layer 60 is disposed between the source/drain epitaxial layer 80 and the bottom fin structure 11 (col.5, lines 19-22) and a liner layer 85, which may be a contact etch stop layer (CESL), is disposed over the source/drain epitaxial layer 80 (col.5, lines 6-8); wherein dielectric layer 60 and liner layer 85 form insulating layers on the bottom surface and on the side of the source/drain epitaxial layer 80 respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the dielectric layer 60 and the liner layer 85 of Cheng in the teachings of ZHANG in order to provide insulation and the liner layer acts as a contact etch stop layer (CESL).
Regarding claim 4, Zhang further teaches the semiconductor device of claim 3, wherein the source/drain regions 207/208 (para.0050) are protruded out of the channel layer 270/280 (para.0078).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US20190371888A1) in view of Gaul et al. (US12249643B2).
Regarding claim 16, Zhang does not teach wherein a material of the plurality of channels includes a transition metal dichalcogenide (TMD) denoted as MX2, where M is a molybdenum (Mo) or tungsten (W) and X is sulfur (S), selenium (Se) or tellurium (Te), and a material of the plurality of insulating layers includes an oxide of Mo
or W.
Fig.16 of Gaul teaches wherein a first two-dimensional (2D) channel layer 180 can be made of a two-dimensional material, including transition metal di chalcogenides (TMDC), for example, molybdenum disulfide (MoS.sub.2), molybdenum diselenide (MoSe.sub.2), tungsten disulfide (WS.sub.2), tungsten diselenide (WSe.sub.2) (col.6, lines 57-63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Gaul’s channel layer, made of a two-dimensional material, including transition metal di chalcogenides (TMDC), for example, molybdenum disulfide (MoS.sub.2), molybdenum diselenide (MoSe.sub.2), tungsten disulfide (WS.sub.2), tungsten diselenide (WSe.sub.2), in the teachings of Zhang because two-dimensional materials can carry similar effective on-state current as Si channels, with significantly thinner channels thus allowing more channels to be built in a stack, thus giving higher overall current density [Gaul, (col.3, lines 58-62)].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891