Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 10/29/25. Claims 6-15 are pending in this application.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 9-15 are rejected under 35 U.S.C. §103 as being unpatentable over Tsai (US 20220336629 A1) and further in view of Kim (KR 100972899 B1).
Regarding claim 6, Tsai discloses a fabricating method of a memory device (figs 1-3), comprising:
forming a plurality of isolation trenches in a substrate, wherein the substrate comprises a silicon layer and a first nitride layer (see 316, see para [0036]);
forming a first oxide layer carpet-covering the first nitride layer and the plurality of isolation trenches (see fig 4, 416);
forming a second nitride layer carpet-covering the first oxide layer (see 716);
removing portions of the second nitride layer so that at least a portion of the first oxide layer is exposed (see para [0041] disclosing 716 can be partially removed, thereby exposing 616) and remaining portions of the second nitride layer form a plurality of spacers on the substrate (see fig 9); and
forming a second oxide layer to cover the plurality of spacers 1104 to an extent that the surface of the second oxide layer is higher than the surface of the substrate (see fig 11).
However, Tsai does not explicitly disclose their top surfaces of the spacers are lower than a surface of the substrate. Kim is directed towards STI features and at least at fig 2m discloses spacers are lower than a surface of the substrate, see fig 2m of Kim.
Tsai and Kim are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Tsai and Kim. Tsai and Kim may be combined by forming the trench of Kim within the substrate as disclosed in Kim. One having ordinary skill in the art would be motivated to combine Tsai with Kim in order to improve device structure stability, see Kim.1
Regarding claim 9, Tsai and Kim disclose the fabricating method of a memory device of claim 6, wherein the forming the plurality of isolation trenches comprises: forming the first nitride layer overlying the silicon layer (see fig 7, 716 formed over 616,); forming a photoresist layer overlying the first nitride layer (see para [0041] disclosing photoresist); performing a lithography process to remove portions of the photoresist layer ( see para [0041] disclosing etching); etching through the first nitride layer and a portion of the silicon layer utilizing remaining portions of the photoresist layer as an etching mask to form the plurality of isolation trenches (see figs 7-9 disclosing etching masking the spacers); and removing the remaining portions of the photoresist layer (see para [0041] disclosing photoresist is removed).
Regarding claim 10, Tsai and Kim discloses the fabricating method of a memory device of claim 9, wherein the etching through the first nitride layer and the portion of the silicon layer is performed by reactive ion etching (see para [0041] disclosing ion etching).
Regarding claim 11, Tsai and Kim disclose the fabricating method of a memory device of claim 6, wherein the plurality of isolation trenches are formed such that the plurality of isolation trenches form a first patterned zone and a second patterned zone upon completion of etching, the first patterned zone comprises a plurality of first trenches having first trench widths (see fig 7), the second patterned zone comprises a plurality of second trenches having second trench widths, and the first trench widths are larger than the second trench widths (see fig 8, element 718 second trench).
Regarding claim 12, Tsai and Kim disclose the fabricating method of a memory device of claim 6, wherein the forming the second oxide layer comprises: depositing the second oxide layer by spin on dielectric deposition process (see para [0048] disclosing spin-on); and densifying the second oxide layer (see para [0038] disclosing doping as densification).
Regarding claim 13, Tsai and Kim disclose the fabricating method of a memory device of claim 6, wherein the first nitride layer and the second nitride layer comprise silicon nitride, and the first oxide layer and the second oxide layer comprise silicon oxide (see para [0044] disclosing silicon nitride and oxide layers).
Regarding claim 14, Tsai and Kim disclose he fabricating method of a memory device of claim 13, wherein the removing the portions of the second nitride layer is performed by an etching process that has a high selectivity between silicon nitride and silicon oxide so that the first oxide layer remains substantially identical when the portions of the second nitride layer are etched away (see fig 8, where 616 remains).
Regarding claim 15, Tsai and Kim disclose the fabricating method of a memory device of claim 6, wherein the forming the second nitride layer is performed by chemical vapor deposition (see para [0042] disclosing cvd).
Allowable Subject Matter
The cited art do not disclose the subject matter of claim 7. Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 depends from claim 7 and is also objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
1 Kim 3A, a second liner oxide layer 231 is formed on the second liner nitride layer 230. Here, the second liner oxide film 231 is formed to prevent damage to the second liner nitride film 230 and at the same time to prevent lifting of the second insulating film to be formed in a subsequent process. This is to improve the embedding characteristics according to the physical properties of the second insulating film, which is effective when the second insulating film is formed of an SOD film.