DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-8, and 10-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention I, and sub-inventions IIA-IIE, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 10/14/2025.
Applicant's election with traverse of invention II, and sub-invention IIF in the reply filed on 10/14/2025 is acknowledged. The traversal is on the ground(s) that sub-inventions are all related to semiconductor structures, and that therefore no undue burden is present. This is not found persuasive because the bar for inventions is not whether or not they are all included in an entire subclass such as semiconductors, or optics. As those areas (semiconductors/optics) contain millions of patents each. What the examiner did provide was a detailed analysis of how each sub-invention required varying classifications, contained different subject matter which results in varying fields of search and search terms. Since the actual thrust of the restriction as provided by the examiner has not be challenged, the requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lei (U.S. PGPub No. 2017/0192050 A1).
As to claim 9, Lei discloses and shows in . A semiconductor structure, comprising:
a first conductive line (317, labeled in figure 3A below) and a second conductive line (other line 317, labeled in figure 3A below), extending in a first direction and spaced apart from each other in a second direction (explicitly shown in figure 3A) ([0011]; [0037], ll. 1-8; where the active channel region Rx (317) is implicitly conductive to charge or the structure would not function as known in the art);
first transistors (lines 319, labeled in figure 3A below, where the examiner is interpret a gate structure as disclosed as a form of transistor), connected to the first conductive line, wherein each of the first transistors includes a first contact (i.e. the contact point between the gate 319 as labeled and the active region Rx 317) ([0001], ll. 1-3; [0037], ll. 1-8);
second transistors (other lines 319, labeled in figure 3A below, where the examiner is interpret a gate structure as disclosed as a form of transistor), connected to the second conductive line, wherein each of the second transistors includes a second contact (i.e. the contact point between the gate 319 as labeled and the active region Rx 317) ([0001], ll. 1-3; [0037], ll. 1-8); and
a first conductive line contact, connected to the first conductive line (i.e. the overlap contact area of 317 and gates 319, the examiner notes that structures SC and Vdd could also be considered line contacts as the also explicitly contact line 317) ([0037], ll. 1-8).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (U.S. PGPub No. 2024/0006254 A1).
As to claim 9, Wen discloses and shows in figures 1, 2A and 3B, a semiconductor structure, comprising:
a first conductive line (306B) and a second conductive line (308B), extending in a first direction (e.g. horizonal direction relative to the page) and spaced apart from each other in a second direction (e.g. spaced apart in the vertical direction as explicitly shown) ([0044], ll. 6-9, clearly in being signal and ground lines they are conductive);
first transistors (320b1 and 320b2), connected to the first conductive line (explicitly shown via connection lines 307 and 309), wherein each of the first transistors includes a first contact (intersection point of either lines noted to the corresponding ground and signal terminals) ([0044], ll. 6-13, claim 3 of Wen discloses the devices 320 as transistor structures);
second transistor (320b3), connected to the second conductive line (explicitly shown via connection lines 307 and 309), wherein each of the second transistors includes a second contact (intersection point of either lines noted to the corresponding ground and signal terminals) ([0044], ll. 6-13; claim 3 of Wen discloses the devices 320 as transistor structures); and
a first conductive line contact (any of the points where connections intersect the ground and signal lines, further traces 310b could be interpreted as the first conductive line contacts), connected to the first conductive line ([0044], ll. 1-6).
Wen does not explicitly disclose the use of four total transistors, in other words a set of first transistors and a set of second transistors.
However, Wen does disclose in ([0042]) the use of multiple device or multiple VC structures may appear in a block. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use a further device/transistor 320b, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Wen with the use of four total transistors, in other words a set of first transistors and a set of second transistors in order to provide the advantage of increased accuracy as adding one more transistor device 320b just provides for a higher resolution defect analysis of the sample under test, as one would need to resolve more features in said sample.
Claim(s) 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (U.S. PGPub No. 2024/0006254 A1) in view of Satya et al. (U.S. Patent No. 6,636,064 B1).
As to claim 17, Wen does disclose the use of a electron beam microscopy system to measure the sample under test but not the particular structures as claimed, further Wen discloses a determination operation, determining a bright state and a dark state in the image to determine whether there is a defect between the first conductive line and the second conductive line of the semiconductor structure ([0016]; [0017]).
Wen does not explicitly disclose an inspection system for inspecting the semiconductor structure, the inspection system comprises: an electron beam emitting system having an electron source and a detector; a stage, configured to carry the semiconductor structure; and a processing device, configured to perform following operations: a pre-charge operation, emitting an electron beam toward the first conductive line contact of the semiconductor structure through the electron source; an imaging operation, scanning the semiconductor structure and receiving secondary electrons that come from the semiconductor structure through the detector to generate an image of the semiconductor structure
However, Satya does disclose and show in figure 25 and in (col. 1, ll. 21-23; col. 27, l. 59 thru col. 28, l. 14; col. 35, ll. 29-38 and l. 66 thru col. 36, l. 9) the use of an electron beam emitting source (952) with a detector (970). Further Satya discloses where the sample/semiconductor is placed on a stage (959). Additionally Satya discloses the basic use of a processing device (FIB/SEM computer/E-BEAM control unit) with the system. Satya further discloses using said source to send electrons towards semiconductor dies which have conduction lines, and imaging the result scattered electrons. The examiner further notes for compact prosecution that Satya also discloses defect detection as a function of contrast in bright/dark regions of an image of the sample under test.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Wen with an inspection system for inspecting the semiconductor structure, the inspection system comprises: an electron beam emitting system having an electron source and a detector; a stage, configured to carry the semiconductor structure; and a processing device, configured to perform following operations: a pre-charge operation, emitting an electron beam toward the first conductive line contact of the semiconductor structure through the electron source; an imaging operation, scanning the semiconductor structure and receiving secondary electrons that come from the semiconductor structure through the detector to generate an image of the semiconductor structure in order to provide the advantage of expected results of using a known technique with known structure to predictably measure the sample under test for defects in an accurate manner (col. 1, l. 60 thru col. 2, l. 2).
As to claim 18, Wen as modified by Satya disclose an inspection system, wherein in response to the second contact of any one of the second transistors being in the bright state in the image, the determination operation determines that there is a defect (i.e. short defect as disclosed) between the first conductive line and the second conductive line ([0017]; [0048], ll. 7-11).
As to claim 19, Wen as modified by Satya discloses and shows in figure 3B, an inspection system, wherein the second conductive line comprises sub-conductive lines at least including a first sub-conductive line (vertical part of black line 308b relative to the page) and a second sub-conductive line (vertical part of line 308b), and in response to the second contact of the second transistors connected to the first sub-conductive line being in the bright state in the image, the determination operation determines that there is a defect between the first sub-conductive line and the first conductive line (as disclosed all connections are measured, as such this noted determination is disclosed) ([0017]; [0048], ll. 7-11)..
As to claim 20, Wen as modified by Satya disclose an inspection system, wherein in response to the second contact of each of the second transistors being in the dark state in the image, the determination operation determines that there is no defect (i.e. as explicitly disclosed that an open defect is not connected to a ground) between the first conductive line and the second conductive line ([0017]; [0048], ll. 7-11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P LAPAGE whose telephone number is (571)270-3833. The examiner can normally be reached Monday-Friday 8-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tarifur Chowdhury can be reached at 571-272-2287. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael P LaPage/Primary Examiner, Art Unit 2877
Prosecution Insights