DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (U.S. PGPub No. 2024/0006254 A1).
As to claim 9, Wen discloses and shows in figures 1, 2A and 3B, a semiconductor structure, comprising:
a first conductive line (306B) and a second conductive line (308B), comprising a conductive material and extending in a first direction (e.g. horizonal direction relative to the page) and spaced apart from each other in a second direction (e.g. spaced apart in the vertical direction as explicitly shown) ([0020]; [0044], ll. 6-9, clearly in being signal and ground lines they are conductive, also as explicitly disclosed they electrically couple the devices which requires a conductive material);
first transistors (320b1 and 320b2), connected to the first conductive line (explicitly shown via connection lines 307 and 309), wherein each of the first transistors includes a first contact (intersection point of either lines noted to the corresponding ground and signal terminals) ([0044], ll. 6-13, claim 3 of Wen discloses the devices 320 as transistor structures);
second transistor (320b3), connected to the second conductive line (explicitly shown via connection lines 307 and 309), wherein each of the second transistors includes a second contact (intersection point of either lines noted to the corresponding ground and signal terminals) ([0044], ll. 6-13; claim 3 of Wen discloses the devices 320 as transistor structures); and
a first conductive line contact (any of the points where connections intersect the ground and signal lines, further traces 310b could be interpreted as the first conductive line contacts), connected to the first conductive line ([0044], ll. 1-6).
Wen does not explicitly disclose the use of four total transistors, in other words a set of first transistors and a set of second transistors.
However, Wen does disclose in ([0042]) the use of multiple device or multiple VC structures may appear in a block. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use a further device/transistor 320b, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Wen with the use of four total transistors, in other words a set of first transistors and a set of second transistors in order to provide the advantage of increased accuracy as adding one more transistor device 320b just provides for a higher resolution defect analysis of the sample under test, as one would need to resolve more features in said sample.
Wen does not explicitly disclose where a first source/drain contact is disposed on a first source/drain region or likewise for a second source/drain contact/region.
However, Wen does disclose in ([0056]; [0062]) that “As is well known in the art, source and drain regions are formed within a substrate adjacent to the gate stack of each MOS transistor”. It is therefore obvious that source/drain contacts could be implemented next to the gate stack transistors (i.e. in source/drain regions) as they are well-known in the art to be used as explicitly stated by Wen.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Wen with a first source/drain contact is disposed on a first source/drain region or likewise for a second source/drain contact/region in order to provide the advantage of expected results as noted in Wen they are well known to be used in the art to achieve a predictable flow of current between two regions in an expected manner.
Claim(s) 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (U.S. PGPub No. 2024/0006254 A1) in view of Satya et al. (U.S. Patent No. 6,636,064 B1).
As to claim 17, Wen does disclose the use of an electron beam microscopy system to measure the sample under test but not the particular structures as claimed, further Wen discloses a determination operation, determining a bright state and a dark state in the image to determine whether there is a defect between the first conductive line and the second conductive line of the semiconductor structure ([0016]; [0017]).
Wen does not explicitly disclose an inspection system for inspecting the semiconductor structure, the inspection system comprises: an electron beam emitting system having an electron source and a detector; a stage, configured to carry the semiconductor structure; and a processing device, configured to perform following operations: a pre-charge operation, emitting an electron beam toward the first conductive line contact of the semiconductor structure through the electron source; an imaging operation, scanning the semiconductor structure and receiving secondary electrons that come from the semiconductor structure through the detector to generate an image of the semiconductor structure or where bright state and dark state of each of the first source/drain contact and second source/drain contact are imaged to determine defects.
However, Satya does disclose and show in figure 25 and in (col. 1, ll. 21-23; col. 27, l. 59 thru col. 28, l. 14; col. 35, ll. 29-38 and l. 66 thru col. 36, l. 9) the use of an electron beam emitting source (952) with a detector (970). Further Satya discloses where the sample/semiconductor is placed on a stage (959). Additionally Satya discloses the basic use of a processing device (FIB/SEM computer/E-BEAM control unit) with the system. Satya further discloses using said source to send electrons towards semiconductor dies which have conduction lines, and imaging the result scattered electrons. The examiner further notes for compact prosecution that Satya also discloses defect detection as a function of contrast in bright/dark regions of an image of the sample under test. Specifically that shorts are detected as a bright to dark or dark to bright in a scan area. Obviously if Wen has these areas to scan and if a short (i.e. defect) is present it would be detected with the teaching of Satya.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Wen with an inspection system for inspecting the semiconductor structure, the inspection system comprises: an electron beam emitting system having an electron source and a detector; a stage, configured to carry the semiconductor structure; and a processing device, configured to perform following operations: a pre-charge operation, emitting an electron beam toward the first conductive line contact of the semiconductor structure through the electron source; an imaging operation, scanning the semiconductor structure and receiving secondary electrons that come from the semiconductor structure through the detector to generate an image of the semiconductor structure or where bright state and dark state of each of the first source/drain contact and second source/drain contact are imaged to determine defects in order to provide the advantage of expected results of using a known technique with known structure to predictably measure the sample under test for defects in an accurate manner resulting in a more detailed analysis of the integrated circuit under test that can include source/drain contact points (col. 1, l. 60 thru col. 2, l. 2).
As to claim 18, Wen as modified by Satya disclose an inspection system, wherein in response to the second source/drain contact (as modified already above) of any one of the second transistors being in the bright state in the image, the determination operation determines that there is a defect (i.e. short defect as disclosed) between the first conductive line and the second conductive line ([0017]; [0048], ll. 7-11).
As to claim 19, Wen as modified by Satya discloses and shows in figure 3B, an inspection system, wherein the second conductive line comprises sub-conductive lines at least including a first sub-conductive line (vertical part of black line 308b relative to the page) and a second sub-conductive line (vertical part of line 308b), and in response to the second source/drain contact (as modified already above) of the second transistors connected to the first sub-conductive line being in the bright state in the image, the determination operation determines that there is a defect between the first sub-conductive line and the first conductive line (as disclosed all connections are measured, as such this noted determination is disclosed) ([0017]; [0048], ll. 7-11)..
As to claim 20, Wen as modified by Satya disclose an inspection system, wherein in response to the second source/drain contact (as modified already above) of each of the second transistors being in the dark state in the image, the determination operation determines that there is no defect (i.e. as explicitly disclosed that an open defect is not connected to a ground) between the first conductive line and the second conductive line ([0017]; [0048], ll. 7-11).
Response to Arguments
Applicant's arguments filed 04/30/2026 have been fully considered but they are not persuasive.
As to applicant’s argument that Wen does not explicitly disclose “a real structure” the examiner respectfully disagrees. Firstly applicant fails to in any manner geometrically define “contact”. One definition of contact is “The state or condition of touching or of immediate proximity.” The broadest reasonable interpretation of the claim language encompasses this definition. As such the argument is not found persuasive until applicants argument is represented in the claim. In other words until which point the “contact” is defined in some geometric way to exclude the interpretation provided by the examiner. As such the rejection is maintained at this time relative to the concept of “contact”.
As to the argument that Wen fails to disclose the newly amended limitation of claim 17, the examiner considers this argument moot as Satya was relied upon to disclose the noted limitation. As to Satya not disclosing the noted limitation, the examiner respectfully disagrees. The fact that Satya never explicitly discloses the measurement of “transistor” is not considered persuasive. The title of Satya is “Dual Probe Test Structures For Semiconductor Integrated Circuits”. Clearly one structure extremely common and well-known that integrated circuits comprise is transistors. The examiner is just interpreting Satya as a more broad analysis technique that can include all structures of integrated circuits such as transistors, resistors or capacitors as known in the art. As such the rejection is maintained at this time. The examiner has provided further analysis above to address the newly amended limitation add to claims 17-20.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P LAPAGE whose telephone number is (571)270-3833. The examiner can normally be reached Monday-Friday 8-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tarifur Chowdhury can be reached at 571-272-2287. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael P LaPage/Primary Examiner, Art Unit 2877
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