DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The Applicant’s arguments with respect to claim 1 in the reply filed on 04/08/2026 have been carefully considered, and are persuasive.
Applicant's arguments with respect to claims 10 and 17 filed 04/08/2026 have been fully considered but they are not persuasive.
As to claim 10, prior art Chou teaches the partial removal of the Ruthenium layer.
As to claim 17, the teaching of prior art Yamazaki has been utilized in place of prior art Nabatame. The combination of prior arts Chou, Zhang, and Yamazaki teach the amended language.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 2023/0008409 A1), hereafter “Chou”, in view of Zhang et al. (US 2021/0126018 A1), hereafter “Zhang”, and further in view of Nabatame (US 2010/0187644 A1), hereafter “Nabatame”.
As to claim 10, Chou teaches a method for fabricating a semiconductor device, comprising:
exposing one or more surfaces of a first conduction channel of a first transistor (Fig. 6B, 126 of 100N, ⁋ [0041]);
exposing one or more surfaces of a second conduction channel of a second transistor (Fig. 6B, 126 of 100P, ⁋ [0041]);
overlaying the one or more surfaces of the first conduction channel with a first high-k dielectric layer and the one or more surfaces of the second conduction channel with a second high-k dielectric layer, respectively (Fig. 8B, 182, ⁋⁋ [0045], [0070], “In some embodiments, each gate dielectric layer includes a first high-k dielectric layer”);
overlaying the first high-k dielectric layer with a third high-k dielectric layer and the second high-k dielectric layer with a fourth high-k dielectric layer, respectively (Fig. 8B, 182, ⁋⁋ [0045], [0070], “In some embodiments each gate dielectric layer includes…and a second high-k dielectric layer”);
depositing a ruthenium-containing layer over each of the third high-k dielectric layer and the fourth high-k dielectric layer (Fig. 12B, 192, ⁋ [0053], “ruthenium”); and
removing the ruthenium-containing layer (Fig. 10B, ⁋ [0055], “one or more etching processes are performed to etch back the replacement gate structures 190”).
Chou fails to teach forming a first combination of threshold voltage modulation layers over the first high-k dielectric layer;
forming a second combination of threshold voltage modulation layers over the second high-k dielectric layer;
performing a first annealing process on at least the first combination of threshold voltage modulation layers and the second combination of threshold voltage modulation layers;
removing the first combination of threshold voltage modulation layers and the second combination of threshold voltage modulation layers; and
performing a second annealing process with a temperature not greater than a threshold so as to remove oxygen vacancies from at least the first high-k dielectric layer and from the second high-k dielectric layer.
Zhang teaches a similar method of fabricating a semiconductor device wherein a threshold voltage modulation layer (Fig. 7, 170a/170b, ⁋ [0051]) is created over a high-k dielectric layer (Fig. 7, 132a/132b, ⁋ [0042]), followed by an annealing process on the threshold voltage modulation layer (⁋ [0056], “An anneal process can then be performed”), and removing the threshold voltage modulation layer (Fig. 10, ⁋ [0057], “layers 170a-190a are removed from the GAA FET device”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the threshold voltage modulation layer and annealing method of Zhang into the method of Chou in view of Nabatame to provide further benefits regarding negative-bias temperature instability (NBTI) and inversion-layer thickness (T.sub.inv) of the gate stack (⁋ [0024]).
Chou in view of Zhang fails to teach performing a second annealing process with a temperature not greater than a threshold so as to remove oxygen vacancies from at least the first high-k dielectric layer and from the second high-k dielectric layer.
Nabatame teaches a manufacturing method for a Metal Insulator Semiconductor transistor (⁋ [0002]) which contains a high-k dielectric layer (HK1, ⁋ [0035]), a second high-k dielectric layer (HK2, ⁋ [0046], “hafnium-based oxide” is a high-k dielectric) and a ruthenium layer (CL, ⁋ [0056]; CL also functions as a work function of the gate electrode as in Chao), wherein an annealing process takes place (⁋ [0051]) not greater than a threshold (1150 °C) to remove oxygen vacancies from at least the first high-k dielectric layer (Figs. 5+6, ⁋ [0051], “the oxygen deficient portions DP which have occurred due to the densification…are reduced”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the heat treatment as taught by Nabatame into the method of Chou in order to create a film with a high oxygen density can be formed, so that it is possible to suppress the flow of the gate-leakage current (⁋ [0053]).
As to claim 11, Chou in view of Zhang and Nabatame teaches the method of claim 10, Chou further teaches wherein each of the first conduction channel and second conduction channel includes a plurality of nanostructures vertically spaced from one another (Fig. 6B, ⁋ [0040], “semiconductor nanosheets”).
As to claim 12, Chou in view of Nabatame and Zhang teach the method of claim 10, Zhang further teaches wherein the threshold voltage modulation layers are selected from a group consisting of: lanthanum(III) oxide (La203), lutetium oxide (LuO), scandium oxide (ScO), yttrium oxide (Y203), Thulium(III) oxide (Tm203), gadolinium(III) oxide (Gd203), zinc oxide (ZnO), germanium oxide (GeO), aluminum(II) oxide (AlO), titanium(II) oxide (TiO), vanadium(II) oxide (VO), and combinations thereof (⁋⁋ [0054], [0048], “La2O3).
As to claim 13, Chou in view of Zhang and Nabatame teach the method of claim 10, Zhang further teaches wherein the first combination of threshold voltage modulation layers are configured to provide the first transistor with a first threshold voltage, and the second combination of threshold voltage modulation layers are configured to provide the second transistor with a second threshold voltage (⁋ [0036], “In one embodiment, the GAA FET device 102a is a device with dipole engineering to modulate Vt, and the GAA FET device 102b is a device without dipole engineering, which will have a different Vt from the first GAA FET device”).
As to claim 16, Chou in view of Zhang and Nabatame teach the method of claim 10, Chou further teaches wherein the ruthenium-containing layer essentially consists of ruthenium or ruthenium oxide (⁋ [0053], “ruthenium”).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Zhang and Nabatame, as applied to claim 10, and further in view of Yamazaki.
As to claim 14, Chou in view of Zhang and Nabatame teach the method of claim 10, but fail to teach wherein the threshold is about 550°C.
Yamazaki teaches a manufacturing method of a transistor (⁋ [0002]) with a heat treatment preferably higher than or equal to 350° C. and lower than or equal to 450° C to reduce oxygen vacancies (⁋ [0414]) in an insulator.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the temperature of Yamazaki into the method of Chou in view of Nabatame because the heat treatment can increase the crystallinity of the insulator and can remove impurities (⁋ [0414]).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Zhang and Yamazaki.
As to claim 17, Chou teaches a method for fabricating a semiconductor device, comprising:
exposing one or more surfaces of a first conduction channel of a first transistor (Fig. 6B, 126 of 100N, ⁋ [0041]) configured with a first threshold voltage (the GAA FET device 102a is a device with dipole engineering to modulate Vt);
exposing one or more surfaces of a second conduction channel of a second transistor (Fig. 6B, 126 of 100P, ⁋ [0041]) configured with a second threshold voltage (⁋ [0036], the GAA FET device 102b is a device without dipole engineering), the second threshold voltage different from the first threshold voltage (⁋ [0036], “In one embodiment, the GAA FET device 102a is a device with dipole engineering to modulate Vt, and the GAA FET device 102b is a device without dipole engineering, which will have a different Vt from the first GAA FET device.”);
wrapping the one or more surfaces of the first conduction channel with a first high-k dielectric layer and the one or more surfaces of the second conduction channel with a second high-k dielectric layer, respectively (Fig. 8B, 182, ⁋⁋ [0045], [0070], “In some embodiments, each gate dielectric layer includes a first high-k dielectric layer”);
wrapping the first high-k dielectric layer with a third high-k dielectric layer and the second high-k dielectric layer with a fourth high-k dielectric layer, respectively (Fig. 8B, 182, ⁋⁋ [0045], [0070], “In some embodiments each gate dielectric layer includes…and a second high-k dielectric layer”);
wrapping each of the third high-k dielectric layer and the fourth high-k dielectric layer with a ruthenium-containing layer (Fig. 12B, 192, ⁋ [0053], “ruthenium”).
Chou fails to teach wrapping the first high-k dielectric layer with a first combination of threshold voltage modulation layers;
forming the second high-k dielectric layer with a second combination of threshold voltage modulation layers;
performing a first annealing process on at least the first combination of threshold voltage modulation layers and the second combination of threshold voltage modulation layers;
removing the first combination of threshold voltage modulation layers and the second combination of threshold voltage modulation layers; and
performing a second annealing process to remove oxygen vacancies from at least the first high-k dielectric layer and from the second high-k dielectric layer;
wherein the first annealing process has a higher maximum temperature than the second annealing process.
Zhang teaches a similar method of fabricating a semiconductor device wherein a threshold voltage modulation layer (Fig. 7, 170a/170b, ⁋ [0051]) is created over a high-k dielectric layer (Fig. 7, 132a/132b, ⁋ [0042]), followed by an annealing process on the threshold voltage modulation layer (⁋ [0056], “An anneal process can then be performed”), and removing the threshold voltage modulation layer (Fig. 10, ⁋ [0057], “layers 170a-190a are removed from the GAA FET device”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the threshold voltage modulation layer and annealing method of Zhang into the method of Chou in view of Nabatame to provide further benefits regarding negative-bias temperature instability (NBTI) and inversion-layer thickness (T.sub.inv) of the gate stack (⁋ [0024]).
Chou in view of Zhang fails to teach performing a second annealing process to remove oxygen vacancies from at least the first high-k dielectric layer and from the second high-k dielectric layer; wherein the first annealing process has a higher maximum temperature than the second annealing process.
Yamazaki teaches a manufacturing method of a transistor (⁋ [0002]) with a heat treatment preferably higher than or equal to 350° C. and lower than or equal to 450° C to reduce oxygen vacancies (⁋ [0414]) in an insulator.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the temperature of Yamazaki into the method of Chou in view of Zhang because the heat treatment can increase the crystallinity of the insulator and can remove impurities (⁋ [0414]).
Chou modified by Zhang and Yamazaki teach wherein the first annealing process has a higher maximum temperature (Zhang; ⁋ [0056] “970 degrees Celsius”) than the second annealing process (Yamazaki; ⁋ [0002] “lower than or equal to 450° C”).
As to claim 18, Chou in view of Zhang and Yamazaki teach the method of claim 17, but fail to teach wherein a temperature of the second annealing process is equal to or less than about 550°C.
Yamazaki teaches a manufacturing method of a transistor (⁋ [0002]) with a heat treatment preferably higher than or equal to 350° C. and lower than or equal to 450° C to reduce oxygen vacancies (⁋ [0414]) in an insulator.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the temperature of Yamazaki into the method of Chou in view of Nabatame because the heat treatment can increase the crystallinity of the insulator and can remove impurities (⁋ [0414]).
As to claim 19, Chou in view of Zhang and Yamazaki teach the method of claim 17, Chou further teaches wherein the ruthenium-containing layer essentially consists of ruthenium or ruthenium oxide (⁋ [0053], “ruthenium”).
As to claim 20, Chou in view of Zhang and Yamazaki teach the method of claim 17, Zhang further teaches wherein the threshold voltage modulation layers are selected from a group consisting of: lanthanum(III) oxide (La203), lutetium oxide (LuO), scandium oxide (ScO), yttrium oxide (Y203), Thulium(III) oxide (Tm203), gadolinium(III) oxide (Gd203), zinc oxide (ZnO), germanium oxide (GeO), aluminum(II) oxide (AlO), titanium(II) oxide (TiO), vanadium(II) oxide (VO), and combinations thereof (⁋⁋ [0054], [0048], “La2O3).
Indication of Allowable Subject Matter
Claims 1-9 are indicated allowable.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 1, Chou and Nabatame are the closest prior arts and teach the method of claim 1 (see for example the office action dated 01/08/2026), however, they fail to teach performing a second annealing process with a temperature not greater than a second threshold so as to remove the ruthenium-containing layer.
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 15, Chou and Nabatame are the closest prior art and fail to teach after the second annealing process, further comprising forming at least one work function metal layer over each of the third high-k dielectric layer and the fourth high-k dielectric layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CARNELL HUNTER III/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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