Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 and 19-20 in the reply filed on 10/6/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/5/2023 and 8/6/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 8-9 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. US 2003/0107081.
Re claim 1, Lee teaches an integrated circuit (fig2), comprising:
at least one transistor (FET with gate 214, fig2, [36]) including:
a semiconductor substrate (200, fig2, [32]) having a front face (top surface of 200, fig2);
a gate structure (212, 214, 215 and 224, fig2, [33]) including a first dielectric layer (212, fig2, [33]), a first conductive layer (214, fig2, [33]), a second dielectric layer (215, fig2, [33]), and a second conductive layer (224, fig2, [33]);
a field plate (232 or 234, fig2, [28]) physically separated from the gate structure (212, 214, 215 and 224, fig2, [33]) and disposed on the front face of the semiconductor substrate, the field plate including a third dielectric layer (215 or 218, fig2, [28]) and a third conductive layer (232 or 234, fig2, [28]); and
a doped conduction region (204, 210, fig2, [32]) in the semiconductor substrate located transverse with an edge of the gate structure that is facing the field plate (210 along left-right form a right angle with edge of gate going into the page, fig2) and transverse with an edge of the field plate that is facing the edge of the gate structure (210 along left-right form a right angle with edge of 232/234 going into the page, fig2).
Re claim 2, Lee teaches the integrated circuit according to claim 1, wherein said at least one transistor further includes a lightly doped conduction region (205, 204, fig2, [41]) implanted in the semiconductor substrate, extending on either side of the conduction region under the gate structure (212, 214, 215 and 224, fig2, [33]) from the edge of the gate structure and under the field plate from the edge of the field plate.
Re claim 4, Lee teaches the integrated circuit according to claim 1, wherein the gate structure includes a first gate region (212, 214, fig2, [33]) and a second gate region (215 and 224, fig2, [33]), the first gate region including the first conductive layer (214, fig2, [33]) disposed on the first dielectric layer (212, fig2, [33]) and being located on the front face of the substrate, the second gate region (215 and 224, fig2, [33]) including the second conductive layer (224, fig2, [33]) disposed on the second dielectric layer (215, fig2, [33]), the second gate region including an internal portion (part of 215 and 224 over 214, fig2, [33]) on the first gate region and an external portion (part of 215 and 224 on side of 214/212, fig2, [33]) projecting from the first gate region on the front face of the substrate, the conduction region (204, 210, fig4, [32]) being located transverse with an edge of the external portion of the second gate region (215/224 between 212 and 210, fig2).
Re claim 5, Lee teaches the integrated circuit according to claim 4, wherein the lightly doped conduction region (205, 204, fig2, [25]) extends under the external portion of the second gate region (part of 215 and 224 on side of 214/212, fig2, [33]).
Re claim 6, Lee teaches the integrated circuit according to claim 4, wherein the field plate comprises the third conductive layer (234, fig2 and 9, [28]) disposed on the third dielectric layer (215 under 234, fig2 and 9, [28]) and is located on the front face of the substrate, the third conductive layer (234, fig2 and 9, [28]) having the same composition and the same thickness as the second conductive layer (224, fig2 and 9, [33]), the third dielectric layer (215 under 234, fig2 and 9, [28]) having the same composition and the same thickness as the second dielectric layer (215 under 224, fig2 and 9, [28]) of the external portion of the second gate region.
Re claim 8, Lee teaches the integrated circuit according to claim 1, wherein the field plate (232 or 234, fig2, [28]) is electrically connected to the conduction region (204, 210, fig2, [32]).
Re claim 9, Lee teaches the integrated circuit according to claim 1, wherein the edge of the field plate (edge of 232 or 234 facing 214, fig2, [28]) opposite said edge (edge of 214 facing 218, fig2) transverse with the conduction region (204, 210, fig2, [33]) is located above a dielectric volume of a shallow isolation trench (218, fig2, [28]).
Re claim 20, Lee teaches the transistor device according to claim 1, wherein the third dielectric layer (215 under 234, fig2, [28]) has a composition that are the same as a composition of the second dielectric layer (215 under 224, fig2, [33]) and the third conductive layer (234, fig2 and 9, [28]) has a composition that are the same as a composition of the second conductive layer (224, fig2 and 9, [33]).
Re claim 19, Lee teaches a transistor device (fig2), comprising:
a semiconductor substrate having a front face (top surface of 200, fig4, [32]);
a gate structure (212, 214, 215 and 224, fig2, [33]) on the front face of the substrate, the gate structure comprising:
a first dielectric layer (212, fig2, [33]) having a first end (left end of 212, fig2, [33]) and a second end (right end of 212, fig2, [33]);
a first conductive layer (214, fig2, [33]) on the first dielectric layer, the first conductive layer having a first end (left end of 214, fig2, [33]) coplanar with the first end of the first dielectric layer (left end of 212, fig2, [33]) and a second end (right end of 214, fig2, [33]) coplanar with the second end of the first dielectric layer (right end of 212, fig2, [33]);
a second dielectric layer (215 above 214, fig4, [33]) on the first conductive layer (214, fig2, [33]) and extending onto the front face of the semiconductor substrate (top surface of 200, fig4, [32]); and
a second conductive layer (224, fig2, [33]) on the second dielectric layer;
a field plate (234, fig2, [28]) physically separated from the gate structure (212, 214, 215 and 224, fig2, [33]) and on the front face of the substrate,
the field plate comprising:
a third dielectric layer (215 under 234, fig2, [28]) having a first end (left end of 215, fig2, [28]) and a second end (right end of 215, fig2, [28]); and
a third conductive layer (234, fig2, [28]) on the third dielectric layer, the third conductive layer having a first end (left end of 234, fig2, [28]) coplanar with the first end (left end of 215, fig2, [28]) of the third dielectric layer and a second end (right end of 234, fig2, [28]) coplanar with the second end (right end of 215, fig2, [28]) of the third dielectric layer; and
a doped conduction region (204, 210, fig2, [32]) in the semiconductor substrate located between the gate structure (212, 214, 215 and 224, fig2, [33]) and the field plate (234, fig2, [28]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-29 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2003/0107081 in view of Guowei et al. US 2013/0277741.
Re claim 21, Lee teaches a device (fig2), comprising:
a substrate (200, fig4, [32]);
a first (210, fig2, [32]) and a second (206, 205, fig2, [25]) conduction region in a first surface of the substrate (top surface of 200, fig4, [32]);
a gate structure (212, 214, 215 and 224, fig2, [33]) on the first surface of the substrate between the first (204, 210, fig2, [32]) and second (206, 205, fig2, [25]) conduction regions along a first direction (direction from left to right, fig2 and 8),
the gate structure including:
a first gate region (212, 214, fig2, [33]) including a first dielectric layer (212, fig2, [33]) and a first conductive layer (214, fig2, [33]); and
a second gate region (215, 224, fig2, [33]) on the first gate region and surrounding the first gate region along the first direction (direction from left to right, fig2 and 8);
a field plate (232 or 234, fig2, [28]) on a first lightly doped conduction region (204 or 204 under 234/232, fig2, [33]) in the first surface of the substrate; and
Lee does not explicitly show a plurality of contact pillars coupled between the field plate and the first conduction region.
Guowei teaches a field plate (102, fig2A, [24]) on a first lightly doped conduction region (16, fig2A, [23]) in the first surface of the substrate; and a plurality of contact pillars (104C, fig2A, [24]) coupled between the field plate (102, fig2A, [24]) and the first conduction region (20, fig2A, [23]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lee and Guowei to add Field plate 102-104C with 236 or 232 of Lee connected to 104C in region 12 of Guowei and added 104C between gate and drain. The motivation to do so is to improve the breakdown voltage of the device (Guowei, [22]).
Re claim 22, Lee modified above teaches the device according to claim 21, wherein the second gate region (Lee, 215, 224, fig2, [33]) includes a second conductive layer (Lee, 224, fig2, [33]) on a second dielectric layer (Lee, 215, fig2, [33]).
Re claim 23, Lee modified above teaches the device according to claim 22, comprising a plurality of lightly doped conduction regions (Lee, 205, 204, fig2, [25]) in the first surface of the substrate.
Re claim 24, Lee modified above teaches the device according to claim 23, wherein the first gate region (Lee, 212, 214, fig2, [33]) is between a second (Lee, 205, fig2, [25]) and a third (Lee, 204 between gate 214 and 210, fig2, [25]) lightly doped conduction region of the plurality of lightly doped conduction regions along the first direction (Lee, direction from left to right, fig2 and 8).
Re claim 25, Lee modified above teaches the device according to claim 24, wherein the second gate region (Lee, 215, 224, fig2, [33]) includes a first portion (Lee, 215 and 224 over 214, fig2, [33]) on the first gate region (Lee, 212, 214, fig2, [33]) and a plurality of second portions (Lee, 215 and 224 on side of 214, fig2, [33]) on the second (Lee, 205, fig2, [25]) and third (Lee, 204 between gate 214 and 210, fig2, [25]) lightly doped conduction regions, respectively.
Re claim 26, Lee modified above teaches the device according to claim 25, wherein the first dielectric layer (Lee, 212, fig2, [33]) has a first end (Lee, front or back end of 212, fig2 and 8, [33]) and the first conductive layer has a second end (Lee, front or back end of 214, fig2 and 8, [33]) coplanar with the first end along a second direction (Lee, direction going into the page, fig2 and 8) transverse to the first direction (Lee, direction from left to right, fig2 and 8).
Re claim 27, Lee modified above teaches the device according to claim 25, wherein the second dielectric layer has a first end (Lee, front or back end of 215, fig2 and 9-10, [33]) and the second conductive layer has a second end (Lee, front or back end of 224, fig2 and 9-10, [33]) coplanar with the first end along a second direction (Lee, direction going into the page, fig2 and 9-10) transverse to the first direction (Lee, direction from left to right, fig2 and 9-10).
Re claim 28, Lee modified above teaches the device according to claim 21, wherein the field plate includes a second conductive layer (Lee, 234 acting as 104C over 12, fig2) and a second dielectric layer (Lee, 215, fig2, [28]) between the second conductive layer (Lee, 234, fig2, [28]) and the first lightly doped conduction region (Lee, 204 or 204 under 234/232, fig2, [33]).
Re claim 29, Lee modified above teaches the device according to claim 28, wherein the second dielectric layer has a first end (Lee, front or back end of 215, fig2 and 9-10, [28]) and the second conductive layer has a second end (Lee, front or back end of 234, fig2 and 9-10, [28]) coplanar with the first end along a second direction (Lee, direction going into the page, fig2 and 9-10) transverse to the first direction (Lee, direction from left to right, fig2 and 9-10).
Claim(s) 1, 4-5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Adler et al. US 5252848 and Guowei et al. US 2013/0277741.
Re claim 1, Adler teaches an integrated circuit, comprising:
at least one transistor (10, fig1, col1 line 68) including:
a semiconductor substrate (11, fig1, col2 line 1-5) having a front face (top surface of 11 facing 12, fig1);
a gate structure (21, 22, 24, 26, 27, fig1, col2 line 40-68) including a first dielectric layer (21, fig1, col2 line45), a first conductive layer (22, fig1, col2 line46), a second dielectric layer (24, fig1, col2 line68), and a second conductive layer (27, fig1, col2 line66);
Adler does not explicitly show a field plate physically separated from the gate structure and disposed on the front face of the semiconductor substrate, the field plate including a third dielectric layer and a third conductive layer; and a doped conduction region in the semiconductor substrate located transverse with an edge of the gate structure that is facing the field plate and transverse with an edge of the field plate that is facing the edge of the gate structure.
Guowei teaches a field plate (102, 104C, 106, 108 and 12, fig2A, [23, 24, 25]) physically separated from the gate structure (30, fig2A, [24]) and disposed on the front face of the semiconductor substrate (top surface of 10, fig2A, [23]), the field plate including a third dielectric layer (106, 108, 12, fig2A, [25, 34]) and a third conductive layer (104C, 102, fig2A, [24]);
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Adler and Guowei to add Field plate 102-104C-106-108-12 over region around 31 of Adler in fig1. The motivation to do so is to improve the breakdown voltage of the device (Guowei, [22]).
Adler modified above teaches a doped conduction region (Adler, 18 and 19, fig1,col2 line 20) in the semiconductor substrate located transverse with an edge of the gate structure (Adler, 18 and 19 across edge of gate 21-27 going into the page, fig1) that is facing the field plate and transverse with an edge of the field plate that is facing the edge of the gate structure (Adler, 18 and 19 across edge of 104C added between gate and drain).
Re claim 4, Adler modified above teaches the integrated circuit according to claim 1, wherein the gate structure includes a first gate region (Adler, 21 and 22 around 20, fig1, col2 line 40-68) and a second gate region (Adler, 24, 26 and 27, fig1, col2 line 40-68), the first gate region including the first conductive layer (Adler, 22, fig1, col2 line 40-68) disposed on the first dielectric layer (Adler, 21, fig1, col2 line 40-68) and being located on the front face of the substrate, the second gate region (Adler, 24, 26 and 27, fig1, col2 line 40-68) including the second conductive layer (Adler, 27, fig1, col2 line 40-68) disposed on the second dielectric layer (Adler, 24 and 26, fig1, col2 line 40-68), the second gate region including an internal portion (Adler, 24, 26 and 27 over 20, fig1, col2 line 40-68) on the first gate region and an external portion (Adler, 24, 26 and 27 outside of 20, fig1, col2 line 40-68) projecting from the first gate region on the front face of the substrate, the conduction region (Adler, 18 and 19, fig1,col2 line 20) being located transverse with an edge of the external portion of the second gate region (Adler, 24, 26 and 27 between 20 and 31, fig1, col2 line 40-68).
Re claim 5, Adler modified above teaches the integrated circuit according to claim 4, wherein the lightly doped conduction region (Adler, 18, fig1, col2 line 20) extends under the external portion of the second gate region (Adler, 24, 26 and 27 between 20 and 31, fig1, col2 line 40-68).
Re claim 8, Adler modified above teaches the integrated circuit according to claim 1, wherein the field plate (Guowei, 102, 104C, 106, 108 and 12, fig2A, [23, 24, 25]) is electrically connected to the conduction region (Guowei, 16, 20, fig2A, [23]).
Re claim 9, Adler modified above teaches the integrated circuit according to claim 1, wherein the edge of the field plate (Guowei, 102 on right side of 106, fig2A) opposite said edge (Guowei, 102 on left side of 106, fig2A) transverse with the conduction region (Guowei, 16, 20, fig2A, [23]) is located above a dielectric volume of a shallow isolation trench (Guowei, 12, fig2A, [34]).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Adler et al. US 5252848 and Guowei et al. US 2013/0277741 and Zhang et al. US 2015/0333177.
Re claim 2, Adler does not explicitly show the integrated circuit according to claim 1, wherein said at least one transistor further includes a lightly doped conduction region implanted in the semiconductor substrate, extending on either side of the conduction region under the gate structure from the edge of the gate structure and under the field plate from the edge of the field plate.
Adler teaches a lightly doped conduction region (18, fig1, col2 line 19) in the semiconductor substrate drain side (19, fig1, col2 line 20-25).
Zhang teaches a lightly doped conduction region (60, fig1, [27]) in the semiconductor substrate source side (36, fig1, [27]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Adler in view of Guowei and Zhang to add LDD region on side of source 17. The motivation to do so is to reduce hot-carrier effect (Zhang, [27]).
Allowable Subject Matter
Claim 3 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to reduce size of the high voltage transistor and increase the breakdown voltage of the device.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812