Prosecution Insights
Last updated: April 19, 2026
Application No. 18/180,588

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102
Filed
Mar 08, 2023
Examiner
GEBREMARIAM, SAMUEL A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Winbond Electronics Corp.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
685 granted / 825 resolved
+15.0% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
19 currently pending
Career history
844
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
36.5%
-3.5% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 825 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of 7-14 in the reply filed on 9/24/2025 is acknowledged. The traversal is on the ground(s) that there is no serious burden on the examiner to examine all pending claims. This is not found persuasive because as explicitly stated in the restriction requirement mailed 8/04/2025 as the inventios acquired a separate status in the art in view of their different classification. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin US 2015/0294923. Regarding claim 1, Shin discloses (fig. 2 and related text)a semiconductor structure (30), comprising: a substrate (210) that comprises active regions (214) and isolation structures (212), and the isolation structures surround the active regions (fig. 2); buried word lines (WL, fig. 2) disposed in the substrate (210); a dielectric material layer (230B) formed on the substrate (210); a semiconductor material layer (226, [0089]) formed on the dielectric material layer (230B); and contacts (400) adjacent to the semiconductor material layer (fig. 2), wherein the contacts (DC/400) penetrate the semiconductor material layer (between 226B), the dielectric material layer (230B) and parts of the substrate (210), and the contacts are positioned in the respective active regions (214). Regarding claim 2, Shin discloses the substrate includes an array region (CA) and a periphery region (Core/Peri), and the semiconductor material layer (226) extends over the array region (226B) and the periphery region (226A), and wherein the active regions (214) and the contacts (400) are positioned in the array region (CA), and a portion of the semiconductor material layer (226A) that extends over the periphery region (CORE/Peri) is a part of peripheral conductive wires ([0084]). Regarding claim 3, Shin discloses top surfaces of the contacts (DC) are coplanar with top surface of the semiconductor material layer (226B, fig. 2). Regarding claim 4, Shin discloses the contacts (400) and the semiconductor material layer (226) are made of the same material ([0068], DC, 400 and 226 [0089] could be doped polysilicon). Regarding claim 5, Shin discloses a plurality of doping regions [0065], wherein the doping regions are disposed between the semiconductor material layer (226B) and the respective contacts (DC, 400), so that the semiconductor material layer (226B) is separated from the contacts (DC/400, fig. 2). Regarding claim 6, Shin discloses a plurality of bit lines (234B/232B) formed on the contacts (DC) and the semiconductor material layer (226B), wherein top surfaces of the doping regions are in contact with bottom surfaces of the plurality of bit lines (electrical contact, the claim does not require direct contact), and wherein the buried word lines extend in a first direction, the plurality of bit lines extend in a second direction, and the first direction is different from the second direction (fig. 2). Regarding claim 15, Shin discloses the semiconductor material (226) layer includes: a first semiconductor material (226B) portion formed in the array region (CA); and a second semiconductor material portion (226A) formed in the periphery region (CORE/Peri) to form the part of peripheral conductive wires (fig. 2). Regarding claim 16, Shin discloses the semiconductor material layer includes a polysilicon layer ([0089]). Regarding claim 17, Shin discloses the doping regions include amorphous material (the doping of the substrate causes amorphous region, hence the same material). Allowable Subject Matter Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Mar 08, 2023
Application Filed
Nov 14, 2025
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+8.9%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 825 resolved cases by this examiner. Grant probability derived from career allow rate.

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