DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/08/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 11/17/2025 is acknowledged.
Claims 1-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected product, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/17/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-19, 21 and 22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2023/0420359 to Xie et al (hereinafter Xie).
Regarding Claim 17, Xie discloses a method for forming a semiconductor structure, comprising:
forming a first fin structure protruding from a front side of a substrate, wherein the first fin structure comprises first semiconductor material layers (210, Fig. 18B) and second semiconductor material layers (208) alternately stacked;
forming an isolation structure (205) surrounding the first fin structure;
removing a portion of the first fin structure to form a S/D recess;
forming an S/D structure (214 (Fig. 20A) in the S/D recess;
forming a first contact structure (260, Fig. 23C) over a first side of the S/D structure, wherein the first contact structure has an extending portion, and the extending portion has a bottom surface lower than a top surface of the S/D structure (Fig. 23C, the figure being upside down); and
forming a second contact structure (262) over a second side of the S/D structure, wherein the second contact structure is in direct contact with the first contact structure (Fig. 23C).
Regarding Claim 18, Xie discloses the method for forming the semiconductor structure as claimed in Claim 17, further comprising:
removing a portion of the substrate to expose the isolation structure (Fig. 18C);
forming a dielectric layer (216) on the isolation structure;
forming a trench through the dielectric layer and the isolation structure (Fig. 20C); and
forming the second contact structure in the trench (Fig. 21C).
Regarding Claim 19, Xie discloses the method for forming the semiconductor structure as claimed in Claim 18, wherein a bottom surface of the S/D structure is exposed by the trench, and the second contact structure is in direct contact with a bottom surface of the S/D structure after forming the second contact structure in the trench (Fig. 22C).
Regarding Claim 21, Xie discloses the method for forming the semiconductor structure as claimed in claim 17, further comprising:
forming a dummy gate structure over the first fin structure;
removing the first semiconductor material layers to form a plurality of nanostructures; and
replacing the dummy gate structure with a gate structure (210), wherein the nanostructures are wrapped by the gate structure [0102].
Regarding Claim 22, Xie discloses the method for forming the semiconductor structure as claimed in Claim 17, further comprising:
forming a fin spacer (211, Fig. 20A) adjacent to the S/D structure, wherein the bottom surface of the extending portion of the first contact structure is lower than a top surface of the fin spacer (Fig. 20C).
Claim 31 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2022/0102522 to Dewey et al (hereinafter Dewey).
Regarding Claim 31, Dewey discloses a method for forming a semiconductor structure, comprising:
forming a first fin structure and a second fin structure (502, Fig. 5) protruding from a front side of a substrate, wherein the first fin structure and the second fin structure, respectively, comprise first semiconductor material layers and second semiconductor material layers alternately stacked (Fig. 1B);
removing a portion of the first fin structure to form a first S/D recess (Fig. 4C);
removing a portion of the second fin structure to form a second S/D recess (Fig. 4C);
forming a first S/D structure (432, 506, Fig. 5) in the first S/D recess;
forming a second S/D structure (432, 506) in the second S/D recess; and
forming a first contact structure (514) over a frontside of the first S/D structure and a frontside of the second S/D structure, wherein the first contact structure has a T-shaped structure (Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23, 26, 27 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Xie.
Regarding Claims 23, Xie discloses the method for forming the semiconductor structure as claimed in Claim 17 but does not disclose forming a silicide layer on the S/D structure, wherein a bottommost surface of the silicide layer is lower than a top surface of the S/D structure.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the method of Xie to have included the formation of a silicide layer on the S/D structure, including forming it lower than a top surface of the S/D structure. Silicides were known in the art for providing reduced resistance between layers. Since the S/D contact extends along both a top surface and a side surface of the S/D structure, it would have been obvious to form a silicide layer along a top surface and side surface of the S/D structure to reduce the electrical resistance along the full interface of the S/D structure and contact.
Regarding Claim 26, Xie discloses a method for forming a semiconductor structure, comprising:
forming a first fin structure (103, Fig. 1A) protruding from a front side of a substrate, wherein the first fin structure comprises first semiconductor material layers (106) and second semiconductor material layers (108) alternately stacked;
forming a dummy gate structure (not shown, Fig. 2A; [0083]) on the first fin structure;
forming a gate spacer layer adjacent to the dummy gate structure [0084];
forming a fin spacer (120, Fig. 3A) adjacent to the first fin structure;
removing a portion of the first fin structure to form a S/D recess (Fig. 2A);
forming an S/D structure (113/114) in the S/D recess; and
forming a first contact structure (260/262, Fig. 23C) over a first side of the S/D structure, wherein a bottom surface of the first contact structure is lower than a top surface of the fin spacer.
Xie does not follow the process order claimed by Applicant. However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed the nanostructure device using the order claimed by Applicant. Absent any unexpected results, Applicant’s process order results in a similar structure as Xie. The inventive concept appears to focus on the contact structure. As such, various steps and process orders which arrive at a nanostructure GAAFET, prior to forming a contact structure, would have been obvious to utilize.
Regarding Claim 27, Xie makes obvious the method for forming the semiconductor structure as claimed in Claim 26, further comprising:
removing a portion of the substrate from a backside of the substrate (Fig. 22A);
forming a dielectric layer (296, Fig. 23A) below the substrate;
forming a trench through the dielectric layer (not pictured, Fig. 23C; [0107]); and
forming a second contact structure (274) in the trench, wherein the second contact structure interfaces with the first contact structure.
Regarding Claim 29, Xie makes obvious the method for forming the semiconductor structure as claimed in Claim 26 but does not disclose the formation of a silicide layer.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the method of Xie to have included the formation of a silicide layer on the S/D structure, including forming it lower than a top surface of the S/D structure. Silicides were known in the art for providing reduced resistance between layers. Since the S/D contact extends along both a top surface and a side surface of the S/D structure, it would have been obvious to form a silicide layer along a top surface and side surface of the S/D structure to reduce the electrical resistance along the full interface of the S/D structure and contact.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Dewey.
Regarding Claim 35, Dewey discloses the method for forming the semiconductor structure as claimed in Claim 31, further comprising:
forming a dummy gate structure over the first fin structure [0083];
replacing the dummy gate structure with a gate structure, wherein the nanostructures are wrapped by the gate structure [0083].
While Dewey does not explicitly disclose the process for making the nanowires or nanoribbons, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have removed first semiconductor material layers from a stack of alternative first and second semiconductor material layers to form a plurality of nanostructures. Such details are omitted from Dewey as they were common in the art. Additionally, the steps are not relevant to the inventive concept of the contact structure for S/D regions.
Allowable Subject Matter
Claims 20, 24, 25, 28, 32, 33 and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 20 requires a dielectric wall adjacent to the S/D structure, wherein a top surface of the dielectric wall is higher than a top surface of the S/D structure, and a bottom surface of the first contact structure is lower than the top surface of the dielectric wall. While dielectric walls are common in the art, it is not apparent that the wall should be higher than a top surface of the S/D feature having the contact structure as claimed by Applicant.
Claim 24 requires the first contact structure have a T-shaped structure. Xie teaches an L shaped contact and it is not apparent that a T shaped structure would have been beneficial or preferred.
Claim 25 requires a portion of the second contact structure be embedded in the first contact structure. It is not apparent that an embedded second contact structure would have been beneficial to Xie or preferred.
Claim 28 requires a top surface of the second contact structure be higher than a bottom surface of the S/D structure. Xie does not use a method as outlined by Applicant to arrive at a first and second contact structure having the requirements claimed by Applicant.
Claims 32 and 33 requires a second contact structure below a backside of the first S/D structure and a backside of the second S/D structure, wherein the second contact structure has a reversed T shaped structure. Dewey does not disclose a backside contact structure. While backside contact structures are known in the art, it is not apparent that the device of Dewey would benefit from, or function equally as well, with a backside, second S/D structure as detailed by Applicant.
Claim 34 requires a fin spacer adjacent to the first S/D structure, wherein a bottom surface of the first contact structure is lower than a top surface of the fin spacer. Dewey does not utilize a spacer and though they were known in the art before Applicant’s invention for S/D regions, the combination of requirements with a contact structure is not an apparent modification which would have been obvious to utilize in the embodiments taught by Dewey.
Claim 36 requires a dielectric wall adjacent to the first S/D structure, wherein a top surface of the dielectric wall is higher than a top surface of the first S/D structure, and a bottom surface of the first contact structure is lower than the top surface of the dielectric wall.
Conclusion
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893