DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for the benefit of U.S. Provisional Patent Application No. 63/374,782, titled “Semiconductor Devices with Asymmetric Source/Drain Design,” filed September 7, 2022, and U.S. Provisional Patent Application No. 63/340,274, titled “Strategic Asymmetric SD Design for GAA Performance Enhancement,” filed May 10, 2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/9/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restriction
It has been acknowledged that the Applicant has elected without traverse Invention Group I and Species I represented by claims 1-4, 7-13, and 15, cancelling claims 5-6, 14, and 16-20, per the response dated on 10/24/2025. In addition, the Applicant has added claims 21-28 as new claims. Currently, claims 1-4, 7-13, 15, and 21-28 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-13, 15, and 21-28 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Cheng (US 2020/0266060 A1).
Regarding claim 1, Cheng teaches a semiconductor structure (semiconductor integrated circuit device 10, Figs. 1A-C, [0035]), comprising:
a plurality of semiconductor layers (active nanosheet channel layers 112, 114, and 116, Figs. 1A-C, [0036]) on a substrate (semiconductor substrate 100, Figs. 1A-C, [0036]);
a gate structure (high-k dielectric/metal gate (HKMG) structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Figs. 1A-B, [[0037]) wrapped around the plurality of semiconductor layers (active nanosheet channel layers 112, 114, and 116, Figs. 1A-B);
an inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A, [0036]) between the plurality of semiconductor layers (active nanosheet channel layers 112, 114, and 116, Figs. 1A-C) and in contact with a first side (right side in Fig. 1A) of the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A); and
an epitaxial layer (source/drain extension contacts 140 on the left in Fig. 1A, [0041]: “… source/drain extension contacts 140 comprise epitaxial layers that are grown on the end portions of the active nanosheet channel layers 112, 114 and 116”) in contact with a second side (left side in Fig. 1A) of the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A), wherein the second side (left side in Fig. 1A) is opposite to the first side (right side in Fig. 1A) .
Regarding claim 2, Cheng teaches the semiconductor structure of claim 1, wherein the epitaxial layer (source/drain extension contacts 140, Fig. 1C) is in contact with the substrate (semiconductor substrate 100, Fig. 1C).
Regarding claim 3, Cheng teaches the semiconductor structure of claim 1, further comprising a source/drain (SID) structure (source/drain (S/D) layer 150 on the left in Fig. 1A, [0036]) in contact with the epitaxial layer (source/drain extension contacts 140 on the left, Fig. 1A).
Regarding claim 4, Cheng teaches the semiconductor structure of claim 1, further comprising:
an additional epitaxial layer (source/drain extension contacts 140 on the right in Fig. 1A) in contact with the plurality of semiconductor layers (active nanosheet channel layers 112, 114, and 116, Figs. 1A) and the inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A); and
a SID structure (source/drain (S/D) layer 150 on the right in Fig. 1A) in contact with the additional epitaxial layer (source/drain extension contacts 140 on the right in Fig. 1A) and the inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A).
Regarding claim 7, Cheng teaches the semiconductor structure of claim 1, wherein an end portion (right side of active nanosheet channel layers 112, 114, and 116) of the plurality of semiconductor layers (active nanosheet channel layers 112, 114, and 116 in Figs. 1A) is aligned with the first side (right side of HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174 in Fig. 1A) of the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A: the end portion is aligned with an offset in the Y direction in Fig. 1A).
Regarding claim 8, Cheng teaches the semiconductor structure of claim 1, wherein the epitaxial layer (source/drain extension contacts 140 on the left in Fig. 1A) comprises a silicon epitaxial layer doped with a dopant ([0062]: “the source/drain extension contacts 140 can be formed of epitaxial carbon doped silicon (Si:C).”).
Regarding claim 9, Cheng teaches the semiconductor structure of claim 1, wherein the epitaxial layer (source/drain extension contacts 140 on the left in Fig. 1A) has a thickness ranging from about 1 nm to about 10 nm ([0063]: “the source/drain extension contacts 140 are formed with a thickness in a range of about 2 nm to about 4 nm.”).
Regarding claim 10, Cheng teaches a semiconductor device, comprising:
a plurality of channel structures (active nanosheet channel layers 112, 114, and 116, Figs. 1A-C, [0036]) on a substrate (semiconductor substrate 100, Figs. 1A-C, [0036]);
a gate structure (high-k dielectric/metal gate (HKMG) structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Figs. 1A-B, [[0037]) wrapped around the plurality of channel structures (active nanosheet channel layers 112, 114, and 116, Figs. 1A-B);
an inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A, [0036]) in contact with the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A) and adjacent to a first end (right side of active nanosheet channel layers 112, 114, and 116 in Fig. 1A) of the plurality of channel structures (active nanosheet channel layers 112, 114, and 116, Figs. 1A);
a gate spacer (gate sidewall spacer 136 on the right in Fig. 1A, [0036]) on a sidewall (upper right sidewall of HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174 in Fig. 1A) of the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A) and above the plurality of channel structures (active nanosheet channel layers 112, 114, and 116, Figs. 1A); and
an epitaxial layer (source/drain extension contacts 140 on the left in Fig. 1A, [0041]: “… source/drain extension contacts 140 comprise epitaxial layers that are grown on the end portions of the active nanosheet channel layers 112, 114 and 116”) in contact with the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A) and a second end (left side of active nanosheet channel layers 112, 114, and 116 in Fig. 1A) of the plurality of channel structures (active nanosheet channel layers 112, 114, and 116, Figs. 1A) , wherein the second end (left side in Fig. 1A) is opposite to the first end (right side in Fig. 1A).
Regarding claim 11, Cheng teaches the semiconductor device of claim 10, wherein the epitaxial layer (source/drain extension contacts 140 on the left in Fig. 1A) comprises a vertical portion (the vertical walls of source/drain extension contacts 140) in contact with the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A) and the plurality of channel structures (active nanosheet channel layers 112, 114, and 116, Figs. 1A) and a horizontal portion (the potion shown in Fig. 1C) in contact with the substrate (semiconductor substrate 100, Figs. 1C).
Regarding claim 12, Cheng teaches the semiconductor device of claim 10, further comprising a source/drain (SID) structure (source/drain (S/D) layer 150 on the left in Fig. 1A, [0036]) in contact with the epitaxial layer (source/drain extension contacts 140 on the left, Fig. 1A).
Regarding claim 13, Cheng teaches the semiconductor device of claim 10, further comprising:
an additional epitaxial layer (source/drain extension contacts 140 on the right in Fig. 1A) in contact with the first end (right side of active nanosheet channel layers 112, 114, and 116 in Fig. 1A) of the plurality of channel structures (active nanosheet channel layers 112, 114, and 116 in Fig. 1A); and
a SID structure (source/drain (S/D) layer 150 on the left in Fig. 1A) in contact with the additional epitaxial layer (source/drain extension contacts 140 on the right in Fig. 1A) and the inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A).
Regarding claim 15, Cheng teaches the semiconductor device of claim 10, wherein the first end (right side of active nanosheet channel layers 112, 114, and 116 in Fig. 1A) of the plurality of channel structures (active nanosheet channel layers 112, 114, and 116 in Fig. 1A) is under the gate spacer (gate sidewall spacer 136 on the right in Fig. 1A: the right side surface of the gate sidewall spacer 136 is aligned with the right side surface of the active nanosheet channel layers 112, 114, and 116. Therefore, the first end of the plurality of channel structures is under the gate spacer.).
Regarding claim 21, Cheng teaches the semiconductor structure of claim 4, wherein the epitaxial layer (source/drain extension contacts 140 on the left in Fig. 1A) and the additional epitaxial layer (source/drain extension contacts 140 on the right in Fig. 1A) comprise a same semiconductor material ([0062]: “the source/drain extension contacts 140 can be formed of epitaxial carbon doped silicon (Si:C).”).
Regarding claim 22, Cheng teaches the semiconductor structure of claim 4, wherein the additional epitaxial layer (source/drain extension contacts 140 on the right in Fig. 1A) has a thickness ranging from about 1 nm to about 10 nm ([0063]: “the source/drain extension contacts 140 are formed with a thickness in a range of about 2 nm to about 4 nm.”).
Regarding claim 23, Cheng teaches the semiconductor device of claim 12, wherein a vertical portion of the epitaxial layer (vertical portions of source/drain extension contacts 140 on the left in Fig. 1A) separates the SID structure (source/drain (S/D) layer 150 on the left in Fig. 1A) from the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A) and the plurality of channel structures (active nanosheet channel layers 112, 114, and 116, Figs. 1A).
Regarding claim 24, Cheng teaches the semiconductor device of claim 10, wherein the epitaxial layer (source/drain extension contacts 140 on the left in Fig. 1A) has a thickness ranging from about 1 nm to about 10 nm ([0063]: “the source/drain extension contacts 140 are formed with a thickness in a range of about 2 nm to about 4 nm.”).
Regarding claim 25, Cheng teaches a semiconductor device, comprising:
a channel structure (active nanosheet channel layer 114, Figs. 1A-C, [0036]) on a substrate (semiconductor substrate 100, Figs. 1A-C, [0036]);
a gate structure (high-k dielectric/metal gate (HKMG) structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Figs. 1A-B, [[0037]) wrapped around the channel structure (active nanosheet channel layer 114, Figs. 1A-B);
an inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A) adjacent to a first end (right end in Fig. 1A) of the channel structure (active nanosheet channel layer 114, Figs. 1A), wherein the inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A) is in contact with the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A); and
an epitaxial layer (source/drain extension contacts 140 on the left in Fig. 1A, [0041]: “… source/drain extension contacts 140 comprise epitaxial layers that are grown on the end portions of the active nanosheet channel layers 112, 114 and 116”) in contact with the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A) and a second end (left end in Fig. 1A) of the channel structure (active nanosheet channel layer 114, Figs. 1A), wherein the second end (left end in Fig. 1A) is opposite to the first end (right end in Fig. 1A).
Regarding claim 26, Cheng teaches the semiconductor device of claim 25, wherein the epitaxial layer (source/drain extension contacts 140, Fig. 1C) is in contact with the substrate (semiconductor substrate 100, Fig. 1C).
Regarding claim 27, Cheng teaches the semiconductor device of claim 25, further comprising a source/drain (SID) structure (source/drain (S/D) layer 150 on the left in Fig. 1A, [0036]) on the epitaxial layer (source/drain extension contacts 140 on the left, Fig. 1A), wherein the epitaxial layer (source/drain extension contacts 140 on the left, Fig. 1A) separates the SID structure (source/drain (S/D) layer 150 on the left in Fig. 1A) from the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A).
Regarding claim 28, Cheng teaches the semiconductor device of claim 25, further comprising:
an additional epitaxial layer (source/drain extension contacts 140 on the right in Fig. 1A, [0041]) in contact with the inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A) and the first end (right end in Fig. 1A) of the channel structure (active nanosheet channel layer 114, Figs. 1A); and
a SID structure (source/drain (S/D) layer 150 on the right in Fig. 1A) in contact with the additional epitaxial layer (source/drain extension contacts 140 on the right in Fig. 1A, [0041]) and the inner spacer structure (gate sidewall spacers 138 on the right in Fig. 1A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hashemi (US 2019/0326288 A1) teaches a nanosheet transistor with asymmetric source/drain connections, which is relevant to all claims.
Kotlyar (US 2020/0105753 A1) teaches a nanosheet transistor with an epitaxial layer between the channels and source/drain regions, which is relevant to all claims
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812