DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 4/16/2026, has been entered. The Applicant has amended claims 1, 10, and 25. Claims 5-6, 14, and 16-20 were canceled previously due to a restriction/election requirement. Accordingly, claims 1-4, 7-13, 15, and 21-28 remain pending in the application.
Priority
Acknowledgment is made of applicant’s claim for the benefit of U.S. Provisional Patent Application No. 63/374,782, titled “Semiconductor Devices with Asymmetric Source/Drain Design,” filed September 7, 2022, and U.S. Provisional Patent Application No. 63/340,274, titled “Strategic Asymmetric SD Design for GAA Performance Enhancement,” filed May 10, 2022.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 2 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
In claim 2, which depends on claim 1, the limitation “the epitaxial layer is in contact with the substrate” does not further limit the semiconductor structure disclosed in amended claim 1, as amended claim 1 includes the same limitation by reciting “an epitaxial layer having a vertical portion in contact with the substrate” on line 6.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, 9-12, and 15, 23-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rodder (US 10,008,583 B1).
Regarding claim 1, Rodder teaches a semiconductor structure (gate-all-around (GAA)
nanosheet (NS) field-effect transistor (FET) 100, Fig. 1; col. 6, lines 20-39), comprising:
a plurality of semiconductor layers (channel regions 106, Fig. 1; col. 6, line 55-56: “In one or more embodiments, the channel layers 106 are formed of silicon (Si).” ) on a substrate (substrate 114, Fig. 1; col 6, lines 61-66);
a gate structure (gate stacks 103, Fig. 1; col. 6, lines 20-39) wrapped around the plurality of semiconductor layers (channel regions 106, Fig. 1);
an inner spacer structure (reverse inner spacers 104, 105, Fig. 1; col. 6, lines 40-54) between the plurality of semiconductor layers (channel regions 106, Fig. 1) and in contact with a first side (right side in Fig. 1) of the gate structure (gate stacks 103, Fig. 1); and
an epitaxial layer (first source electrode region 115, Fig. 1; col. 7, lines 4-9 and col. 10, lines 29-33: “the task of epitaxially re-growing the source and drain electrodes 214, 215 includes a task of epitaxially re-growing a first portion 216, 217 of each of the source and drain electrodes 214, 215, respectively.” where first portion 216 (Fig. 2D) is equivalent to first source electrode region 115 (Fig. 1)) having a vertical portion (vertical portion 119, Fig.1; col. 7, lines 27-33) in contact with the substrate (the bottom of the vertical portion 125 is in contact with the substrate 114, Fig. 1) and a second side (left side in Fig. 1) of the gate structure (gate stacks 103, Fig. 1: the lateral extensions 123 of the vertical portion 119 (col. 7, lines 4-15) are in contact with the gate stacks 103), wherein the second side (left side in Fig. 2H) is opposite to the first side (right side in Fig. 2H) .
Regarding claim 2, Rodder teaches the semiconductor structure of claim 1, wherein the epitaxial layer (first source electrode region 115, Fig. 1) is in contact with the substrate (substrate 114, Fig. 1).
Regarding claim 3, Rodder teaches the semiconductor structure of claim 1, further comprising a source/drain (S/D) structure (second source electrode region 116, Fig. 1; col. 7, lines 4-15) in contact with the epitaxial layer (first source electrode region 115, Fig. 1).
Regarding claim 7, Rodder teaches the semiconductor structure of claim 1, wherein an end portion (right side of channel regions 106, Fig. 1) of the plurality of semiconductor layers (channel regions 106, Fig. 1) is aligned with the first side (right side of gate stacks 103, Fig. 1) of the gate structure (gate stacks 103, Fig. 1: the end portion is aligned with an offset in the horizontal direction in Fig. 1).
Regarding claim 9, Rodder teaches the semiconductor structure of claim 1, wherein the epitaxial layer (first source electrode region 115, Fig. 1) has a thickness (the thickness of the lateral extension 123, Fig. 1) ranging from about 1 nm to about 10 nm (col. 7, lines 54-61: “a vertical height (i.e., a thickness) Hof each of the lateral extensions 123, 129 may be from approximately 2 nm to approximately 6 nm”).
Regarding claim 10, Rodder teaches a semiconductor device (gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) 100, Fig. 1; col. 6, lines 20-39), comprising:
a plurality of channel structures (channel regions 106, Fig. 1; col. 6, line 55-56) on a substrate (substrate 114, Fig. 1; col 6, lines 61-66);
a gate structure (gate stacks 103, Fig. 1; col. 6, lines 20-39) wrapped around the plurality of channel structures (channel regions 106, Fig. 1);
an inner spacer structure (reverse inner spacers 104, 105, Fig. 1; col. 6, lines 40-54) in contact with the gate structure (gate stacks 103, Fig. 1) and adjacent to a first end (right side of channel regions 106, Fig. 1) of the plurality of channel structures (channel regions 106, Fig. 1);
a gate spacer (external spacers 109, Fig. 1, col. 6, lines 36-39) on a sidewall (upper right sidewall of gate stacks 103, Fig. 1) of the gate structure gate stacks 103, Fig. 1) and above the plurality of channel structures (channel regions 106, Fig. 1); and
an epitaxial layer (first source electrode region 115, Fig. 1; col. 7, lines 4-9 and col. 10, lines 29-33: “the task of epitaxially re-growing the source and drain electrodes 214, 215 includes a task of epitaxially re-growing a first portion 216, 217 of each of the source and drain electrodes 214, 215, respectively.” where first portion 216 (Fig. 2D) is equivalent to first source electrode region 115 (Fig. 1)) in contact with a third end (left side ) of the gate structure (gate stacks 103, Fig. 1) and a second end (left side) of the plurality of channel structures (channel regions 106, Fig. 1) , wherein the second end (left side of channel regions 106, Fig. 1) and the third end (left side of gate stacks 103, Fig. 1) are vertically aligned (second end and first end are aligned vertically with an offset) and opposite to the first end (right side in Fig. 1).
Regarding claim 11, Rodder teaches the semiconductor device of claim 10, wherein the epitaxial layer (first source electrode region 115, Fig. 1) comprises a vertical portion (vertical portion 119, Fig.1; col. 7, lines 27-33) in contact with the gate structure (gate stacks 103, Fig. 1: the lateral extensions 123 of the vertical portion 119 (col. 7, lines 4-15) are in contact with the gate stacks 103) and the plurality of channel structures (channel regions 106, Fig. 1) and a horizontal portion (horizontal portion
124, col. 7, lines 21-26) in contact with the substrate (substrate 114, Fig. 1).
Regarding claim 12, Rodder teaches the semiconductor device of claim 10, further comprising a source/drain (S/D) structure (second source electrode region 116, Fig. 1; col. 7, lines 4-15) in contact with the epitaxial layer (first source electrode region 115, Fig. 1).
Regarding claim 15, Rodder teaches the semiconductor device of claim 10, wherein the first end (right side of channel regions 106, Fig. 1) of the plurality of channel structures (channel regions 106, Fig. 1) is under the gate spacer (external spacers 109, Fig. 1).
Regarding claim 23, Rodder teaches the semiconductor device of claim 12, wherein a vertical portion of the epitaxial layer (vertical portion 119, Fig. 1; col. 7, lines 4-15) separates the S/D structure (second source electrode region 116, Fig. 1; col. 7, lines 4-15) from the gate structure external spacers 109, Fig. 1, col. 6, lines 36-39) and the plurality of channel structures (channel regions 106, Fig. 1; col. 6, line 55-56).
Regarding claim 24, Rodder teaches the semiconductor device of claim 10, the epitaxial layer (first source electrode region 115, Fig. 1) has a thickness (the thickness of the lateral extension 123, Fig. 1) ranging from about 1 nm to about 10 nm (col. 7, lines 54-61: “a vertical height (i.e., a thickness) Hof each of the lateral extensions 123, 129 may be from approximately 2 nm to approximately 6 nm”).
Regarding claim 25, Rodder teaches a semiconductor device (gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) 100, Fig. 1; col. 6, lines 20-39), comprising:
a channel structure (channel regions 106, Fig. 1; col. 6, line 55-56) on a substrate (substrate 114, Fig. 1; col 6, lines 61-66);
a gate structure (gate stacks 103, Fig. 1; col. 6, lines 20-39) wrapped around the channel structure (channel regions 106, Fig. 1);
an inner spacer structure (reverse inner spacers 104, 105, Fig. 1; col. 6, lines 40-54) adjacent to a first end (right side of channel regions 106, Fig. 1) of the channel structure (channel regions 106, Fig. 1), wherein the inner spacer structure (reverse inner spacers 104, 105, Fig. 1) is in contact with the gate structure (gate stacks 103, Fig. 1); and
an epitaxial layer (first source electrode region 115, Fig. 1; col. 7, lines 4-9 and col. 10, lines 29-33: “the task of epitaxially re-growing the source and drain electrodes 214, 215 includes a task of epitaxially re-growing a first portion 216, 217 of each of the source and drain electrodes 214, 215, respectively.” where first portion 216 (Fig. 2D) is equivalent to first source electrode region 115 (Fig. 1)) covering end portions (covering the left and right ends of gate stacks 103 over the reverse inner spacers 104 and 105, Fig. 1) of the gate structure (gate stacks 103, Fig. 1) and a second end (left side of channel regions 106, Fig. 1) of the channel structure (channel regions 106, Fig. 1), wherein the second end (left side in Fig. 1) is opposite to the first end (right side in Fig. 1).
Regarding claim 26, Rodder teaches the semiconductor device of claim 25, wherein the epitaxial layer (first source electrode region 115, Fig. 1) is in contact with the substrate (substrate 114, Fig. 1).
Regarding claim 27, Rodder teaches the semiconductor device of claim 25, further comprising a source/drain (S/D) structure (second source electrode region 116, Fig. 1; col. 7, lines 4-15) on the epitaxial layer (first source electrode region 115, Fig. 1), wherein the epitaxial layer (first source electrode region 115, Fig. 1) separates the S/D structure (second source electrode region 116, Fig. 1) from the gate structure (gate stacks 103, Fig. 1).
Examiner notes that Rodder teaches claims 1-3, 7, 9-12, 15, and 23-27, and Rodder in view of Cheng (US 2021/0210598 A1) teaches claim 8 (see 103 rejections below), but these references do not specifically cover claims 4, 13, 21-22, and 28, as these claims target at features of a structurally different part of the semiconductor structure (the portion of the epitaxial layer on the right side versus the left side of the semiconductor structure of the current application). Another set of rejections are being made below over Cheng (US 2021/0210598 A1) for claims 10, 12-13, 15, 23, 25, and 27-28 (now also covering claims 13 and 28), so as to cover claims 1-3, 7-13, 15, and 23-28 in total. There has been no prior art identified that teaches claims 4, and therefore claims 21-22, which depend on claim 4.
Claims 10, 12-13, 15, 23, 25, and 27-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (US 2021/0210598 A1).
Regarding claim 10, Cheng teaches a semiconductor device (semiconductor structure, Fig. 16, [0022]), comprising:
a plurality of channel structures (channel nanosheets 108, Fig. 16, [0033]) on a substrate (substrate 102, Fig. 16, [0032]);
a gate structure (high-k dielectric/metal gate 136, Fig. 16, [0056]) wrapped around the plurality of channel structures (channel nanosheets 108, Fig. 16);
an inner spacer structure (inner spacer 116, Fig. 16, [0055]) in contact with the gate structure (high-k dielectric/metal gate 136, Fig. 16) and adjacent to a first end (right side of channel nanosheets 108, Fig. 16) of the plurality of channel structures (channel nanosheets 108, Fig. 16);
a gate spacer (gate spacer 112, Fig. 16, [0054]) on a sidewall (upper right sidewall of high-k dielectric/metal gate 136, Fig. 16) of the gate structure (high-k dielectric/metal gate 136, Fig. 16) and above the plurality of channel structures (channel nanosheets 108, Fig. 16); and
an epitaxial layer (isolation layers 132 on the left side, Fig. 16, [0055]: “… the isolation layers 132 comprises doped silicon (Si) epitaxially grown within the channel recesses 118”) in contact with a third end (left side where the isolation layer 132 contacts the gate high-k dielectric/metal gate 136, Fig. 16) of the gate structure (high-k dielectric/metal gate 136, Fig. 16) and a second end (left side where the isolation layer 132 contacts channel nanosheets 108, Fig. 16) of the plurality of channel structures (channel nanosheets 108, Fig. 16) , wherein the second end (left side where the isolation layer 132 contacts channel nanosheets 108, Fig. 16) and the third end (left side where the isolation layer 132 contacts the gate high-k dielectric/metal gate 136, Fig. 16) are vertically aligned (second end and first end are aligned vertically) and opposite to the first end (right side in Fig. 16).
Regarding claim 12, Cheng teaches the semiconductor device of claim 10, further comprising a source/drain (SID) structure (source/drain (S/D) region 124 on the left in Fig. 16, [0045]) in contact with the epitaxial layer (isolation layers 132 on the left side, Fig. 16).
Regarding claim 13, Cheng teaches the semiconductor device of claim 10, further comprising:
an additional epitaxial layer (isolation layers 132 on the right side, Fig. 16) in contact with the first end (right side) of the plurality of channel structures (channel nanosheets 108, Fig. 16); and
a S/D structure (source/drain (S/D) region 124 on the right in Fig. 16, [0045]) in contact with the additional epitaxial layer (isolation layers 132 on the right side, Fig. 16) and the inner spacer structure (inner spacer 116, Fig. 16).
Regarding claim 15, Cheng teaches the semiconductor device of claim 10, wherein the first end (right side of channel nanosheets 108, Fig. 16) of the plurality of channel structures (channel nanosheets 108, Fig. 16) is under the gate spacer (gate spacer 112 on the right in Fig. 16).
Regarding claim 23, Cheng teaches the semiconductor device of claim 12, wherein a vertical portion of the epitaxial layer (wing segments 134, Fig. 16, [0055]) separates the S/D structure (source/drain (S/D) region 124 on the right in Fig. 16) from the gate structure (high-k dielectric/metal gate 136, Fig. 16) and the plurality of channel structures (channel nanosheets 108, Fig. 16, see Figs. 14-15 showing that without the wing segments the source/drain regions would be in contact with the channel nanosheets 108 and sacrificial gate structures (sacrificial nanosheets 106)).
Regarding claim 25, Cheng teaches a semiconductor device (semiconductor structure, Fig. 16, [0022]), comprising:
a channel structure (semiconductor structure, Fig. 16, [0022]) on a substrate (substrate 102, Fig. 16, [0032]);
a gate structure (high-k dielectric/metal gate 136, Fig. 16, [0056]) wrapped around the channel structure (channel nanosheets 108, Fig. 16);
an inner spacer structure (inner spacer 116, Fig. 16, [0055]) adjacent to a first end (right end in Fig. 16) of the channel structure (semiconductor structure, Fig. 16), wherein the inner spacer structure (inner spacer 116, Fig. 16) is in contact with the gate structure (high-k dielectric/metal gate 136, Fig. 16); and
an epitaxial layer (isolation layers 132 on the left side, Fig. 16, [0055]: “… the isolation layers 132 comprises doped silicon (Si) epitaxially grown within the channel recesses 118”) covering end portions (covering parts of the left and right ends, Fig. 16) of the gate structure (HKMG structure 170 comprising gate dielectric layer 172 and metal gate structure 174, Fig. 1A) and a second end (left end in Fig. 16) of the channel structure semiconductor structure, Fig. 16), wherein the second end (left end in Fig. 16) is opposite to the first end (right end in Fig. 16).
Regarding claim 27, Cheng teaches the semiconductor device of claim 25, further comprising a source/drain (S/D) structure (source/drain (S/D) region 124 on the left in Fig. 16, [0045]) on the epitaxial layer (isolation layers 132 on the left side, Fig. 16), wherein the epitaxial layer (source/drain extension contacts 140 on the left, Fig. 1A) separates the S/D structure (source/drain (S/D) region 124 on the left in Fig. 16) from the gate structure (high-k dielectric/metal gate 136, Fig. 16; see Figs. 14-15 showing that the source/drain region 124 would be in contact with the high-k dielectric/metal gate 136 if the isolation layer 132 would not be in between).
Regarding claim 28, Cheng teaches the semiconductor device of claim 25, further comprising:
an additional epitaxial layer (isolation layers 132 on the right side, Fig. 16) in contact with the inner spacer structure (inner spacer 116, Fig. 16) and the first end (right end in Fig. 16) of the channel structure (semiconductor structure, Fig. 16); and
a S/D structure (source/drain (S/D) region 124 on the right in Fig. 16) in contact with the additional epitaxial layer (isolation layers 132 on the right side, Fig. 16) and the inner spacer structure (inner spacer 116, Fig. 16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Rodder (US 10,008,583 B1) in view of Cheng (US 2021/0210598 A1).
Regarding claim 8, Rodder teaches the semiconductor structure of claim 1, wherein the epitaxial layer (first source electrode region 115, Fig. 1) comprises a silicon epitaxial layer (col. 7, lines 51-53: “the first source electrode region 115 and the first drain electrode region 117 may be formed of undoped Si”).
Rodder does not teach that the epitaxial layer is doped with a dopant.
Cheng, on the other hand, teaches a semiconductor structure (semiconductor structure, Fig. 16, [0022]) with an epitaxial layer (isolation layers 132 on the left side, Fig. 16, [0055]: “… the isolation layers 132 comprises doped silicon (Si) epitaxially grown within the channel recesses 118”), wherein the epitaxial layer is doped with a dopant ([0055]: “the isolation layers 132 comprises doped silicon (Si) epitaxially grown within the channel recesses 118”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that doping the epitaxial layer would increase the conductivity of the epitaxial layer and reduce the on resistance of the channels. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor structure (GAA NS FET 100, Fig. 1) of Rodder to include dopants in the epitaxial layer, as taught by Cheng, to improve the conductivity of the transistor.
Allowable Subject Matter
Claims 4 and 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4, disclosing the limitation that “a S/D structure in contact with … the inner spacer structure”, would be allowable if this limitation is incorporated in a claim combining claims 1 and 4.
Regarding the closest prior art, Rodder teaches all the limitations of claim 1 (see claim 1 rejection above), and further teaches
an additional epitaxial layer (first drain electrode region 117, Fig. 1; col. 7, lines 4-15) in contact with the plurality of semiconductor layers (channel regions 106, Fig. 1) and the inner spacer structure (reverse inner spacers 104, 105, Fig. 1); and
a S/D structure (second drain electrode region 118, Fig. 1; col. 7, lines 4-15) in contact with the additional epitaxial layer (first drain electrode region 117, Fig. 1).
Rodder, however, fails to teach that a S/D structure in contact with the inner spacer structure. There has been no motivation to modify the semiconductor structure of Rodder to make the S/D structure in contact with the inner spacer structure. Therefore, claim 4 is objected.
Claims 21-22-, are also objected as these claims depend directly on claim 4.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 10, and 25 per response dated on 4/16/2026. Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amended independent claims 1, 10, and 25 overcame the 35. U.S.C. 102 rejections made in the non-final office action based on Cheng (US 2020/0266060 A1).
However, amended claims 1 is now rejected under new grounds based on a new prior-art, Rodder (US 10,008,583 B1), in the current office action. Rejections are also made on claims 2-3 and 7-9, which all depend on claim 1. The rejection on claim 4 and 21-22 are withdrawn, however, as no prior-art made claim 4 anticipated or obvious after amended claim 1. Claim 4 is now objected due to its dependency on claim 1 as detailed above. Claims 21-22 are also objected because these claims depend on claim 4.
Amended independent claims 10 and 25 are also rejected under new grounds based on both Rodder and a new prior art, Cheng (US 2021/0210598 A1). Dependent claims 11-13 15, 23-24, and 26-28 are also rejected by these prior art.
For the purpose of compact prosecution, the Examiner notes that the epitaxial layer and source/drain regions in the current application are asymmetric in the left and right side of the channel structures. Therefore, incorporating limitations that point out this asymmetry into independent claims 1, 10, and 25 might make these claims overcome the rejections based on Rodder and Cheng, as in both of these references the epitaxial layer and source/drain regions have a symmetrical structure around the channel structures.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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