DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 09 Mar 2023 for application number 18/181,430. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-25 are presented for examination (Elected claims 1-15 are examined below, along with newly added claims 21-25. Non-elected claims 16-20 have been withdraw; see Election/Restriction below).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09 Mar 2023 and 07 Jan 2025 were filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 03 Dec 2025 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03 Dec 2025.
Claim Objections
Claim 7 is objected to because of the following informalities: clarification is need to express that “the second etching” on line 1 refers to the “etching back” on line 5 of claim 6, not the “second etching” on line 9 of claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The terms “about 50˚” and “about 60˚” in claim 4 are relative terms which render the claim indefinite. The terms “about 50˚” and “about 60˚” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 6-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. [hereinafter as Jung] (US 2020/0365692 A1).
In reference to claim 1, Jung teaches A method, comprising:
receiving a workpiece comprising:
a channel region [area of semiconductor patterns 124/sacrificial patterns 114; Fig. 12, para 0070] extending from a substrate [substrate 100/active pattern 105; Fig. 12, paras 0068-0069] and comprising a plurality of channel layers [semiconductor patterns 124; Fig. 12, para 0070] interleaved by a plurality of sacrificial layers [sacrificial patterns 114; Fig. 12, para 0070],
a source/drain region [area of opening 190; Fig. 12, para 0069] adjacent the channel region [area of 124/112], and
a dummy gate structure [dummy gate structure 175; Fig. 12, para 0069] over the channel region [area of 124/112];
performing a first etching [etching process to create 190; para 0069] process to recess the source/drain region [area of 190] to form a source/drain opening [190], the source/drain opening [190] exposing the substrate [100/105];
performing a second etching [further etching process to create 195; para 0069] process to the substrate, resulting in a V-shape groove [first recess 195; Fig. 12, para 0069] in the substrate [105/100];
forming a dielectric feature [second spacer layer 210 and remaining growth prevention pattern 225; Fig. 13, para 0075, 0078] in the V-shape groove [195];
after the forming of the dielectric feature [210/225], forming a source/drain feature [second epitaxial layer 240; Fig. 17, para 0085] on the dielectric feature [210/225] to fill the source/drain opening [190];
selectively removing the dummy gate structure [175 is removed; Fig. 18, para 0092];
selectively removing the plurality of sacrificial layers [114 is removed to create second opening 280; Fig. 18, para 0092]; and
forming a metal gate stack [gate structure 330; Fig. 18, para 0095; components of 330 may be metal; para 0039] to wrap around each channel layer of the plurality of channel layers [124].
In reference to claim 4, Jung teaches The method of claim 1, wherein an angle between a sidewall of the V-shape groove [195] and a bottom surface of the substrate [105/100] is between about 50° and about 60° [the angle of the “V” at 195 appears to be in the claimed range; Fig. 14].
In reference to claim 6, Jung teaches The method of claim 1, further comprising:
selectively etching the sacrificial layers [114] to form inner spacer recesses [second recesses 200; Fig. 13, para 0073];
conformally depositing a dielectric layer [210] over the workpiece to fill the inner spacer recesses [200; Fig. 13, para 0075]; and
etching back the dielectric layer [210] to form inner spacer features [inner spacer 220; Fig. 14, para 0077] in the inner spacer recesses [200] and a protection layer extending along sidewall surfaces of the channel layers [as 210 is gradually etched, a thin layer of 210, i.e. protection layer, may remain before fully etched].
In reference to claim 7, Jung teaches The method of claim 6, wherein the performing of the second etching process further removes the protection layer [as 210 is gradually etched, a thin layer of 210, i.e. protection layer, may remain (e.g. on the sidewalls) before fully etched, and removing the thin layer, i.e. protection layer].
In reference to claim 8, Jung teaches The method of claim 1, further comprising:
after the forming of the dielectric feature [210/225], forming a low-k dielectric layer [first air gap 260; Fig. 17, para 0088; an air gap is known to be low-k] on the dielectric feature [210/225],
wherein the source/drain feature [240] is spaced apart from the low-k dielectric layer [260] by the dielectric feature [210/225].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 and 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Donaton et al. [hereinafter as Donaton] (US 2016/0181253 A1).
In reference to claim 2, Jung teaches the invention of claim 1.
Jung teaches The method of claim 1, wherein the forming of the dielectric feature in the V- shape groove comprises:
conformally depositing a dielectric layer [210/225] over the workpiece, the dielectric layer [210/225] comprising a first portion extending along sidewalls of the source/drain opening [190] and a second portion in the V-shape groove [210/225 is on sidewalls of 190 and in 195]; and
performing a third etching process to selectively remove the first portion of the dielectric layer [210], leaving the treated second portion of the dielectric layer [210/225] in the V-shape groove [210 is etched to leave 225 in 195; Fig. 14, para 0078].
However, Jung does not explicitly teach performing a plasma treatment to the second portion of the dielectric layer.
Donaton teaches performing a plasma treatment to the second portion of the dielectric layer [para 0034 discloses treating a dielectric layer with plasma curing].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Jung and Donaton before the effective filing date of the claimed invention, to include the plasma treatment as disclosed by Donaton into the semiconductor device of Jung in order to obtain a semiconductor device in which a portion of dielectric is plasma treated.
One of ordinary skill in the art would be motivated to obtain a semiconductor device in which a portion of dielectric is plasma treated to provide the predictable result of hardening [Donaton, para 0034] the dielectric to provide structural stability.
In reference to claim 21, Jung teaches A method, comprising:
forming a fin-shaped structure [fin structure; Figs. 8-10, para 0062] over a substrate [substrate 100/active pattern 105; Fig. 12, paras 0068-0069];
recessing a source/drain region [area of opening 190; Fig. 12, para 0069] of the fin-shaped structure [fin structure] to form a trench [opening 190; Fig. 12, para 0069] extending into the substrate [100/105];
depositing a material layer [second spacer layer 210 and remaining growth prevention pattern 225; Fig. 13, para 0075, 0078] over the substrate [100/105], wherein the material layer [210/225] comprises a vertical portion [210] extending along a sidewall surface of the fin-shaped structure [fin structure] and a non-vertical portion [225] extending from the vertical portion [210]; and
forming a source/drain feature [second epitaxial layer 240; Fig. 17, para 0085] over the non-vertical portion [225] and in the trench [190].
However, Jung does not explicitly teach performing a treatment to the non-vertical portion, thereby increasing etch selectivity between the vertical portion and the non-vertical portion;
after the performing of the treatment, selectively removing the vertical portion without substantially etching the non-vertical portion.
Jung and Donaton teach performing a treatment [Donaton, para 0034 discloses treating a dielectric layer with plasma curing; this is known to the etch selectivity] to the non-vertical portion [225 of Jung], thereby increasing etch selectivity between the vertical portion [210 of Jung] and the non-vertical portion [225 of Jung];
after the performing of the treatment, selectively removing [210 is etched to leave 225 in 195; Fig. 14, para 0078 of Jung] the vertical portion [210 of Jung] without substantially etching [due to the increased etch selectivity created by Donaton’s plasma curing process] the non-vertical portion [225 of Jung].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Jung and Donaton before the effective filing date of the claimed invention, to include the plasma treatment as disclosed by Donaton into the semiconductor device of Jung in order to obtain a semiconductor device in which a portion of dielectric is plasma treated.
One of ordinary skill in the art would be motivated to obtain a semiconductor device in which a portion of dielectric is plasma treated to provide the predictable result of hardening [Donaton, para 0034] the dielectric to provide structural stability, thereby also increasing etch selectivity.
In reference to claim 22, Jung and Donaton teach the invention of claim 21.
Jung teaches The method of claim 21, wherein, in a cross-sectional view cut through the fin-shaped structure [fin structure] and the source/drain feature [240], the non-vertical portion [225] has a top surface and a bottom surface connecting two end points of the top surface [Fig. 17 depicts this characteristic of 225], and the bottom surface has a V-shape profile [Fig. 17 depicts 225 with a V-shaped bottom surface].
In reference to claim 23, Jung and Donaton teach the invention of claim 21.
Jung teaches The method of claim 21, wherein the fin-shaped structure comprises a plurality of channel layers [semiconductor patterns 124; Fig. 12, para 0070] and a plurality of sacrificial layers [sacrificial patterns 114; Fig. 12, para 0070], and the method further comprises:
selectively removing the plurality of sacrificial layers [114 is removed to create second opening 280; Fig. 18, para 0092]; and
forming a gate structure [gate structure 330; Fig. 18, para 0095; components of 330 may be metal; para 0039] wrapping around and over the plurality of channel layers [124].
In reference to claim 24, Jung and Donaton teach the invention of claim 23.
Jung teaches The method of claim 23, further comprising:
after forming the trench [190], recessing the plurality of sacrificial layers [114] to form a plurality of recesses [second recesses 200; Fig. 13, para 0073];
depositing a dielectric layer [210] over the substrate [100/105] and in the plurality of recesses [200; Fig. 13, para 0075]; and
etching back the dielectric layer [210] to form a plurality of inner spacer features [inner spacer 220; Fig. 14, para 0077] in the plurality of recesses [200].
In reference to claim 25, Jung and Donaton teach the invention of claim 24.
Jung teaches The method of claim 24, wherein, after the etching back, a portion of the dielectric layer extends along sidewalls of the plurality of channel layers [as 210 is gradually etched, a thin layer of 210 may remain before fully etched; this thin layer would extend along the sidewalls].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Donaton further in view of Wang et al. [hereinafter as Wang] (US 2021/0407807 A1).
In reference to claim 3, Jung and Donaton teach the invention of claim 2.
Jung teaches The method of claim 2, wherein the dielectric layer comprises silicon nitride [para 0042 discloses that inner spacer 220 (which is made from 210/225), may include silicon nitride].
However, Jung and Donaton do not explicitly teach the third etching process comprises implementing dilute hydrofluoric acid (DHF).
Wang teaches the third etching process comprises implementing dilute hydrofluoric acid (DHF) [para 0077 discloses etching a dielectric using dFH].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Jung, Donaton, and Wang before the effective filing date of the claimed invention, to include the etching process as disclosed by Wang into the semiconductor device of Jung and Donaton in order to obtain a semiconductor device in which a portion of dielectric is etched using dHF.
One of ordinary skill in the art would be motivated to obtain a semiconductor device in which a portion of dielectric is etched using dHF to provide the predictable result of a known, cost-effective, simple, and selective way of etching.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Xie et al. [hereinafter as Xie] (US 2023/0187508 A1).
In reference to claim 5, Jung teaches the invention of claim 1.
However, Jung does not explicitly teach The method of claim 1, wherein the second etching process comprises a wet etching process.
Xie teaches The method of claim 1, wherein the second etching process comprises a wet etching process [para 0089 discloses a wet etching process to create a V-shape region].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Jung and Xie before the effective filing date of the claimed invention, to include the wet etching process as disclosed by Xie into the semiconductor device of Jung in order to obtain a semiconductor device in which a region is etched into a V-shape using a wet etching process.
One of ordinary skill in the art would be motivated to obtain a semiconductor device in which a region is etched into a V-shape using a wet etching process to provide the predictable result of a known, cost-effective, simple, and selective way of etching.
Claim(s) 9-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Zhu et al. [hereinafter as Zhu] (US 7,528,027 B1).
In reference to claim 9, Jung teaches A method, comprising:
forming a dummy gate structure [dummy gate structure 175; Figs 8-10, para 0062] engaging a semiconductor fin [fin structure; Figs. 8-10, para 0062], the semiconductor fin [fin structure] comprising a top portion of a substate [substrate 100/active pattern 105; Fig. 12, paras 0068-0069] and a vertical stack of alternating channel layers [semiconductor patterns 124; Fig. 12, para 0070] and sacrificial layers [sacrificial patterns 114; Fig. 12, para 0070] thereon;
recessing a portion of the semiconductor fin [fin structure] not covered by the dummy gate structure [175] to form a source/drain opening [opening 190; Fig. 12, para 0069];
selectively recessing the sacrificial layers [114] to form inner spacer recesses [second recesses 200; Fig. 13, para 0073];
forming inner spacer features [inner spacer 220; Fig. 14, para 0077] in the inner spacer recesses [200];
performing a etching process [etching process to create 190; para 0069] to selectively etch the top portion of the substrate [100/105] exposed by the source/drain opening [190], thereby forming an extended source/drain opening [further etching process to create first recess 195 and 190; para 0069];
forming an isolation structure [growth prevention pattern 225; Fig. 13, para 0078]] in the extended source/drain opening [190/195];
forming a source/drain feature [second epitaxial layer 240; Fig. 17, para 0085] on the isolation structure [225] and in the extended source/drain opening [190/195]; and
replacing the sacrificial layers [114 is removed to create second opening 280; Fig. 18, para 0092] and the dummy gate structure [175 is removed; Fig. 18, para 0092] with a metal gate stack [gate structure 330; Fig. 18, para 0095; components of 330 may be metal; para 0039].
However, Jung does not explicitly teach that the etching process is a wet etching process.
Zhu teaches a wet etching process [col. 2, lines 52-62 disclose a wet etching process].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Jung and Zhu before the effective filing date of the claimed invention, to include the wet etching process as disclosed by Zhu into the semiconductor device of Jung in order to obtain a semiconductor device in which a region is etched using a wet etching process.
One of ordinary skill in the art would be motivated to obtain a semiconductor device in which a region is etched using a wet etching process to provide the predictable result of a known, cost-effective, simple, and selective way of etching.
In reference to claim 10, Jung and Zhu teach the invention of claim 9.
Zhu teaches The method of claim 9, wherein, the performing of the wet etching process comprises implementing ammonia [col. 2, lines 52-62 disclose a wet etching process using ammonia].
In reference to claim 11, Jung and Zhu teach the invention of claim 9.
Jung teaches The method of claim 9, wherein, in a cross-sectional view, the extended source/drain opening [190/195] comprises a V-shape lower portion [first recess 195; Fig. 12, para 0069; 195 is V-shaped].
In reference to claim 12, Jung and Zhu teach the invention of claim 9.
Jung teaches The method of claim 9, wherein the forming of the source/drain feature [240] comprising forming a doped epitaxial layer [240 may include doped layers; para 0046] in the extended source/drain opening [190/195], wherein the doped epitaxial layer [240 may include doped layers; para 0046] is spaced apart from the substrate [100/105] by the isolation structure [225].
In reference to claim 13, Jung and Zhu teach the invention of claim 9.
Jung teaches The method of claim 9, wherein the isolation structure [225] comprises a dielectric layer [second spacer layer 210 and remaining growth prevention pattern 225; Fig. 13, para 0075, 0078] on the substrate [100/105] and an air gap [first air gap 260; Fig. 17, para 0088] between the dielectric layer [225] and the source/drain feature [240].
In reference to claim 15, Jung and Zhu teach the invention of claim 9.
Zhu teaches The method of claim 9, wherein the substrate comprises (100) silicon [col. 2, line 34 discloses a (100) silicon substrate], and the extended source/drain opening exposes (111) crystallographic planes of the substrate [col. 2, lines 52-62 disclose a wet etching process exposing a (111) plane].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Zhu further in view of Donaton.
In reference to claim 14, Jung and Zhu teach the invention of claim 9.
Jung teaches The method of claim 9, wherein the forming of the isolation structure comprises:
conformally depositing a dielectric layer [second spacer layer 210 and remaining growth prevention pattern 225; Fig. 13, para 0075, 0078] in the extended source/drain opening [190/195].
However, Jung and Zhu do not explicitly teach:
performing a treatment to a portion of the dielectric layer in direct contact with the substrate without treating a remaining portion of the dielectric layer.
Donaton teaches performing a treatment to a portion of the dielectric layer in direct contact with the substrate without treating a remaining portion of the dielectric layer [para 0034 discloses treating a dielectric layer with plasma curing; it would have been obvious to one of ordinary skill in the art to plasma treat a portion of the dielectric].
Jung and Donaton further teach:
selectively removing the remaining portion of the dielectric layer [210 of Jung] without removing the treated portion [225 of Jung, plasma treated by Zhu] of the dielectric layer [210 of Jung], thereby forming the isolation structure [225 of Jung]
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Jung, Zhu, and Donaton before the effective filing date of the claimed invention, to include the plasma treatment as disclosed by Donaton into the semiconductor device of Jung and Zhu in order to obtain a semiconductor device in which a portion of dielectric is plasma treated.
One of ordinary skill in the art would be motivated to obtain a semiconductor device in which a portion of dielectric is plasma treated to provide the predictable result of hardening [Donaton, para 0034] the dielectric to provide structural stability.
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898