DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/29/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al., U.S. Pat. Pub. 2020/0176390, hereafter Chen.
Regarding claim 1, Chen discloses (Fig. 13) a semiconductor device, comprising:
a dielectric layer [30] disposed on a substrate [10] (Fig. 1);
a stop layer [40] disposed on the dielectric layer [30];
a via [46] extending in the stop layer [40] and the dielectric layer [30]; and
a memory device [50] (par. [0039]-[0044]) disposed on and electrically connected to the via [46], wherein the memory device [50] and the dielectric layer [30] are disposed on two opposite sides of the stop layer [40].
Chen further discloses (Fig. 13, see also Figs 1-12 for labels)
an alignment mark [48], comprising:
a trench [36] disposed in the dielectric layer [30] (see Fig. 3); and
a conductive layer [48] (par. [0033], Fig. 4) covering a sidewall and a bottom surface of the trench [46],
wherein the conductive layer [48] in the trench [36] has a groove (see Fig.4).
Chen fails to explicitly disclose wherein a bottom surface of the trench is lower (see Fig. 3) than a bottom surface of the via.
However, this limitation is obvious over Chen. Chen explicitly teaches forming the alignment mark trench with dimensions such that the conductive layer forms a concave groove, while the via opening has a smaller dimension so it fully fills (Chen, par. [0034]: “In the circuit area CA, the openings 34 are fully filled with the first conductive layer 45 due to the small dimension…”). While Chen does not explicitly state the trench bottom is lower than the via bottom in the text, optimizing the relative depths of the trench and via to ensure the via fills completely while the trench provides a sufficient groove for alignment is a matter of routine design choice. Furthermore, Chen’s Fig. 3 clearly depicts the trench [36] extending deeper into the dielectric layer [30] than the via opening [34]. Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention to modify Chen such that the bottom surface of the trench is lower than the bottom surface of the via to achieve the desired fill characteristics taught by Chen. In Re Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP 2144.04.IV.A).
Regarding claim 4, Chen discloses everything as applied above. Chen further discloses (Fig. 13)
wherein a top surface of the conductive layer [48], a top surface of the stop layer [40], and a top surface of the via [46] are coplanar.
Regarding claim 5, Chen discloses everything as applied above. Chen further discloses (Fig. 13)
wherein a first top surface of the dielectric layer [30] adjacent to the conductive layer [48] and a second top surface of the dielectric layer [30] adjacent to the via [46] are in coplanar.
Regarding claim 6, Chen discloses everything as applied above. Chen further discloses (Fig. 13)
wherein the dielectric layer [30] adjacent to the conductive layer [48] and the dielectric layer [30] adjacent to the via [46] have flat surfaces.
Regarding claim 7, Chen discloses everything as applied above. Chen further discloses (Fig. 4, par. [0037]) a depth of the groove between 300 and 800 angstroms (one of the embodiments lies inside the range, which is between 30 nm and 80 nm in Chen’s nm units).
Regarding claim 8, Chen discloses everything as applied above. Chen fails to explicitly disclose
wherein a ratio of a depth of the trench to a depth of the via is greater than 1.5.
However, it would have been obvious to one having ordinary skill in the art prior to the effective date of the instant application to adjust the relative depth dimensions of the via and the trench. The Federal Circuit has held that where the only difference between the prior art and the claims is a recitation of relative dimensions, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct. In Re Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP 2144.04.IV.A).
To the extent Applicant might argue this specific ratio provides the functional benefit of allowing the via to fill completely while forming a sufficient groove in the trench, Chen explicitly recognizes and teaches this exact functional relationship (Chen, par. [0034]: “the openings 34 are fully filled… due to the small dimension” while the trench 36 forms a “concave portion”). Because the prior art already recognizes the need to vary dimensions to achieve this exact result, optimizing the depth ratio to greater than 1.5 to ensure adequate alignment contrast while filling the via is a matter of routine optimization and design choice.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et. al., U.S. Pat. Pub. 2020/0176390, hereafter Chen, in view of Kuo et. al., U.S. Pat. Pub. 2021/0013395, hereafter Kuo.
Regarding claim 9, Chen discloses everything as applied above. Chen fails to explicitly disclose further comprising: a plurality of spacers disposed on sidewalls of the memory device.
However, Kuo discloses (Fig. 1) further comprising:
a plurality of spacers [20] disposed on sidewalls of the memory device [150].
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to add spacers of Kuo because such spacers protect side surfaces of the sensitive memory element.
Response to Arguments
Applicant’s arguments, see p. 7, filed 06/29/2026, with respect to the rejection under 35 U.S.C. 112(a) have been fully considered and are persuasive. The rejection of claims 1-9 under 35 U.S.C. 112(a) has been withdrawn.
Applicant’s arguments with respect to the prior art rejections of claims 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. To the degree that Applicant’s arguments on pp. 9-11 regarding the Chen reference are still relevant to the current rejections, the Examiner responds as follows:
Regarding the location of the trench: To the extent Applicant argues Chen’s trench [36] does not meet the claimed structural arrangement, the Examiner notes that Chen explicitly discloses patterning both the CMP stop layer [40] and the underlying ILD layer [30] to form the trench opening [36] (Chen, par. [0032] and Fig. 3). Therefore, Chen’s trench extends into and is “disposed in the dielectric layer [30]” exactly as claimed.
Regarding teaching away and relative dimensions: Applicant argues that Chen teaches away from the claimed invention or fails to teach the specific relative dimensions (such as the trench bottom being lower than the via bottom, or the >1.5 depth ratio). The Examiner disagrees. A reference does not teach away if it merely expresses a general preference for an alternative but does not criticize, discredit, or otherwise discourage investigation into the claimed invention. Chen does not criticize altering the relative depths of the trench and via. On the contrary, Chen explicitly teaches the core functional principle relied upon by Applicant: sizing the via opening to be small enough to fully fill with conductive material, while sizing the alignment trench to be large enough to leave a concave groove (Chen, par. [0034]). Because Chen already recognizes and utilizes this functional relationship, optimizing the specific depth ratio or relative bottom surface depths to ensure this exact result is a matter of routine design choice and predictable optimization, not a teaching away.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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/VICTOR V BARZYKIN/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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