DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/18/2026 has been entered.
Claim Objections
Claim 10 is objected to because of the following informalities: “plurality of detection” in lines 1-2 on p.5 should be plurality of detection regions. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Bajaj et. al., U.S. Pat. Pub. 2022/0392810, hereafter ’10, in view of Bajaj et. al., U.S. Pat. Pub. 2022/0392810, hereafter ’10, in view of Wang et. al., U.S. Pat. Pub. 2022/0246775, hereafter ’75.
Regarding claim 1, ’10 discloses (Figs 1-6, see Fig. 6B in particular, other embodiments in Figs 6A, 2C, 2D also read on claim 1) a semiconductor device comprising:
a substrate [102], wherein the substrate has a substrate body and a plurality of detection (par. [0024]) regions [110] disposed on a top surface of the substrate body, wherein one of the plurality of detection regions includes a luminescent material (abstract); and
an overlapping layer [112] disposed on the substrate body, wherein the overlapping layer has a plurality of holes [108] (see Figs 2B-2D for labels), and each one of the plurality of detection regions [110] corresponds to each one of the plurality of holes.
’10 fails to explicitly disclose further comprising:
the plurality of detection regions merged in the substrate body, wherein a top surface of the plurality of detection regions is coplanar with a top surface of the substrate body, and the substrate body surrounds a bottom portion of each one of the plurality of detection regions; and
a plurality of filling pillars, wherein each one of the plurality of filling pillars is disposed on each one of the plurality of detection regions, and wherein each of the plurality of filling pillars fills up each of the plurality of holes, so that a top surface of each of the plurality of filling pillars is completely coplanar with a top surface of the overlapping layer.
However, ’75 discloses (Fig 19E) further comprising (Fig. 19E)
the plurality of detection regions [P-InGaAs] merged in the substrate body [p-Si], wherein a top surface of the plurality of detection regions is coplanar with a top surface of the substrate body (see Fig. 19E, p-Si side, and the substrate body [p-Si] surrounds a bottom portion of each one of the plurality of detection region [p-InGaAs]; and
a plurality of filling pillars ( I-InGaAs pillars in Fig. 19E), wherein each one of the plurality of filling pillars is disposed on each one of the plurality of detection regions (the interface of I-InGaAs pillars with p-Si substrate), and wherein each of the plurality of filling pillars fills up each of the plurality of holes, so that a top surface of each of the plurality of filling pillars is completely coplanar with a top surface of the overlapping layer [1944].
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the structure of the detector device of ’10 with the teachings of conventional pillar detector of ‘75 because ’75 teaches (par. [0012]) that these microstructures increase absorption and optimizes detection.
Regarding claim 2, ’10 in view of ’75 discloses everything as applied above. ’10 further discloses (Figs. 6A, 6B) wherein the top surface of the substrate body [102] has a plurality of recesses (not labeled), and each one of the plurality of detection regions [110] corresponds to and is disposed in each one of the plurality of recesses.
Regarding claim 4, ’10 in view of ’75 discloses everything as applied above. ’10 further discloses wherein the substrate body includes a first metal material (par. [0017]), and one of the plurality of detection regions includes a second metal material, wherein the second metal material is the luminescent material (par. [0038], [10025] metal nanoparticles are fluorescent).
Regarding claim 5, ’10 in view of ’75 discloses everything as applied above. ‘10 further discloses (par. [0038]-[0040]) wherein the luminescent material includes Cu+, Ag+, In+, V2+, Co2+, Sn2+, Eu2+, Mn2+, Ni2+, Pb2+, Bis+, Prs+, Nd2+, Sn2+, Eu3+, Gd3+, Tb3+, Dy3+, Ho3+, Tm3+, Yb3+, Ti3+, Ce3+, or a combination thereof.
Regarding claim 7, ’10 in view of ’75 discloses everything as applied above. ’10 further discloses (par. [0019]) wherein one of the plurality of holes has an aspect ratio of from 5:1 to 100:1.
Claims 10, 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bajaj et. al., U.S. Pat. Pub. 2022/0392810, hereafter ’10, in view of Kim et. al., US. Pat. Pub. 2015/0115154, hereafter ’54, and further in view of Wang et. al., U.S. Pat. Pub. 2022/0246775, hereafter ’75.
Regarding claim 10, ’10 discloses (Figs 1-6) method of manufacturing a semiconductor device comprising:
providing a substrate body [102];
disposing an overlapping layer [112] on the substrate body [102];
forming a plurality of holes [108] in the overlapping layer and exposing an exposed portion of the substrate body;
disposing a plurality of detection (par. [0024]) regions [110] on the substrate body (Fig. 2C-2D) or in the substrate body (Fig. 6B) through the plurality of holes, wherein one of the plurality of detection regions includes a luminescent material (abstract, metal nanoparticles are luminescent);
’10 fails to explicitly disclose further comprising:
providing an electron beam propagating toward the plurality of detection regions to emit a luminescent signal from one of the plurality of detection regions; and
merging a plurality of detection regions in the substrate body through the plurality of holes,
wherein a top surface of each one of the plurality of detection regions is coplanar;
determining an overlay error of the plurality of holes by comparing a practical position of one of the plurality of holes detected by the luminescent signal with a theoretical position of one of the plurality of holes; and
directly disposing each of a plurality of filling pillars on each of the detection regions and filling up each of the holes when the overlay error of the plurality of holes is within an acceptable range, wherein a top surface of each of the plurality of filling pillars is completely coplanar with a top surface of the overlapping layer.
However, ’54 discloses (Fig. 9)
providing [S110] an electron beam propagating toward the plurality of detection regions to emit a luminescent signal from one of the plurality of detection regions; and
determining [S120] an overlay error of the plurality of holes by comparing a practical position of one of the plurality of holes detected by the luminescent signal with a theoretical position of one of the plurality of holes.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant Application to use overlay metrology to align detector regions as taught in ’54 because the method is a highly precise alignment tool to manufacture the device, and is most commonly used for alignment purposes.
’10 in view of ’54 fails to explicitly disclose
merging a plurality of detection regions in the substrate body through the plurality of holes,
wherein a top surface of each one of the plurality of detection regions is coplanar;
directly disposing each of a plurality of filling pillars on each of the detection regions and filling up each of the holes when the overlay error of the plurality of holes is within an acceptable range, wherein a top surface of each of the plurality of filling pillars is completely coplanar with a top surface of the overlapping layer.
However, ’75 discloses (Fig 19E) further comprising (Fig. 19E)
merging a plurality of detection regions (p-InGaAs) in the substrate body (p-Si) through the plurality of holes (I-InGaAs), wherein a top surface of each one of the plurality of detection regions is coplanar;
directly disposing each of the plurality of filling pillars (I-InGaAs pillars in Fig. 19E) on each of the detection regions (p-InGaAs) when the overlay error of the plurality of holes is within an acceptable range (this is a common compensation process, so the limitation is obvious), wherein a top surface of each of the plurality of filling pillars (I-InGaAs pillars in Fig. 19E) is completely coplanar with a top surface of the overlapping layer [1944].
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the structure of the detector device of ’10 with the teachings of conventional pillar detector of ‘75 because ’75 teaches (par. [0012]) that these microstructures increase absorption and optimizes detection.
Regarding claim 11, ’10 in view of ’54 in view of ’75 discloses everything as applied above. ’10 further discloses (Figs 1-6) wherein disposing the plurality of detection regions [110] on the substrate body through the plurality of holes comprises disposing a detection material [110] comprising the luminescent material (metallic nanoparticles are luminescent, abstract, par. [0024]-[0026])on the exposed portion of the substrate body [102].
Regarding claim 14, ’10 in view of ’54 in view of ’75 discloses everything as applied above. ’54 further discloses (Figs 1-2, 9) further comprising:
providing the electron beam [PEB] propagating toward the overlapping layer while providing an electron beam propagating toward the plurality of detection regions; and
determining a surface image of the overlapping layer by detecting secondary electrons reflected by the overlapping layer (par. [0038], [S120] in Fig. 9).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Bajaj et. al., U.S. Pat. Pub. 2022/0392810, hereafter ’10, in view of Kim et. al., US. Pat. Pub. 2015/0115154, hereafter ’54,
in view of Wang et. al., U.S. Pat. Pub. 2022/0246775, hereafter ’75, and further in view of Examiner’s Official Notice, hereafter ON.
Regarding claim 12, ’10 in view of ’54 in view of ’75 discloses everything as applied above. ’10 in view of ’54 fails to explicitly disclose wherein disposing the plurality of detection regions in the substrate body through the plurality of holes comprises doping the luminescent material in the substrate body by an ion-implanting method.
However, the Examiner takes an Official notice that ion implantation is widely used in the Semiconductor art to dope a luminescent material.
It would have been obvious to one having ordinary skill in the art at the time of effective filing date of the instant application to dope a luminescent material by ion implantation in the substrate body to further increase image contrast and improve resolution of high aspect trenches as taught in ’10 (par. [0002]-[0003]).
Regarding claim 13, ’10 in view of 12 in view of ’75 in view of ON discloses everything as applied above. ’10 further discloses wherein the substrate body includes a first metal material (par. [0017]), and the luminescent material is a second metal material (par. [0038], [10025] metal nanoparticles are fluorescent).
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 7 and 10-14, have been considered but are moot because the new ground of rejection does not rely some of the references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VICTOR V BARZYKIN/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights