DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on February 2nd, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Election/Restrictions
Applicant's election without traverse of Group I and Species A directed to Fig. 1B (claims 1-16 and 21-24) in the reply filed on February 2nd, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites “a first pair of spacers disposed on opposite sidewalls of the first S/D region” in line 6 and “wherein the first pair of spacers are disposed on opposite sidewalls of the second contact structure” in lines 11-12. However, according to Applicants’ specification, a pair of S/D spacers 104 disposed on opposite sidewalls of BS contact structure 122B and below opposite sidewalls of S/D region 102A2 in final structure of the device, but not on opposite sidewalls of S/D region 102A2 (see Figs. 1A-1C and [0022-0024]). During manufacturing process, S/D spacers 104 initially formed on opposite sidewalls of S/D region 102A2 in Fig. 10B, but later these opposite sidewalls of S/D spacer 104 are removed to form opening 1222 for forming BS contact structure 122B in Fig. 13A-13B. Therefore, the above limitations of claim 1 conflicts with the applicants’ specification and unclear to the examiner.
Claims 2-10 are rejected for depending on claim 1 and having the above issue incorporated into the claim.
Claim 11 recites “first and second spacers disposed on opposite sidewalls of the epitaxial region” in line 6 and “a contact structure disposed on the epitaxial region and between the first and second spacer” in line 7. However, according to Applicants’ specification, a pair of S/D spacers 104 disposed below opposite sidewalls of S/D region 102A2 but not on opposite sidewalls of S/D region 102A2, and BS contact structure 122B disposed on the S/D region 102A1 and between the pair of S/D spacers 104 in final structure of the device, (see Figs. 1A-1C and [0022-0024]). Therefore, the above limitations of claim 11 conflicts with the applicants’ specification and unclear to the examiner.
Claims 12-16 are rejected for depending on claim 11 and having the above issue incorporated into the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-6, 11-12 and 21-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Thomson et al. (Pub. No.: US 2023/0087444 A1), hereinafter as Thomson.
Regarding claim 1, Thomson discloses a semiconductor device in Fig. 1C, comprising: first and second source/drain (S/D) regions (source/drain region 107a as first S/D and source/drain region 103a as second S/D) (see [0038] and [0049]); a stack of nanostructured semiconductor layers (the middle stack of unreleased nanoribbons/nanowires 101a) disposed adjacent to the first S/D region (see [0037]); a
gate structure (middle gate/dielectric structure 108) at least partially surrounding each of the nanostructured semiconductor layers (see [0037-0038] and [0040]); a first pair of spacers (two top portions of one spacer 102 as illustrated in annotated Fig. 1C below)
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disposed on opposite sidewalls of the first S/D region (opposite sidewalls of Source/drain region 107a) (see Annotated Fig. 1C above and [0037] and [0040]); a second pair of spacers (two top portions of another spacer 102 as illustrated in annotated Fig. 1C above) disposed on opposite sidewalls of the second S/D region (opposite sidewalls of source/drain region 103a) (see Annotated Fig. 1C above and [0037] and [0040]); a third pair of spacers (two lower portions of one spacer 102 as illustrated in annotated Fig. 1C above) disposed on opposite sidewalls of the gate structure (opposite sidewalls of the middle gate/dielectric structure 108) (see [0037]); a first contact structure (lower contact 109b as illustrated in annotated Fig. 1C above) disposed on a first surface of the first S/D region (bottom surface of source/drain region 107a) (see [0038], [0046], and [0049]); and a second contact structure (upper contact 109b as illustrated in annotated Fig. 1C above) disposed on a second surface of the first S/D region (top surface of source/drain region 107a), wherein the first and second surfaces are opposite to each other (see Annotated Fig. 1C above and [0038], [00446], [0049]), and wherein the first pair of spacers are disposed on opposite sidewalls of the second contact structure (the two top portions of one spacer 102 on opposite sidewalls of the upper contact 109b as illustrated in annotated Fig. 1C above).
Regarding claim 2, Thomson discloses the semiconductor device of claim 1, further comprising a dielectric layer (dielectric 105) disposed on the second S/D region (source/drain region 103a), wherein the second pair of spacers are disposed on opposite sidewalls of the dielectric layer (see Annotated Fig. 1C above).
Regarding claim 4, Thomson discloses the semiconductor device of claim 1, further comprising a dielectric layer (another portion of right spacer 102 in annotated Fig. 1C) disposed on the opposite sidewalls of the first S/D region and on sidewalls of the first pair of spacers (indirectly disposed on sidewalls of the illustrated 1st pair of spacer) (see annotated Fig. 1C above).
Regarding claim 5, Thomson discloses the semiconductor device of claim 1, further comprising a dielectric layer (another middle portions of spacer 103 between contacts 113 and 109b below illustrated 3rd pair of spacers) disposed between the first and second S/D regions, wherein the first and second pairs of spacers are disposed on the dielectric layer (see annotated Fig. 1C above).
Regarding claim 6, Thomson discloses the semiconductor device of claim 1, wherein the second contact structure comprises a contact plug (contact 109b comprising a contact metal) and a barrier layer (conductive liner/barrier) disposed on the contact plug, and wherein the barrier layer is in contact with the first pair of spacers (see annotated Fig. 1 C above and [0046]).
Regarding claim 11, Thomson discloses a semiconductor device in Fig. 1C, comprising: first and second nanostructured channel regions (right stack of
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nanoribbons/nanowires 101a and middle stack of nanoribbons/nanowires 101a) (see annotated Fig. 1C above and [0037]); first and second gate structures (the right gate/dielectric structure 108 and the middle gate/dielectric structure 108) at least partially surrounding the first and second nanostructured channel regions, respectively (see annotated Fig. 1C above and [0037]); an epitaxial region (source/drain region107a) disposed between the first and second nanostructured channel regions (see annotated Fig. 1C above and [0038]); first and second spacers (two upper portions of spacer 102 as illustrated in Fig. 1C above) disposed on opposite sidewalls of the epitaxial region (sidewalls of source/drain region 107a) (see [0037]); and a contact structure (upper contact 109b) disposed on the epitaxial region and between the first and second spacers (see annotated Fig. 1C above and [0038], [0049]).
Regarding claim 12, Thomson discloses the semiconductor device of claim 11, further comprising a dielectric layer (another portion of right spacer 102 in annotated Fig. 1C) disposed on the opposite sidewalls of the epitaxial region and on sidewalls of the first and second spacers (indirectly disposed on sidewalls of the illustrated first and second spacer) (see annotated Fig. 1C above).
Regarding claim 21, Thomson discloses a semiconductor device in Fig. 1C,
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comprising: a gate structure (middle gate/dielectric structure 108) (see annotated Fig. 1C above and [0037]); first and second source/drain regions (source/drain region 107a as first S/D and source/drain region 103a as second S/D) disposed on either side of the gate structure (see [0038] and [0049]); a conductive structure (upper contact 109b) disposed on a back-side surface of the first source/drain region (top surface of source/drain region 107a being back-side surface respect to the bottom view of device in Fig. 1C and [0038], [0046]); a dielectric structure (dielectric 105) disposed on a back-side surface of the second source/drain region (top surface of source/drain region 103a being back-side surface respect to the bottom view of device in Fig. 1C and [0049]); a first spacer (one upper portion of spacer 102 as illustrated in annotated Fig. 1C above) disposed on a sidewall of the conductive structure (sidewall of upper contact 109b) (see [0037]); and a second spacer (another upper portion of spacer 102 as illustrated in annotated Fig. 1C above) disposed on a sidewall of the dielectric structure (sidewall of dielectric 105) (see [0037] and [0049]).
Regarding claim 22, Thomson discloses the semiconductor device of claim 21, further comprising a dielectric layer (another upper portion of spacer 102 adjacent to gate/dielectric structure 108) disposed between the first and second spacers (see annotated Fig. 1C above).
Regarding claim 23, Thomson discloses the semiconductor device of claim 21, further comprising an etch stop layer (middle portions of spacer 102) disposed along sidewalls of the first and second source/drain regions facing each other and along sidewalls of the first and second spacers facing each other (see annotated Fig. 1C above).
Regarding claim 24, Thomson discloses the semiconductor device of claim 21, further comprising a dielectric (dielectric 104) disposed on a back-side surface of the gate structure (see [0037] and [0049]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818