Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--Method Of Manufacturing A Gate-All-Around Transistor Using Support Cantilevers On Opposing Ends Of A Multilayered Stack--
Claim Objections
Claims 1 and 5 are objected to because of the following informalities:
Regarding Claim 1, “forming on a multilayered stack” should read --forming a multilayered stack--
Regarding Claim 5,
“exposing opposing side surfaces of the patterned multilayered stack” should read --exposing opposing sidewalls of the patterned multilayered stack--
“etching the sacrificial layers to expose side surfaces each channel layer” should read --etching the sacrificial layers to expose side surfaces of each channel layer--
“while ends of the channel layer are” should read --while ends of the channel layers are--
Appropriate correction is required.
Claim Rejections - 35 USC § 112(d)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 2 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding Claim 2, the limitation “the forming a patterned multilayered stack comprises forming a plurality of alternatingly stacked channel layers” does not further narrow the method of Claim 1, which already claims “a patterned multilayered stack comprising sacrificial layers alternatingly stacked with channel layers”. Claim 1 already establishes a plurality of stacked channel layers (in that the plural “layers” is used) and that the channel layers are alternatingly stacked (in that they are alternatingly stacked with the sacrificial layers).
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wan et al. (U.S. Pub. 2021/0135016), hereinafter Wan.
Regarding Claim 1, Wan teaches a method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]), comprising:
-forming a patterned multilayered stack (e.g. (M1); Fig. 3A, Paragraph [0024]) comprising sacrificial layers ((11); Fig. 3A, Paragraph [0030]) alternatingly stacked with channel layers ((12); Fig. 3A, Paragraph [0030]) on a substrate ((10), specifically a bulk silicon layer of (10); Fig. 3A, Paragraph [0029]), the patterned multilayered stack (M1) having opposing sidewalls (the right and left sides of (M1) in the Y-Z plane, as in Fig. 3B) and opposing ends (the right and left sides of (M1) in the X-Z plane, as in Fig. 3A);
-forming cantilever supports ((14) formed in trenches (19) between adjacent stacks; Fig. 5A, Paragraph [0042]) on the substrate (10), each cantilever support (14) being in contact with a respective opposing end of the patterned multilayered stack (right and left sides of (M1) in X-Z);
-forming a gate-all-around (GAA) structure (comprising gate dielectric (21) and gate electrode (GE); Figs. 8A-10, Paragraphs [0047] and [0050]) around each channel layer (21) while the opposing ends of the multilayered stack are supported by the cantilever supports (14);
-removing the cantilever supports from the opposing ends of the patterned multilayered stack to expose end portions of each channel layer; and
-forming source-drain (S-D) regions on the exposed end portions of each respective channel layer (‘source/drain features’ formed on the sides of (12); Paragraph [0055]).
Regarding the limitation:
-removing the cantilever supports from the opposing ends of the patterned multilayered stack to expose end portions of each channel layer;
Wan teaches that after the structures of Figs. 9A-10 are formed, subsequent processes are performed to complete a FET structure, including the forming of source-drain regions (Paragraph [0055]). Since the cantilever supports (14) are taught to be made of silicon nitride (Paragraph [0030]), which is insulating, and source-drain regions must be made of conductive materials in the space where the cantilever supports are present ((14), i.e. on the ends; Fig. 9A) in order to have a functional device, as by the structural nature of being GAA, Wan necessarily teaches the limitation.
Regarding Claim 3, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 1, wherein:
-the forming a patterned multilayered stack (M1) comprises epitaxially growing SiGe sacrificial layers and Si channel layers (‘the channel layers (12) are made of silicon (Si) and the sacrificial layers (11) are made of silicon germanium (SiGe)’; Paragraph [0035]) on the substrate (10).
Regarding Claim 4, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 1, wherein:
-the forming a patterned multilayered stack (M1) further comprises forming a dummy isolation layer on the substrate (‘a silicon-germanium layer formed on a bulk silicon layer’; Paragraph [0029]), the sacrificial layers (11) and channel layers (12) being alternatingly stacked on the on the dummy isolation layer (SiGe layer of (10)).
Regarding Claim 5, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 1, wherein:
the forming a GAA structure ((21) and (GE)) comprises:
-exposing opposing sidewalls of the patterned multilayered stack (e.g. via removing the insulating layer (16) from the sidewalls of (M1); Fig. 5B, Paragraph [0041]);
-selectively etching the sacrificial layers (11) to expose side surfaces of each channel (12) layer (Figs. 6A and 6B, Paragraph [0043]), while ends of the channel layers (e.g. labelled as (12-1E), (12-2E), etc. on Fig. 5A; Paragraph [0042]) are supported and covered by the cantilever supports (14); and
-forming the GAA structure ((21) and (GE)) on the exposed side surfaces of each channel layer (12) (See Figs. 8A-10).
Regarding Claim 6, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 5, wherein:
the forming a GAA structure ((21) and (GE)) comprises:
-depositing a gate dielectric (21) on the exposed side surfaces of each channel layer (12) (Figs. 8A and 8B); and depositing a gate conductor (GE) on the gate dielectric (21) (Figs. 9A and 9B).
Regarding Claim 7, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 6, wherein:
the depositing a gate dielectric (21) comprises:
-depositing a high-k layer (‘gate dielectric layer (21) includes one or more high-k dielectric materials’; Paragraph [0047]) on the exposed side surfaces of each channel layer (12).
Regarding Claim 8, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 6, wherein:
the depositing a gate conductor comprises:
-depositing a work function metal ((GE) includes a ‘work function tuning metal layer’ (26); Fig. 10, Paragraph [0051]) on the gate dielectric (21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 10, 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Lee et al. (U.S. Pub. 2020/0373411), hereinafter Lee.
Regarding Claim 9, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 1 upon which it depends, but does not teach it:
-further comprising forming inner spacers to isolate each GAA structure from respective S-D regions.
Lee teaches a method of fabricating a gate-all-around transistor wherein:
-forming inner spacers ((710); Fig. 7, Paragraph [0041]) to isolate each GAA structure (‘gate layers’ (620); Fig. 7, Paragraph [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the method of Wan such that the method further comprises forming inner spacers to isolate each GAA structure from respective S-D regions (“from respective S-D regions” is necessarily true by the incorporation). Futhermore, the incorporation would be done such that forming inner spacers (Lee, (710)) comprises selectively etching an end portion of each GAA (Lee, gate layers (120) into (620); Figs. 5 and 6, Paragraph [0029]) to form an etch indent (Lee, ‘opening’ (622); Fig. 5, Paragraph [0040]); and filling the etch indent with dielectric material (Lee, ‘dielectric’ (710); Fig. 7, Paragraph [0041]). This would be due to the fact that doing so would produce the predictable result of preventing electrical shorting between the gates and the source-drain regions.
Regarding Claim 10, Wan as modified by Lee teaches the method of fabricating a semiconductor device (Wan, Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 9, wherein:
forming inner spacers (Lee, (710)) comprises:
-selectively etching an end portion of each GAA (Lee, (120)) to form an etch indent (Lee, (622)); and filling the etch indent with dielectric material (Lee, ‘dielectric’ (710)). (See the incorporation of the teachings of Lee into Wan in Claim 9 above, also Lee Figs. 5-7 and Paragraphs [0040] and [0041]).
Regarding Claim 14, Wan teaches a method of fabricating a gate-all-around (GAA) transistor device (Figs. 2A-10, Paragraphs [0026] and [0027]), comprising:
-forming a nanosheet stack (e.g. (M1) ‘nanosheet stacks’; Fig. 3A, Paragraph [0024]) of alternating SiGe ((11) are made of silicon germanium (SiGe); Fig. 3A, Paragraphs [0030] and [0035]) and Si ((12) are made of silicon (Si); Fig. 3A, Paragraphs [0030] and [0035]) nanosheets on a substrate ((10), specifically a bulk silicon layer of (10); Fig. 3A, Paragraph [0029]), wherein the nanosheet stack (M1) has opposing ends (the right and left sides of (M1) in the X-Z plane, as in Fig. 3A) contacting cantilever supports ((14) formed in trenches (19) between adjacent stacks; Fig. 5A, Paragraph [0042]);
-forming a gate structure (comprising gate dielectric (21) and gate electrode (GE); Figs. 8A-10, Paragraphs [0047] and [0050]) all around each Si nanosheet (12) while ends of each Si nanosheet (e.g. labelled as (12-1E), (12-2E), etc. on Fig. 5A; Paragraph [0042]) are supported by the cantilever supports (14);
-forming source-drain (S-D) regions on the ends of each Si nanosheet (‘source/drain features’ formed on the sides of (12); Paragraph [0055]).
Wan does not explicitly teach
-replacing end portions of the gate structure with a dielectric material to form inner spacers for the GAA transistor;
Lee teaches a method of fabricating a gate-all-around transistor wherein:
- replacing end portions of the gate structure (Lee, gate layers (120) into (620) with end portions (622); Figs. 5 and 6, Paragraphs [0029] and [0040]) with a dielectric material to form inner spacer ((710); Fig. 7, Paragraph [0041]) for the GAA transistor (as part of the stack e.g. (140a), Paragraph [0029])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the method of Wan such that the method further comprises replacing end portions of the gate structure with a dielectric material to form inner spacers for the GAA transistor. By consequence of the incorporation, the method necessarily includes the limitation that each S-D region is isolated from the gate structure by a respective inner space. This would be due to the fact that doing so would produce the predictable result of preventing electrical shorting between the gates and the source-drain regions.
Regarding Claim 15, Wan as modified by Lee teaches the method of fabricating a gate-all-around (GAA) transistor (Wan, Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 14, wherein:
the forming a gate structure (Wan, (21) and (GE)) comprises:
etching the SiGe nanosheets (Wan, (11), Figs. 6A and 6B, Paragraph [0043]) to release the Si nanosheets (Wan, (12)) while the cantilever supports (Wan, (14)) support opposing ends of each Si nanosheet (Wan, See paragraph [0043]).
Regarding Claim 16, Wan as modified by Lee teaches the method of fabricating a gate-all-around (GAA) transistor (Wan, Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 15, wherein:
the forming a gate structure (Wan, (21) and (GE)) further comprises:
-depositing a gate dielectric layer (Wan, (21); Figs. 8A and 8B) around the released Si nanosheets (Wan, (12)) while the cantilever supports (Wan, (14)) support opposing ends of each Si nanosheet (Wan, (12)).
Regarding Claim 17, Wan as modified by Lee teaches the method of fabricating a gate-all-around (GAA) transistor (Wan, Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 16, wherein:
the forming a gate structure (Wan, (21) and (GE)) further comprises:
-depositing a gate conductor (Wan, (GE); Figs. 9A and 9B) around the gate dielectric layer (Wan, (21)) while the cantilever supports (Wan, (14)) support opposing ends of each Si nanosheet (Wan, (12)).
Regarding Claim 18, Wan as modified by Lee teaches the method of fabricating a gate-all-around (GAA) transistor (Wan, Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 16, wherein:
the replacing end portions of the gate structure (Lee, gate layers (120) into (620) and dielectric spacer (710)) comprises:
-removing the cantilever supports (Wan, (14)) to expose ends of each Si nanosheet (Wan, (12), specifically (12-1E), (12-2E), etc.) and ends of a respective gate structure (Wan, (21) and (GE)) formed on the Si nanosheet (Wan, (12));
(As previously shown in Claim 1, Wan teaches that after the structures of Figs. 9A-10 are formed, subsequent processes are performed to complete a FET structure, including the forming of source-drain regions (Paragraph [0055]). Since the cantilever supports (14) are taught to be made of silicon nitride (Paragraph [0030]), which is insulating, and source-drain regions must be made of conductive materials in the space where the cantilever supports are present ((14), i.e. on the ends; Fig. 9A) in order to have a functional device, as by the structural nature of being GAA, Wan necessarily teaches the cantilever supports are removed prior to the deposition of the source-drain regions. Since the method of Lee is incorporated, it is understood that the replacing of the end portions of the gate structure is done following the removal of the cantilever supports, as Lee shows as there are no intervening structures present. And thus, in order for Lee’s teachings to be incorporated, the limitation must necessarily be true.)
-selectively etching an indent (Lee, ‘opening’ (622); Fig. 5, Paragraph [0040]) at each end of the gate structure (Lee, gate layers (120) into (620); Figs. 5 and 6, Paragraph [0029]); and depositing dielectric material in each indent to form the inner spacers (Lee, ‘dielectric’ (710); Fig. 7, Paragraph [0041]) for the GAA transistor (Wan as modified by Lee, (M1)).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wan in view of Cheng et al. (U.S. Pub. 2016/0111494), hereinafter Cheng.
Regarding Claim 11, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 1, wherein the method includes:
-removing the cantilever supports (14) such that it exposes ends of each channel layer (12) and ends of the GAA structure ((21) and (GE)) formed around the respective channel layer. (See Claim 1’s explanation)
But does not specifically disclose:
-etching the cantilever supports and a portion of the opposing ends of the patterned multilayered stack
Cheng teaches a method of fabricating a semiconductor device (GAA nanowire device (200) and method (100); Figs. 1 and 2f, Paragraphs [0010] and [0016]) which incorporates the use of nanosheet stacks (each set of (225); Figs. 2a and 2f, Paragraph [0016]) and support cantilevers ((240); Fig. 2d, Paragraph [0016]) wherein removing the cantilever supports comprises:
-etching the cantilever supports ((240); Fig. 2d, Paragraph [0024]) and a portion of the opposing ends of the patterned multilayered stack (in this case, specifically a portion of the gate (250); Fig. 2d, Paragraph [0025]) (Process shown in Fig. 2e, Paragraph [0027])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Cheng into the device of Wan such that removing the cantilever supports comprises etching the cantilever supports and a portion of the opposing ends of the patterned multilayered stack. This would be due to the fact that doing so would have the predictable result of ensuring removal of the no longer needed structures and open the area for source and drain region deposition.
Regarding Claim 12, Wan teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 1, wherein the method includes:
-forming source-drain (S-D) regions on the exposed end portions of each respective channel layer (‘source/drain features’ formed on the sides of (12); Paragraph [0055]).
But Wan does not explicitly teach:
-wherein the forming S-D regions comprises epitaxially growing doped semiconductor material.
Cheng teaches a method of fabricating a semiconductor device (GAA nanowire device (200) and method (100); Figs. 1 and 2f, Paragraphs [0010] and [0016]) which incorporates the use of nanosheet stacks (each set of (225); Figs. 2a and 2f, Paragraph [0016]) and support cantilevers ((240); Fig. 2d, Paragraph [0016]) wherein:
-forming the S-D regions ((270); Fig. 2f, Paragraph [0016]) comprises epitaxially growing doped semiconductor material (Paragraph [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Cheng into the method of Wan such that the process of forming S-D regions comprises epitaxially growing doped semiconductor material. Futhermore, the incorporation would be done such that it comprises forming one of n-doped and p-doped S-D regions (Cheng, e.g. silicon doped with arsenic (n-doped) or silicon doped with boron (p-doped); Paragraph [0028]). This would be due to the fact that doing so would provide for more effective source/drain regions (Cheng, Paragraph [0009]).
Regarding Claim 13, Wan as modified by Cheng teaches the method of fabricating a semiconductor device (Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 12, wherein:
the epitaxially growing doped semiconductor material (Cheng, (270)) comprises
-forming one of n-doped and p-doped S-D regions. (See the incorporation of the teachings of Cheng into Wan in Claim 12 above, also Cheng Paragraph [0028]).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wan and Lee in view of Cheng.
Regarding Claim 19, Wan as modified by Lee teaches the method of fabricating a gate-all-around (GAA) transistor (Wan, Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 18, wherein the method comprises:
-forming S-D regions on the ends of each Si nanosheet (Wan, nanosheet (12), Paragraph [0055])
However, neither Wan nor Lee explicitly disclose forming S-D regions comprising:
-epitaxially growing doped Si on the ends of each Si nanosheet.
Cheng teaches a method of fabricating a semiconductor device (GAA nanowire device (200) and method (100); Figs. 1 and 2f, Paragraphs [0010] and [0016]) which incorporates the use of nanosheet stacks (each set of (225); Figs. 2a and 2f, Paragraph [0016]) and support cantilevers ((240); Fig. 2d, Paragraph [0016]) wherein:
-forming the S-D regions ((270); Fig. 2f, Paragraph [0016]) comprises epitaxially growing doped Si (Paragraph [0028]) on the ends of each Si nanosheet ((220); Fig. 2f, Paragraph [0021])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Cheng into the method of Wan as modified by Lee such that the process of forming S-D regions comprises epitaxially growing doped Si on the ends of each Si nanosheet. Futhermore, the incorporation would be done such that it comprises epitaxially growing n-doped Si or p-doped Si on the ends of each Si nanosheet (Cheng, e.g. silicon doped with arsenic (n-doped) or silicon doped with boron (p-doped); Paragraph [0028]). This would be due to the fact that doing so would provide for more effective source/drain regions (Cheng, Paragraph [0009]).
Regarding Claim 20, Wan as modified by Lee and Cheng teaches the method of fabricating a gate-all-around (GAA) transistor (Wan, Figs. 2A-10, Paragraphs [0026] and [0027]) of Claim 19, wherein:
-The forming S-D regions (Wan as modified by Cheng, see Chen (160) Paragraph [0013]) comprises:
- epitaxially growing n-doped Si or p-doped Si on the ends of each Si nanosheet. (See the incorporation of the teachings of Cheng into Wan as modified by Lee in Claim 19 above, also Cheng Paragraph [0028]).
Conclusion
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/D.M./ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812