DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II in the reply filed on 02/11/2026 is acknowledged.
Claims 9-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II and Group I, Species I and III-XI, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/11/2026.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6-7, and 10 of U.S. Patent No. 12,543,267 in view of Hirai et al. [U.S. Pub. No. 2019/0244743].
Regarding Claim 1, U.S. Patent No. 12,543,267 in claims 1, 6-7, and 10 shows an inductor inlay, comprising: a magnetic layer stack; and an electrically conductive structure embedded in the magnetic layer stack, wherein the electrically conductive structure is configured as an inductor element that comprises a coil-like shape.
U.S. Patent No. 12,543,267 does not explicitly show a plurality of interconnected magnetic layers.
Hirai et al. shows an inductor inlay (Figs. 1-2), comprising: a magnetic layer stack (10), comprising a plurality of interconnected magnetic layers (11, 12); and an electrically conductive structure (21) embedded in the magnetic layer stack (see Figs. 1-2), wherein the electrically conductive structure (21) is configured as an inductor element (Paragraph [0067]) that comprises a coil-like shape (see Figs. 1-2, Paragraph [0067]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a plurality of interconnected magnetic layers as taught by Hirai et al. for the inductor as disclosed by U.S. Patent No. 12,543,267 to obtain a closed magnetic path to achieve improvement of inductance with reduced magnetic flux leakage and eddy current loss (Paragraph [0128]).
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 12,543,267 in view of Yoshioka et al. [U.S. Pub. No. 2018/0075965] (hereinafter as “Yoshioka ‘965”).
Regarding Claim 14, U.S. Patent No. 12,543,267 in claim 10 shows a component carrier, comprising: a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure; and an inductor inlay, wherein the inductor inlay is embedded in the stack, wherein the inductor inlay includes: a magnetic layer stack; and an electrically conductive structure embedded in the magnetic layer stack, wherein the electrically conductive structure is configured as an inductor element that comprises a coil-like shape.
U.S. Patent No. 12,543,267 does not explicitly show a plurality of interconnected magnetic layers.
Yoshioka ‘965 shows a component carrier (Fig. 10 with teachings from Fig. 1), comprising: a stack (5) comprising at least one electrically conductive layer structure (6a, 6b, 6e) and at least one electrically insulating layer structure (8); and an inductor inlay (1), wherein the inductor inlay is embedded in the stack (see Fig. 10), wherein the inductor inlay (1) includes: a magnetic layer stack (10), comprising a plurality of interconnected magnetic layers (11, 12); and an electrically conductive structure (21) embedded in the magnetic layer stack (see Fig. 10), wherein the electrically conductive structure (21) is configured as an inductor element (element 21 is a spiral wire that functions as an inductor element) that comprises a coil-like shape (Paragraph [0131], see Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a plurality of interconnected magnetic layers as taught by Yoshioka ‘965 for the inductor as disclosed by U.S. Patent No. 12,543,267 to obtain a closed magnetic path to achieve improvement of inductance (Paragraph [0142]).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15, line 5, recites “at least one electrically conductive structure of the stack” is indefinite and unclear. According to claim 14, line 3, the stack comprises “at least one electrically conductive layer structure”. Therefore, as best understood, “at least one electrically conductive structure of the stack” in claim 15, line 5, should be “at least one electrically conductive layer structure”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirai et al. [U.S. Pub. No. 2019/0244743].
Regarding Claim 1, Hirai et al. shows an inductor inlay (Figs. 1-2), comprising:
a magnetic layer stack (10), comprising a plurality of interconnected magnetic layers (11, 12); and
an electrically conductive structure (21) embedded in the magnetic layer stack (see Figs. 1-2), wherein the electrically conductive structure (21) is configured as an inductor element (Paragraph [0067]) that comprises a coil-like shape (see Figs. 1-2, Paragraph [0067]).
Regarding Claim 2, Hirai et al. shows the magnetic layer stack comprises exactly two magnetic layers (11, 12, see Fig. 3M and Fig. 3R, upper and lower elements 67) or exactly three magnetic layers.
Regarding Claim 3, Hirai et al. shows the inductor element is embedded horizontally in the magnetic layer stack (see Figs. 1-2), or
wherein the inductor element is embedded vertically in the magnetic layer stack.
Regarding Claim 4, Hirai et al. shows at least one of the magnetic layers (11) is partially (Paragraphs [0115]-[0116]) or entirely dielectric; and/or
wherein at least one of the magnetic layers comprises a magnetic matrix; and/or
wherein the magnetic matrix comprises a dielectric material, in which magnetic particles are embedded,
wherein the magnetic particles comprise at least one of the group consisting of a ferrite, a 3d material, and a 4f material; and/or
wherein the magnetic matrix continuously fills a volume around the inductor element; and/or
wherein the magnetic matrix comprises a rigid solid and/or a paste; and/or
wherein the magnetic matrix is electrically insulating; and/or
wherein a relative magnetic permeability pr of the magnetic matrix is in a range from 1.1 to 500; and/or
wherein the magnetic matrix comprises at least one material of the group consisting of a ferromagnetic material, a ferrimagnetic material, a permanent magnetic material, a soft magnetic material, a ferrite, a metal oxide, a dielectric matrix, a prepreg, and an alloy or alloyed silicon.
Regarding Claim 5, Hirai et al. shows the inductor element is meander-shaped and/or spiral-shaped (see Figs. 1-2, Paragraph [0067]).
Regarding Claim 6, Hirai et al. shows the inductor element comprises at least two terminal sections (31, 32) exposed with respect to the plurality of interconnected magnetic layers of the magnetic layer stack (see Figs. 1-2, Paragraph [0074]).
Regarding Claim 7, Hirai et al. shows the at least two terminal sections (31, 32) have a larger vertical and/or larger horizontal extension than a central section of the inductor element that is located between the at least two terminal sections (see Figs. 1-2, elements 31, 32 have a larger vertical and/or larger horizontal extension than a central section of element 21 that is located between elements 31, 32).
Regarding Claim 8, Hirai et al. shows the inductor inlay further comprises:
at least one electrically conductive via (31 or 32), being a blind via or a through-hole via (see Figs. 1-2), that extends at least partially through the magnetic layer stack (see Figs. 1-2) and that connects the inductor element (21) to an exterior surface of the inductor inlay (upper surface of element 11 which is part of element 10, Paragraph [0074]),
wherein the at least one electrically conductive via (31 or 32) is filled at least partially with electrically conductive material (see Figs. 1-2, Paragraphs [0067], [0071], [0091]), or
wherein the at least one electrically conductive via is a hollow lining which is filled at least partially with an electrically insulating material.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) or 35 U.S.C. 102(a)(2) as being anticipated by Yoshioka et al. [U.S. Pub. No. 2022/0068546].
Regarding Claim 1, Yoshioka et al. shows an inductor inlay (Figs. 1-3), comprising:
a magnetic layer stack (20), comprising a plurality of interconnected magnetic layers (21, 22, 23); and
an electrically conductive structure (30) embedded in the magnetic layer stack (see Figs. 1-3), wherein the electrically conductive structure (30) is configured as an inductor element (Paragraph [0049]) that comprises a coil-like shape (see Figs. 1-3, Paragraph [0051]).
Regarding Claim 2, Yoshioka et al. shows the magnetic layer stack comprises exactly two magnetic layers or exactly three magnetic layers (21, 22, 23).
Regarding Claim 3, Yoshioka et al. shows the inductor element is embedded horizontally in the magnetic layer stack (see Figs. 1-3), or
wherein the inductor element is embedded vertically in the magnetic layer stack.
Regarding Claim 4, Yoshioka et al. shows at least one of the magnetic layers (21) is partially (Paragraph [0048]) or entirely dielectric; and/or
wherein at least one of the magnetic layers comprises a magnetic matrix; and/or
wherein the magnetic matrix comprises a dielectric material, in which magnetic particles are embedded,
wherein the magnetic particles comprise at least one of the group consisting of a ferrite, a 3d material, and a 4f material; and/or
wherein the magnetic matrix continuously fills a volume around the inductor element; and/or
wherein the magnetic matrix comprises a rigid solid and/or a paste; and/or
wherein the magnetic matrix is electrically insulating; and/or
wherein a relative magnetic permeability pr of the magnetic matrix is in a range from 1.1 to 500; and/or
wherein the magnetic matrix comprises at least one material of the group consisting of a ferromagnetic material, a ferrimagnetic material, a permanent magnetic material, a soft magnetic material, a ferrite, a metal oxide, a dielectric matrix, a prepreg, and an alloy or alloyed silicon.
Regarding Claim 5, Yoshioka et al. shows the inductor element is meander-shaped and/or spiral-shaped (see Figs. 1-3, Paragraph [0051]).
Regarding Claim 6, Yoshioka et al. shows the inductor element comprises at least two terminal sections (41, 42) exposed with respect to the plurality of interconnected magnetic layers of the magnetic layer stack (see Figs. 1-3, Paragraph [0070]).
Regarding Claim 7, Yoshioka et al. shows the at least two terminal sections (41, 42) have a larger vertical (TV1, TV2) and/or larger horizontal extension than a central section of the inductor element that is located between the at least two terminal sections (see Figs. 1-3, elements 41, 42 have a larger vertical TV1, TV2 and/or larger horizontal extension than a central section of element 30 such as element TI that is located between elements 41, 42, Paragraphs [0055], [0059], [0061]).
Regarding Claim 8, Yoshioka et al. shows the inductor inlay further comprises:
at least one electrically conductive via (41 or 42), being a blind via or a through-hole via (see Figs. 1-3), that extends at least partially through the magnetic layer stack (see Figs. 1-3) and that connects the inductor element (30) to an exterior surface of the inductor inlay (main surface of element 20, Paragraphs [0070], [0140]),
wherein the at least one electrically conductive via (41 or 42) is filled at least partially with electrically conductive material (see Figs. 1-3, Paragraphs [0058], [0060]), or
wherein the at least one electrically conductive via is a hollow lining which is filled at least partially with an electrically insulating material.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hamada et al. [U.S. Pub. No. 2018/0310408].
Regarding Claim 14, Hamada et al. shows a component carrier (Fig. 2), comprising:
a stack (20A, 20B) comprising at least one electrically conductive layer structure (26, 26a) and at least one electrically insulating layer structure (28); and
an inductor inlay (10), wherein the inductor inlay is embedded in the stack (see Fig. 2),
wherein the inductor inlay (10) includes:
a magnetic layer stack (stack of elements 11a), comprising a plurality of interconnected magnetic layers (elements 11a); and
an electrically conductive structure (12) embedded in the magnetic layer stack (see Fig. 2), wherein the electrically conductive structure (12) is configured as an inductor element (element 12 is a coil that functions as an inductor element) that comprises a coil-like shape (Paragraph [0068]).
Regarding Claim 15, Hamada et al. shows the component carrier is configured as an integrated circuit, or an IC substrate; and/or
wherein at least one electrically conductive structure (26, 26a) of the stack (20A, 20B) is electrically connected to the inductor element (12) of the inductor inlay via terminal sections (elements 16 or 27, see Fig. 2, Paragraphs [0079]-[0080]); and/or
wherein the inductor inlay is embedded in the stack, such that directions of main extension of the inductor inlay are essentially parallel or essentially perpendicular to the directions of main extension of the component carrier.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hamada et al. [U.S. Pub. No. 2017/0098997] (hereinafter as “Hamada ‘997”).
Regarding Claim 14, Hamada ‘997 shows a component carrier (Fig. 9 with teachings from Fig. 7 and Figs. 1A-1B), comprising:
a stack (2) comprising at least one electrically conductive layer structure (81, 82) and at least one electrically insulating layer structure (85); and
an inductor inlay (1B), wherein the inductor inlay is embedded in the stack (see Fig. 9),
wherein the inductor inlay (1B) includes:
a magnetic layer stack (30A), comprising a plurality of interconnected magnetic layers (element 30A is the same as element 30 from Fig. 1 which contains elements 31, 32, 33, 34, Paragraph [0158]); and
an electrically conductive structure (22) embedded in the magnetic layer stack (see Fig. 9 and see Fig. 7), wherein the electrically conductive structure (22) is configured as an inductor element (element 22 is a spiral wire that functions as an inductor element) that comprises a coil-like shape (Paragraph [0186], see Fig. 1A).
Regarding Claim 15, Hamada ‘997 shows the component carrier is configured as an integrated circuit, or an IC substrate; and/or
wherein at least one electrically conductive structure (81, 82) of the stack (2) is electrically connected to the inductor element (22) of the inductor inlay via terminal sections (elements 11, 12, see Fig. 9, Paragraph [0201]); and/or
wherein the inductor inlay is embedded in the stack, such that directions of main extension of the inductor inlay are essentially parallel or essentially perpendicular to the directions of main extension of the component carrier.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshioka et al. [U.S. Pub. No. 2018/0075965] (hereinafter as “Yoshioka ‘965”).
Regarding Claim 14, Yoshioka ‘965 shows a component carrier (Fig. 10 with teachings from Fig. 1), comprising:
a stack (5) comprising at least one electrically conductive layer structure (6a, 6b, 6e) and at least one electrically insulating layer structure (8); and
an inductor inlay (1), wherein the inductor inlay is embedded in the stack (see Fig. 10),
wherein the inductor inlay (1) includes:
a magnetic layer stack (10), comprising a plurality of interconnected magnetic layers (11, 12); and
an electrically conductive structure (21) embedded in the magnetic layer stack (see Fig. 10), wherein the electrically conductive structure (21) is configured as an inductor element (element 21 is a spiral wire that functions as an inductor element) that comprises a coil-like shape (Paragraph [0131], see Fig. 1).
Regarding Claim 15, Yoshioka ‘965 shows the component carrier is configured as an integrated circuit, or an IC substrate; and/or
wherein at least one electrically conductive structure (6a, 6b, 6e) of the stack (5) is electrically connected to the inductor element (21) of the inductor inlay via terminal sections (elements 31, 32 or 41, 42, see Fig. 10, Paragraphs [0240]-[0241]); and/or
wherein the inductor inlay is embedded in the stack, such that directions of main extension of the inductor inlay are essentially parallel or essentially perpendicular to the directions of main extension of the component carrier.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirai et al. in view of Yoshioka et al. [U.S. Pub. No. 2022/0068546].
Regarding Claim 7, Hirai et al. shows the claimed invention as applied above.
In addition, Yoshioka et al. shows the at least two terminal sections (41, 42) have a larger vertical (TV1, TV2) and/or larger horizontal extension than a central section of the inductor element that is located between the at least two terminal sections (see Figs. 1-3, elements 41, 42 have a larger vertical TV1, TV2 and/or larger horizontal extension than a central section of element 30 such as element TI that is located between elements 41, 42, Paragraphs [0055], [0059], [0061]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the at least two terminal sections have a larger vertical and/or larger horizontal extension than a central section of the inductor element that is located between the at least two terminal sections as taught by Yoshioka et al. for the inductor as disclosed by Hirai et al. to achieve improvement of inductance (Paragraphs [0089], [0091], [0153], [0161]).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirai et al. in view of Park et al. [U.S. Pub. No. 2020/0126711].
Regarding Claim 7, Hirai et al. shows the claimed invention as applied above.
In addition, Park et al. shows (Fig. 2) the at least two terminal sections (107, 108) have a larger vertical (T2) and/or larger horizontal extension than a central section of the inductor element that is located between the at least two terminal sections (see Fig. 2, elements 107, 108 have a larger vertical T2 than a central section of element 103 such as less than element T3 that is located between elements 107, 108).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the at least two terminal sections have a larger vertical and/or larger horizontal extension than a central section of the inductor element that is located between the at least two terminal sections as taught by Park et al. for the inductor as disclosed by Hirai et al. to sufficiently secured magnetic grains and improve Ls property (Paragraph [0041]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirai et al. in view of Tsurumi et al. [U.S. Pub. No. 2015/0042440].
Regarding Claim 8, Hirai et al. shows the claimed invention as applied above.
In addition, Tsurumi et al. shows at least one electrically conductive via (23), being a blind via or a through-hole via (see Figs. 4(a)-4(c)), that extends at least partially through the magnetic layer stack (see Figs. 4(a)-4(c)) and that connects the inductor element (22) to an exterior surface of the inductor inlay (lower surface of element 4, Paragraph [0103]),
wherein the at least one electrically conductive via (23) is filled at least partially with electrically conductive material (see Figs. 4(a)-4(c), Paragraphs [0084], [0103]), or
wherein the at least one electrically conductive via is a hollow lining which is filled at least partially with an electrically insulating material.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have at least one electrically conductive via, being a blind via or a through-hole via, that extends at least partially through the magnetic layer stack and that connects the inductor element to an exterior surface of the inductor inlay, wherein the at least one electrically conductive via is filled at least partially with electrically conductive material as taught by Tsurumi et al. for the inductor as disclosed by Hirai et al. to facilitate electrical connection to an external circuit to achieve desirable operating characteristics and inductance values (Paragraph [0016]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshioka et al. in view of Tsurumi et al. [U.S. Pub. No. 2015/0042440].
Regarding Claim 8, Yoshioka et al. shows the claimed invention as applied above.
In addition, Tsurumi et al. shows at least one electrically conductive via (23), being a blind via or a through-hole via (see Figs. 4(a)-4(c)), that extends at least partially through the magnetic layer stack (see Figs. 4(a)-4(c)) and that connects the inductor element (22) to an exterior surface of the inductor inlay (lower surface of element 4, Paragraph [0103]),
wherein the at least one electrically conductive via (23) is filled at least partially with electrically conductive material (see Figs. 4(a)-4(c), Paragraphs [0084], [0103]), or
wherein the at least one electrically conductive via is a hollow lining which is filled at least partially with an electrically insulating material.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have at least one electrically conductive via, being a blind via or a through-hole via, that extends at least partially through the magnetic layer stack and that connects the inductor element to an exterior surface of the inductor inlay, wherein the at least one electrically conductive via is filled at least partially with electrically conductive material as taught by Tsurumi et al. for the inductor as disclosed by Yoshioka et al. to facilitate electrical connection to an external circuit to achieve desirable operating characteristics and inductance values (Paragraph [0016]).
Conclusion
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/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837