Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments in regard to the 35 U.S.C. 112(b) rejection of claim 9, filed in “Arguments/Remarks Made in an Amendment” in response dated 10/06/2025 have been fully considered but they are not persuasive.
Applicant argues that simply having a term of degree does not make the scope of the limitation in the claim ambiguous if one of skill in the art, when reading the term in light of the specification can give the term more context. The problem with this, however, is that the term “sufficiently” is still a term of degree that is not resolved even if reading the section of the specification that applicant pointed to [0054] is directly read into the claims. The parts of the specification that applicant pointed to mention how the substrate is flexible enough to be folded in half/back onto itself. There is nothing to give a reasonable mete and bound to the sufficiently language used.
Examiner will once again point MPEP § 2173.02, subsection II (citing Morton Int ’l, Inc. v. Cardinal Chem. Co., 5 F.3d 1464, 1470, 28 USPQ2d 1190, 1195 (Fed. Cir. 1993)); see also Halliburton Energy Servs., 514 F.3d at 1249, 85 USPQ2d at 1658 (“Otherwise, competitors cannot avoid infringement, defeating the public notice function of patent claims.”). Examiners should bear in mind that “[a]n essential purpose of patent examination is to fashion claims that are precise, clear, correct, and unambiguous. Only in this way can uncertainties of claim scope be removed, as much as possible, during the administrative process.” Zletz, 893 F.2d at 322, 13 USPQ2d at 1322.
Applicant’s arguments of the 35 U.S.C. 102 or 103 rejections with respect to claims 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 21-24, and 26 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 21-24, and 26 recite “a ceramic layer, a first epoxy resin layer coupled to a first side of the ceramic layer, and a second epoxy resin layer coupled to a second side of the ceramic layer opposite the first side.” While there appears to be support for having a ceramic layer, there does not appear to be support filed in the original disclosure that has the ceramic layer has a first and second side where the first side has a first epoxy resin and the second side has a second epoxy resin disposed thereon.
Claim 7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the conductor layer" in line 3. There is insufficient antecedent basis for this limitation in the claim. A second conductor layer has been introduced before this point and as such, either the original conductor layer or the second conductor layer can be referred to as “the conductor layer”. Examiner believes that applicant intended for this limitation was to refer to the second conductor layer and in an effort for compact prosecution, the claim will be treated as if the limitation was referring to “the second conductor layer” for examination of claim 7 in this office action only. Appropriate action is still needed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1, 3-9, 21-22, and 24-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent Application Publication by Esler et al. (US 20220070996 A1; Esler).
Regarding Claim 1, Esler discloses an integrated substrate comprising:
a conductor layer (281);
a heat sink (271) comprising a plurality of fins extending therefrom (Fig. 1, where fins extend from the heatsink 271);
a dielectric layer (291) comprising boron nitride (Para. 29, lines 16-25) chemically bonded to the conductor layer and to the heat sink (Fig. 1, where dielectric layer 291 is bonded to heatsink 271 and conductor layer 281) with an epoxy (Para. 29, lines 16-25);
a semiconductor die (220) coupled over the conductor layer (Fig. 1); and
a spacer (257) coupled between the conductor layer and the semiconductor die (Fig. 1).
Regarding Claim 3, Esler discloses the integrated substrate of claim 1, further comprising a second spacer coupled to the conductor layer (Fig.1, Where there are two semiconductor dies each having their own spacer. The first spacer can be the left spacer 257 and the second spacer can be considered the right spacer 257 in the figure).
Regarding Claim 4, Esler discloses the integrated substrate of claim 3, further comprising a second semiconductor die coupled to the conductor layer and over the second spacer (Fig.1, Where there are two semiconductor dies each having their own spacer. The first semiconductor die can be the left semiconductor die 220 and the second semiconductor die can be considered the right semiconductor die 220 in the figure).
Regarding Claim 5, Esler discloses the integrated substrate of claim 1, further comprising a mold compound (226) coupled to the conductor layer, the heat sink, and the dielectric layer (Fig. 1, The mold compound 226 is at least directly coupled to conductor layer 281 and coupled to dielectric layer 283 and heatsink 271 by being coupled to the conductor layer).
Regarding Claim 6, Esler discloses the integrated substrate of claim 1, further comprising one or more electrical connectors (311) electrically coupled with the conductor layer (Para. 51, and Fig. 2, where electrical connector 311 is connected to conductor layer 381).
Regarding Claim 7, Esler discloses the integrated substrate of claim 1, further comprising a second conductor layer (387), a second heat sink (371), and a second dielectric layer (392) comprising boron nitride (Para. 50) coupled with a semiconductor die coupled (Right semiconductor die in figure 2) with the second (added second, see above 112(b) rejection) conductor layer.
Regarding Claim 8, Esler discloses the integrated substrate of claim 1, wherein the boron nitride of the dielectric layer is a filler in a sheet of epoxy resin (Para. 43, Lines 16-19).
Regarding Claim 9, Esler discloses the integrated substrate of claim 8, and further wherein the dielectric layer is sufficiently flexible to be folded in half (While “Sufficiently” may be a term of degree, it can still be understood that the dielectric layer can at least be folded in half, albeit, maybe only once. Nevertheless, the dielectric layer will still have been folded in half, regardless if there were catastrophic effects. Therefore, the dielectric layer in Esler can at least sill be folded in half).
Regarding Claim 21, Esler discloses an integrated substrate comprising:
a conductor layer (281);
a heat sink (271) comprising a plurality of fins extending therefrom (Fig. 1, where fins extend from the heatsink 271); and
a dielectric layer (291) comprising boron nitride (Para. 29, lines 16-25) chemically bonded to the conductor layer and to the heat sink with an epoxy (Fig. 1, where dielectric layer 291 is bonded to heatsink 271 and conductor layer 281);
wherein the dielectric layer comprises a ceramic layer, a first epoxy resin layer coupled to a first side of the ceramic layer, and a second epoxy resin layer coupled to a second side of the ceramic layer opposite the first side (Para. 43, where there is a coating that can be applied to the first side of dielectric layer 391, that the dielectric layer can be made of ceramic, and that the coatings on either side can be epoxy resin).
Regarding Claim 22, Esler discloses the integrated substrate of claim 21, further comprising a plurality of spacers coupled between the conductor layer and a plurality of semiconductor die (Fig. 2, where there are a plurality of semiconductor dies 320, each of which has a spacer coupled to the die and the conductor layer).
Regarding Claim 24, Esler discloses the integrated substrate of claim 21, wherein a thermal resistance of the integrated substrate is lower than a direct bonded copper substrate comprising silicon nitride.
Regarding Claim 25, Esler discloses an integrated substrate comprising:
a first conductor layer (381);
a first heat sink (371) comprising a first plurality of fins extending therefrom (Fig. 2, where fins extend from the heatsink 371);
a first dielectric layer (391) comprising boron nitride (Para. 29, lines 16-25) chemically bonded to the first conductor layer and to the first heat sink (Fig. 2, where dielectric layer 391 is bonded to heatsink 371 and conductor layer 381) with a first epoxy layer (Para. 29, lines 16-25);
a second conductor layer (387);
a second heat sink (372) comprising a second plurality of fins extending therefrom (Fig. 2, where fins extend from the heatsink 372);
a second dielectric layer (392) comprising boron nitride chemically bonded to second conductor layer and to the second heat sink with a second epoxy layer (Para. 50, Lines 16-20);
wherein a first surface of the first dielectric layer facing the first conductor layer is planar and spans an entire width of the first dielectric layer (Fig 2).
Regarding Claim 26, Esler discloses the integrated substrate of claim 25, wherein the first dielectric layer comprises a ceramic layer, the first epoxy resin layer coupled to a first side of the ceramic layer, and the second epoxy resin layer coupled to a second side of the ceramic layer opposite the first side (Para. 43, where there is a coating that can be applied to the first side of dielectric layer 391, that the dielectric layer can be made of ceramic, and that the coatings on either side can be epoxy resin).
Regarding Claim 27, Esler discloses the integrated substrate of claim 25, further comprising a plurality of spacers (357) coupled between the first conductor layer and a plurality of semiconductor die (Fig. 2, where each die has a spacer 357 coupled between the die and the first conductor layer).
Claim 2 and 29 are rejected under 35 U.S.C. 102(a)(1) as anticipated by United states patent application Publication by Esler and support as to the properties of the materials is given by NPL Qiran Cai et al. High thermal conductivity of high-quality monolayer boron nitride and its thermal expansion.Sci. Adv.5,eaav0129(2019).DOI:10.1126/sciadv.aav0129 and NPL Jiabin, Hu & Wu, Yajing & Li, Cong & Wang, Laili & Wang, Shenghe & Shi, Zhongqi. (2021). Pressure-assisted direct bonding of copper to silicon nitride for high thermal conductivity and strong interfacial bonding strength. Journal of Materials Science. 56. 10.1007/s10853-021-06521-w.
Regarding Claim 2, Esler discloses the integrated substrate of claim 1, and further wherein a thermal resistance of the integrated substrate is lower than a direct bonded copper substrate comprising silicon nitride.
In support of the Examiners position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical process, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1997) and MPEP 2112.02.
In further support for examiners position, Cai explains how Boron Nitride is one of the most thermally conductive (Or least thermally resistive) materials used in semiconductors. “According to optothermal Raman measurements, the suspended 1L BN had a high average κ of 751 W/mK at close to room temperature, and therefore, it was one of the best thermal conductors among semiconductors and electrical insulators”. Meanwhile, Jiabin describes the thermal conductivity of the direct bonding of copper substrate and silicon nitride, “Notably, the sample prepared by Si3N4 plate with 5-μm-thickness SiO2 layer and Cu foil with 5.9-μm-thickness oxide layer (Cu2O) exhibited the optimally comprehensive properties with thermal conductivity of 92 W·m⁻¹·K⁻¹” as found in the abstract and text body.
As shown in the NPL cited above just inherency of the materials used, the thermal resistance of the integrated substrate as disclosed by Esler will be lower than a direct bonded copper substrate comprising silicon nitride.
Regarding Claim 29, Esler discloses the integrated substrate of claim 25, wherein a thermal resistance of the integrated substrate is lower than a direct bonded copper substrate comprising silicon nitride.
In support of the Examiners position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical process, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1997) and MPEP 2112.02.
In further support for examiners position, Cai explains how Boron Nitride is one of the most thermally conductive (Or least thermally resistive) materials used in semiconductors. “According to optothermal Raman measurements, the suspended 1L BN had a high average κ of 751 W/mK at close to room temperature, and therefore, it was one of the best thermal conductors among semiconductors and electrical insulators”. Meanwhile, Jiabin describes the thermal conductivity of the direct bonding of copper substrate and silicon nitride, “Notably, the sample prepared by Si3N4 plate with 5-μm-thickness SiO2 layer and Cu foil with 5.9-μm-thickness oxide layer (Cu2O) exhibited the optimally comprehensive properties with thermal conductivity of 92 W·m⁻¹·K⁻¹” as found in the abstract and text body.
As shown in the NPL cited above just inherency of the materials used, the thermal resistance of the integrated substrate as disclosed by Esler will be lower than a direct bonded copper substrate comprising silicon nitride.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23 and 28 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by Esler over United States Patent Application Publication by Yamamoto et al. (US 20140367702 A1, Yamamoto).
Regarding Claim 23, Esler discloses the integrated substrate of claim 21 but fails to disclose wherein the first heat sink is recessed into a mold compound.
In a similar field of endeavor, Yamamoto discloses an integrated substrate device (1), with a conductor layer (4), a heatsink (2), a dielectric layer (3), and a mold compound (6) in a similar configuration as the instant application. However, the heatsink in Yamamoto sinks into the mold compound as the sidewalls of the heatsink are against the mold compound (Fig. 1).
In view of the disclosure of Yamamoto, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Yamamoto to Esler at the time the instant application was filed to incorporate a larger amount of mold compound, such that the heatsink sinks into the excess mold compound. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that sealing the device, including at least the side of the heatsink, in order to hold the device together has (Para. 33).
Regarding Claim 28, Esler discloses the integrated substrate of claim 25, but fails to disclose wherein the first heat sink is recessed into a mold compound.
In a similar field of endeavor, Yamamoto discloses an integrated substrate device (1), with a conductor layer (4), a heatsink (2), a dielectric layer (3), and a mold compound (6) in a similar configuration as the instant application. However, the heatsink in Yamamoto sinks into the mold compound as the sidewalls of the heatsink are against the mold compound (Fig. 1).
In view of the disclosure of Yamamoto, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Yamamoto to Esler at the time the instant application was filed to incorporate a larger amount of mold compound, such that the heatsink sinks into the excess mold compound. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that sealing the device, including at least the side of the heatsink, in order to hold the device together has (Para. 33).
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 8am-5pm EST.
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/DANIEL J HIBBERT/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899