Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/01/2026 has been entered.
Response to Arguments made in Amendment
Applicant’s arguments, see pages 8-9 in Applicant Arguments/Remarks Made in an Amendment, filed 04/01/2026, with respect to the 35 U.S.C. § 112(a) and (b) rejections of claims 7, 21-24, and 26 have been fully considered and are persuasive. The amendments clear any issues raised as to new matter and indefiniteness. Therefore, the 35 U.S.C. § 112(a) and (b) rejections of claims 7, 21-24, and 26 have been withdrawn.
Applicant’s arguments, see pages 9-13 in Applicant Arguments/Remarks Made in an Amendment, filed 04/01/2026, with respect to the 35 U.S.C. § 102(a)(1) and 103 rejection(s) of claim(s) 1-9, 21-29 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration and in view of the new limitations introduced in amendment, new ground(s) of rejections are made by obvious combinations.
Claim Objections
Claim 26 is objected to because of the following informalities:
Claim 25 uses a “first epoxy layer” and a “second epoxy layer.” Where claim 26 which depends on claim 25, uses “the first epoxy resin layer” and “the second epoxy resin layer”. It is clear that the first and second epoxy resin layers are calling back to the first and second epoxy layers in claim 25, and for that reason, Examiner believes that this does not rise to a antecedent issue. However, in an effort for consistency, Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over United States Patent Application Publication by Esler et al. (US 20220070996 A1; Esler) in view of United States Patent Application Publication by Yamamoto et al. (US 20180261520 A1, Yamamoto).
Regarding Claim 1, Esler discloses an integrated substrate comprising:
a conductor layer (281);
a heat sink (271) comprising a plurality of fins extending therefrom (Fig. 1, where fins extend from the heatsink 271);
a dielectric layer (291) comprising boron nitride (Para. 29, lines 16-25) chemically bonded to the conductor layer and to the heat sink (Fig. 1, where dielectric layer 291 is bonded to heatsink 271 and conductor layer 281) with an epoxy (Para. 29, lines 16-25);
a semiconductor die (220) coupled over the conductor layer (Fig. 1);
a spacer (257) coupled between the conductor layer and the semiconductor die (Fig. 1); and
A mold compound (226), that is at least coupled directly to the conductor layer 281, and the semiconductor dies 220 (Fig. 1).
However, Esler fails to disclose where the mold compound is also directly coupled to the heat sink (271) and the dielectric layer (291) as well as well.
In a similar field of endeavor, Yamamoto discloses a similarly integrated substrate, comprising at least a conductor layer (Yamamoto: 4), a heatsink (Yamamoto: 2), a dielectric layer (Yamamoto: 3) comprised of boron nitride (Yamamoto: Para. Para. 45, lines 1-4) and bonded to the conductor layer and the heat sink with epoxy (Yamamoto: Para. 45, Para. 44, for bonding, Para. 45. Where it is epoxy). Yamamoto also discloses a mold compound (Yamamoto: 5), where the mold compound is directly coupled to the heat sink, the dielectric layer, the conductive layer, and the semiconductor die (Yamamoto: Para. 48, and Fig. 1).
In view of the disclosure of Yamamoto, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Yamamoto to Esler at the time the instant application was filed to incorporate extending the mold compound of Esler to also directly bond with the heat sink and the dielectric layer as well. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that having mold compound coupled to these components help to prevent warpage of said components due to thermal stress, which leads to improved reliability (Yamamoto: Para. 48)
Claims 1, 3-4, 6-9, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Esler in view of United States Patent Application Publication by Schwab et al. (US 20220122905 A1, Schwab).
Regarding Claim 1, Esler discloses an integrated substrate comprising:
a conductor layer (281);
a heat sink (271) comprising a plurality of fins extending therefrom (Fig. 1, where fins extend from the heatsink 271);
a dielectric layer (291) comprising boron nitride (Para. 29, lines 16-25) chemically bonded to the conductor layer and to the heat sink (Fig. 1, where dielectric layer 291 is bonded to heatsink 271 and conductor layer 281) with an epoxy (Para. 29, lines 16-25);
a semiconductor die (220) coupled over the conductor layer (Fig. 1);
a spacer (257) coupled between the conductor layer and the semiconductor die (Fig. 1); and
A mold compound (226), that is at least coupled directly to the conductor layer 281, and the semiconductor dies 220 (Fig. 1).
However, Esler fails to disclose where the mold compound is also directly coupled to the heat sink (271) and the dielectric layer (291) as well as well.
In a similar field of endeavor, Schwab discloses a similarly integrated substrate, comprising at least a conductor layer (Schwab: 106), a heatsink (Schwab: 126), a dielectric layer (Schwab: 122) comprised of boron nitride (Schwab: Para. 32, lines 8-16) and bonded to the conductor layer and the heat sink with epoxy (Schwab: Para. 32, and Fig. 1). Schwab also discloses a mold compound (Schwab: 104), where the mold compound is directly coupled to the heat sink, the dielectric layer, the conductive layer, and the semiconductor die (Schwab: Fig. 1).
In view of the disclosure of Schwab, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Schwab to Esler at the time the instant application was filed to incorporate extending the mold compound of Esler to also directly bond with the heat sink and the dielectric layer as well. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that having mold compound is directly coupled to the semiconductor die, the conductor layer, the heat sink and the dielectric layer [Die pad in Schwab], while still allowing for access to the underside of the dielectric layer which helps to improve thermal conductivity (Schwab: Para. 4-7).
Regarding Claim 3, the combination of Esler and Schwab discloses the integrated substrate of claim 1, and further comprising a second spacer coupled to the conductor layer and a second semiconductor die coupled to the conductor layer and coupled over the second spacer. (Esler: Fig.1, Where there are two semiconductor dies each having their own spacer. The first die and spacer can be the left die 220 and spacer 257 and the second die and spacer can be considered the right die 220 and spacer 257 in the figure).
Regarding Claim 4, the combination of Esler and Schwab discloses the integrated substrate of claim 1, wherein the mold compound extends partially down the side of the heat sink (Yamamoto: Fig. 1, wherein when using the mold compound deposition areas of Yamamoto, the mold compound will extend down either side of the heatsink).
Regarding Claim 6, the combination of Esler and Schwab discloses the integrated substrate of claim 1, further comprising one or more electrical connectors (Esler: 311) electrically coupled with the conductor layer (Esler: Para. 51, and Fig. 2, where electrical connector 311 is connected to conductor layer 381).
Regarding Claim 7, the combination of Esler and Schwab discloses the integrated substrate of claim 1, further comprising a second conductor layer (Esler: 387), a second heat sink (Esler: 371), and a second dielectric layer (Esler: 392) comprising boron nitride (Esler: Para. 50) coupled with a semiconductor die coupled (Esler: Right semiconductor die in figure 2) with the second (Esler: added second, see above 112(b) rejection) conductor layer.
Regarding Claim 8, the combination of Esler and Schwab disclose the integrated substrate of claim 1, and further wherein the boron nitride of the dielectric layer is a filler in a sheet of epoxy resin (Esler: Para. 43, Lines 16-19).
Regarding Claim 9, the combination of Esler and Schwab discloses the integrated substrate of claim 8, and further wherein the wherein the mold compound encompasses an entire perimeter of the dielectric layer, the conductive layer, and the semiconductor die (Yamamoto: Fig. 1, wherein when using the mold compound deposition areas of Yamamoto, entire perimeter of the dielectric layer, the conductive layer, and the semiconductor die will be encompassed by the mold compound).
Regarding Claim 21, Esler discloses an integrated substrate comprising:
a conductor layer (281);
a heat sink (271) comprising a plurality of fins extending therefrom (Fig. 1, where fins extend from the heatsink 271); and
a dielectric layer (291) comprising boron nitride layer (Para. 29, lines 16-25) chemically bonded to the conductor layer and to the heat sink with an epoxy (Fig. 1, where dielectric layer 291 is bonded to heatsink 271 and conductor layer 281);
a spacer (257) coupled between the conductor layer and the semiconductor die (Fig. 1);
a die attach material (231) coupled between the semiconductor die and the conductor layer (Para. 22, where 231 are contact pads that at the very least that can be used to operatively couple the device to external circuitry, where they are arranged between the die and the contact layer);
wherein the dielectric layer comprises a first epoxy resin layer coupled to a first side of the boron nitride layer, and a second epoxy resin layer coupled to a second side of the boron nitride layer opposite the first side (Para. 43, where there is a coating that can be applied to the first side of dielectric layer 391, that the dielectric layer can be made using fillers such as boron nitride, and that the coatings on either side can be epoxy resin).
A mold compound (226), that is at least coupled directly to the conductor layer 281, and the semiconductor dies 220 (Fig. 1).
However, Esler fails to disclose where the mold compound is also directly coupled to the heat sink (271) and the dielectric layer (291) as well as well.
In a similar field of endeavor, Schwab discloses a similarly integrated substrate, comprising at least a conductor layer (Schwab: 106), a heatsink (Schwab: 126), a dielectric layer (Schwab: 122) comprised of boron nitride (Schwab: Para. 32, lines 8-16) and bonded to the conductor layer and the heat sink with epoxy (Schwab: Para. 32, and Fig. 1). Schwab also discloses a mold compound (Schwab: 104), where the mold compound is directly coupled to the heat sink, the dielectric layer, the conductive layer, and the semiconductor die (Schwab: Fig. 1).
In view of the disclosure of Schwab, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Schwab to Esler at the time the instant application was filed to incorporate extending the mold compound of Esler to also directly bond with the heat sink and the dielectric layer as well. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that having mold compound is directly coupled to the semiconductor die, the conductor layer, the heat sink and the dielectric layer [Die pad in Schwab], while still allowing for access to the underside of the dielectric layer which helps to improve thermal conductivity (Schwab: Para. 4-7).
Regarding Claim 22, the combination of Esler and Schwab discloses the integrated substrate of claim 21, further comprising a plurality of spacers coupled between the conductor layer and a plurality of semiconductor die (Esler: Fig. 2, where there are a plurality of semiconductor dies 320, each of which has a spacer coupled to the die and the conductor layer).
Claims 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Esler in view of United States Patent Application Publication by Basler et al. (US 20160358838 A1, Basler).
Regarding Claim 25, Esler discloses an integrated substrate comprising:
a first conductor layer (381);
a first heat sink (371) comprising a first plurality of fins extending therefrom (Fig. 2, where fins extend from the heatsink 371);
a first dielectric layer (391) comprising boron nitride (Para. 29, lines 16-25) chemically bonded to the first conductor layer and to the first heat sink (Fig. 2, where dielectric layer 391 is bonded to heatsink 371 and conductor layer 381) with a first epoxy layer (Para. 29, lines 16-25);
a second conductor layer (387);
a second heat sink (372) comprising a second plurality of fins extending therefrom (Fig. 2, where fins extend from the heatsink 372);
a second dielectric layer (392) comprising boron nitride chemically bonded to second conductor layer and to the second heat sink with a second epoxy layer (Para. 50, Lines 16-20);
wherein a first surface of the first dielectric layer facing the first conductor layer is planar and spans an entire width of the first dielectric layer (Fig 2).
However, Esler fails to disclose where the length of the first conductive layer is less than the length of the first heat sink; and wherein the length of the second conductive layer is less than the length of the second heat sink.
In a similar field of endeavor, Basler discloses a similarly integrated substrate, comprising at least two conductor layer (Basler: 260_1 and 260_2), two heatsinks (Basler: 190 and 590), two dielectric layers (Basler: 150a and 150b) comprised of boron nitride (Basler: Para. 44, lines 8-16) and bonded to a conductor layer and a heat sink with epoxy (Basler: Para. 43, and Fig. 10). Basler also discloses where the length of the first conductive layer is less than the length of the first heat sink; and wherein the length of the second conductive layer is less than the length of the second heat sink (Figs. 5 and 10, where the heat sinks extend over the device layers including the conductor layers).
In view of the disclosure of Basler, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Basler to Esler at the time the instant application was filed to incorporate the heatsinks in Esler to be extended past the length of the conductor layers. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that having extended heatsinks provide such as improved thermal conductivity (Basler: Para. 65) due to being able to use a clamping (Basler: 510) method between the heatsinks (Basler: Fig. 5, Para. 63-67).
Regarding Claim 26, the combination of Esler and Basler discloses the integrated substrate of claim 25, and further wherein the first dielectric layer comprises the first epoxy
Regarding Claim 27, the combination of Esler and Basler discloses the integrated substrate of claim 25, further comprising a plurality of spacers (Esler: 357) coupled between the first conductor layer and a plurality of semiconductor die (Esler: Fig. 2, where each die has a spacer 357 coupled between the die and the first conductor layer).
Claims 2 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Esler in view Schwab, with further support as to the properties of the materials is given by NPL Qiran Cai et al. (High thermal conductivity of high-quality monolayer boron nitride and its thermal expansion.Sci. Adv.5,eaav0129(2019).DOI:10.1126/sciadv.aav0129 and NPL Jiabin, Hu & Wu, Yajing & Li, Cong & Wang, Laili & Wang, Shenghe & Shi, Zhongqi. (2021). Pressure-assisted direct bonding of copper to silicon nitride for high thermal conductivity and strong interfacial bonding strength. Journal of Materials Science. 56. 10.1007/s10853-021-06521-w.)
Regarding Claim 2, the combination of Esler and Schwab discloses the integrated substrate of claim 1, and further wherein a thermal resistance of the integrated substrate is lower than a direct bonded copper substrate comprising silicon nitride.
In support of the Examiners position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical process, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1997) and MPEP 2112.02.
In further support for examiners position, Cai explains how Boron Nitride is one of the most thermally conductive (Or least thermally resistive) materials used in semiconductors. “According to optothermal Raman measurements, the suspended 1L BN had a high average κ of 751 W/mK at close to room temperature, and therefore, it was one of the best thermal conductors among semiconductors and electrical insulators”. Meanwhile, Jiabin describes the thermal conductivity of the direct bonding of copper substrate and silicon nitride, “Notably, the sample prepared by Si3N4 plate with 5-μm-thickness SiO2 layer and Cu foil with 5.9-μm-thickness oxide layer (Cu2O) exhibited the optimally comprehensive properties with thermal conductivity of 92 W·m⁻¹·K⁻¹” as found in the abstract and text body.
As shown in the NPL cited above just inherency of the materials used, the thermal resistance of the integrated substrate as disclosed by Esler will be lower than a direct bonded copper substrate comprising silicon nitride.
Regarding Claim 24, the combination of Esler and Schwab discloses the integrated substrate of claim 21, and further wherein a thermal resistance of the integrated substrate is lower than a direct bonded copper substrate comprising silicon nitride.
In support of the Examiners position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical process, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1997) and MPEP 2112.02.
In further support for examiners position, Cai explains how Boron Nitride is one of the most thermally conductive (Or least thermally resistive) materials used in semiconductors. “According to optothermal Raman measurements, the suspended 1L BN had a high average κ of 751 W/mK at close to room temperature, and therefore, it was one of the best thermal conductors among semiconductors and electrical insulators”. Meanwhile, Jiabin describes the thermal conductivity of the direct bonding of copper substrate and silicon nitride, “Notably, the sample prepared by Si3N4 plate with 5-μm-thickness SiO2 layer and Cu foil with 5.9-μm-thickness oxide layer (Cu2O) exhibited the optimally comprehensive properties with thermal conductivity of 92 W·m⁻¹·K⁻¹” as found in the abstract and text body.
As shown in the NPL cited above just inherency of the materials used, the thermal resistance of the integrated substrate as disclosed by Esler will be lower than a direct bonded copper substrate comprising silicon nitride.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Esler in view of Basler, with further support as to the properties of the materials is given by NPL Qiran Cai et al. (High thermal conductivity of high-quality monolayer boron nitride and its thermal expansion.Sci. Adv.5,eaav0129(2019).DOI:10.1126/sciadv.aav0129 and NPL Jiabin, Hu & Wu, Yajing & Li, Cong & Wang, Laili & Wang, Shenghe & Shi, Zhongqi. (2021). Pressure-assisted direct bonding of copper to silicon nitride for high thermal conductivity and strong interfacial bonding strength. Journal of Materials Science. 56. 10.1007/s10853-021-06521-w.)
Regarding Claim 29, Esler and Basler discloses the integrated substrate of claim 25, wherein a thermal resistance of the integrated substrate is lower than a direct bonded copper substrate comprising silicon nitride.
In support of the Examiners position, Examiner notes that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical process, a prima facie case of either anticipation or obviousness has been established. In re Best, 195 USPQ 430, 433 (CCPA 1997) and MPEP 2112.02.
In further support for examiners position, Cai explains how Boron Nitride is one of the most thermally conductive (Or least thermally resistive) materials used in semiconductors. “According to optothermal Raman measurements, the suspended 1L BN had a high average κ of 751 W/mK at close to room temperature, and therefore, it was one of the best thermal conductors among semiconductors and electrical insulators”. Meanwhile, Jiabin describes the thermal conductivity of the direct bonding of copper substrate and silicon nitride, “Notably, the sample prepared by Si3N4 plate with 5-μm-thickness SiO2 layer and Cu foil with 5.9-μm-thickness oxide layer (Cu2O) exhibited the optimally comprehensive properties with thermal conductivity of 92 W·m⁻¹·K⁻¹” as found in the abstract and text body.
As shown in the NPL cited above just inherency of the materials used, the thermal resistance of the integrated substrate as disclosed by Esler will be lower than a direct bonded copper substrate comprising silicon nitride.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Esler in view of Schwab and further in view of Yamamoto.
Regarding Claim 23, the combination of Esler and Schwab discloses the integrated substrate of claim 21 but fails to disclose wherein the first heat sink is recessed into a mold compound.
In a similar field of endeavor, Yamamoto discloses an integrated substrate device (Yamamoto: 1), with a conductor layer (Yamamoto: 4), a heatsink (Yamamoto: 2), a dielectric layer (Yamamoto: 3), and a mold compound (Yamamoto: 6) in a similar configuration as the instant application. However, the heatsink in Yamamoto sinks into the mold compound as the sidewalls of the heatsink are against the mold compound (Yamamoto: Fig. 1).
In view of the disclosure of Yamamoto, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Yamamoto to the combination of Esler and Schwab at the time the instant application was filed to incorporate a larger amount of mold compound, such that the heatsink sinks into the excess mold compound. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that sealing the device, including at least the side of the heatsink, in order to hold the device together has (Yamamoto: Para. 33).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Esler in view of Basler and further in view of Yamamoto.
Regarding Claim 28, the combination of Esler and Basler discloses the integrated substrate of claim 25, but fails to disclose wherein the first heat sink is recessed into a mold compound.
In a similar field of endeavor, Yamamoto discloses an integrated substrate device (Yamamoto: 1), with a conductor layer (Yamamoto: 4), a heatsink (Yamamoto: 2), a dielectric layer (Yamamoto: 3), and a mold compound (Yamamoto: 6) in a similar configuration as the instant application. However, the heatsink in Yamamoto sinks into the mold compound as the sidewalls of the heatsink are against the mold compound (Yamamoto: Fig. 1).
In view of the disclosure of Yamamoto, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Yamamoto to the combination of Esler and Basler at the time the instant application was filed to incorporate a larger amount of mold compound, such that the heatsink sinks into the excess mold compound. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that sealing the device, including at least the side of the heatsink, in order to hold the device together has (Yamamoto: Para. 33).
Conclusion
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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