DETAILED ACTION
Election/Restrictions - NO TRAVERSE
A restriction requirement was mailed on 10/6/25.
Applicant’s election without traverse of Group I (method claims 1-16) in the reply filed on 11/5/25 is acknowledged. Applicant canceled the nonelected claims 17-20 and presented new claims 21-24 that are in the elected group.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Image sensor having deep isolation regions
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21 and 24 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2016/0126271 A1 (“Sakurano”).
Sakurano teaches, for example:
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Sakurano teaches:
21. A method, comprising:
epitaxially growing an n-type semiconductor layer 307 (Fig. 5) over a substrate 305;
forming a p-type well (comprising all 311s in regions 303a, see e.g. para 78) in the n-type semiconductor layer;
forming an n-type doped region (e.g. 309, see para 77) in the n-type semiconductor layer and surrounded by the p-type well;
forming a first trench (e.g. 323, see e.g. para 87) extending through the n-type semiconductor layer and a second trench (e.g. another 323) separating the n-type doped region and the p-type well;
depositing a dielectric layer (e.g. 325, see e.g. para 88) in the first trench and the second trench; and
depositing a conductive layer (e.g. 327, see e.g. para 88) over the dielectric layer and in the first trench and the second trench, thereby forming a first feature (e.g. one portion of 325/327) in the first trench and a second feature (e.g. another portion of 325/327) in the second trench,
wherein, in a top view, the first feature surrounds the p-type well, and the second feature surrounds the n-type doped region (see e.g. Fig. 6).
24. The method of claim 21, wherein the p-type well laterally extends from the first feature to the second feature (see e.g. Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7, 9-11, 15, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0126271 A1 (“Sakurano”) in view of US 2012/0199882 A1 (“Shin”).
Sakurano teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A method, comprising:
a substrate 305 (see e.g. Fig. 5);
epitaxially growing an n-type semiconductor layer 307 (Fig. 5);
after the epitaxially growing of the n-type semiconductor layer, forming a p-type well (comprising all 311s in regions 303a, see e.g. para 78) in the n-type semiconductor layer;
forming an n-type doped region (e.g. 309, see para 77) in the n-type semiconductor layer and surrounded by the p-type well;
forming a first trench (e.g. 323, see e.g. para 87) extending through the n-type semiconductor layer and the p-type semiconductor layer and surrounding the p-type well; and
forming a first isolation structure (e.g. 325, and/or 327, see e.g. para 88) in the first trench.
Sakurano does not teach: epitaxially growing a p-type semiconductor layer on a substrate; epitaxially growing the n-type semiconductor layer 307 over the p-type semiconductor layer.
Shin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Sakurano epitaxially growing a p-type semiconductor layer (103, see e.g. para 71 and 74) on a substrate (bulk silicon); epitaxially growing the n-type semiconductor layer (e.g. Sakurano’s layer 307, which corresponds with Shin’s n-type impurity region 111) over the p-type semiconductor layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Shin to the invention of Sakurano. The motivation to do so is that the combination produces the predictable results of allowing for an extra p-type layer between the residual substrate and the N-type epitaxial layer, which allows for an overall P-N-P pinned diode structure (see e.g. para 74 and 111) instead of Sakarano’s PN diode (see e.g. para 45-46), having benefits well known in the art and alluded to in Shin (e.g. having the potential level of the pinned photodiode pinned to a specific value, see e.g. para 74).
Sakurano and Shin together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
2. The method of claim 1, further comprising:
forming a second trench (another 323, see e.g. Fig. 5) to separate the p-type well and the n-type doped region; and forming a second isolation structure (e.g. another 325 and/or 327) in the second trench.
3. The method of claim 2, wherein a depth of the second trench is greater than a depth of the n-type doped region (see e.g. Fig. 5).
4. The method of claim 2, wherein, in a top view, the second isolation structure surrounds the n-type doped region (see e.g. Fig. 6).
7. The method of claim 1, wherein a dopant concentration of an upper portion of the n-type semiconductor layer is different than a dopant concentration of a lower portion of the n-type semiconductor layer (regions such as 313 and 315, at the top of 301, have different concentrations than portions of 301 in other locations, such as near its bottom, see e.g. para 80, 75).
Sakurano teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
9. A method, comprising:
forming an n-type semiconductor layer 307 (Fig. 5) of a photodiode over a top surface of a substrate 305;
forming a p well (comprising all 311s in regions 303a, see e.g. para 78) in the n-type semiconductor layer of the photodiode;
forming a diffusion region (e.g. 315, see para 80) in the n-type semiconductor layer of the photodiode and adjacent the p well;
forming an isolation structure extending through the p well and the n-type semiconductor layer of the photodiode; and
forming a gate structure (e.g. 323, and/or the layers 325 and/or 327 therein, see e.g. para 87) extending through the floating diffusion region and extending into the n-type semiconductor layer of the photodiode,
wherein the gate structure is disposed between the p well and the floating diffusion region (see e.g. Fig. 5),
wherein, in a top view, the gate structure surrounds the floating diffusion region (see e.g. Fig. 6).
Sakurano does not explicitly teach that the diffusion region is a floating diffusion region. Shin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Sakurano that the diffusion region is a floating diffusion region (see e.g. para 59). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Shin to the invention of Sakurano. The motivation to do so is that the combination produces the predictable results of implementing Sakurano’s invention at least in some pixels as a MOS device that has a floating diffusion region to store charges (see e.g. para 16, 59).
Sakurano and Shin together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
10. The method of claim 9, further comprising:
epitaxially forming a p-type semiconductor layer (Shin’s 103, see e.g. para 71 and 74) on the top surface of the substrate, wherein the n-type semiconductor layer of the photodiode is spaced apart from the substrate by the p-type semiconductor layer (see e.g. Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Shin to the invention of Sakurano. The motivation to do so is that the combination produces the predictable results of allowing for an extra p-type layer between the residual substrate and the N-type epitaxial layer, which allows for an overall P-N-P pinned diode structure (see e.g. para 74 and 111) instead of Sakarano’s PN diode (see e.g. para 45-46), having benefits well known in the art and alluded to in Shin (e.g. having the potential level of the pinned photodiode pinned to a specific value, see e.g. para 74).
11. The method of claim 9, wherein the forming of the n-type semiconductor layer comprises epitaxially forming an in-situ doped n-type semiconductor layer over the top surface of the substrate (see e.g. para 76), wherein a dopant concentration of an upper portion of the n-type semiconductor layer is different than a dopant concentration of a lower portion of the n-type semiconductor layer (regions such as 313 and 315, at the top of 301, have different concentrations than portions of 301 in other locations, such as near its bottom, see e.g. para 80, 75).
15. The method of claim 9, wherein a bottom surface of the gate structure is below the floating diffusion region (see e.g. Fig. 5).
Re claim 22, Sakurano teaches claim 21, and further teaches that the depth of the second feature is greater than a depth of the p-type well and the n-type doped region (see e.g. Fig. 5 wherein all 323/325/327 are deeper than the bottom of 307), but does not teach wherein a depth of the first feature is greater than a depth of the second feature.
Shin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Sakurano wherein a depth of the first feature) is greater than a depth of the second feature (see e.g. Fig. 4, wherein isolations 107 at the exterior of the pixel, which are the first features, are deeper than the isolations, which are the second features, surrounding the FD region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Shin to the invention of Sakurano. The motivation to do so is that the combination produces the predictable results of implementing Sakurano’s invention at least in some pixels as a MOS device that has a floating diffusion region to store charges (see e.g. para 16, 59).
Claim(s) 5-6 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0126271 A1 (“Sakurano”) in view of US 2012/0199882 A1 (“Shin”) and US 2017/0373108 A1 (“Hwangbo”).
Sakurano and Shin teach claims 1 and 9, and further teach:
wherein the forming of the first isolation structure comprises: conformally depositing a dielectric liner (e.g. 325) over the substrate; depositing a conductive material layer (e.g. 327) over the dielectric liner (claim 5);
wherein the conductive material layer comprises doped polysilicon (see e.g. para 88), tungsten, titanium, or aluminum (claim 6);
wherein the forming of the isolation structure comprises: performing a first etching process to form a first trench extending through the p well and the n-type semiconductor layer of the photodiode (see e.g. Fig. 5); conformally depositing a dielectric liner (e.g. 325) over the substrate and in the first trench; depositing a conductive material layer (e.g. 327) over the dielectric liner and in the first trench (claim 12);
wherein the forming of the gate structure comprises: performing a second etching process to form a second trench (e.g. another 323) separating the p well and the floating diffusion region, wherein the conformally depositing of the dielectric liner (e.g. 325) further partially fills the second trench, and the depositing of the conductive material layer further fills a remaining portion of the second trench (see e.g. Fig. 5) (claim 14);
Sakurano and Shin do not teach:
performing a planarization process to the dielectric liner and the conductive material layer to expose a top surface of the n-type semiconductor layer (claim 5);
performing a planarization process to the dielectric liner and the conductive material layer to expose a top surface of the n-type semiconductor layer (claim 12);
performing a planarization process to a bottom surface of the substrate to expose the conductive material layer, the bottom surface of the substrate being opposite to the top surface of the substrate; and forming a color filter under the photodiode (claim 13).
Hwangbo teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Sakurano and Shin
performing a planarization process (see e.g. para 76) to the dielectric liner (e.g. gate insulating layer 41) and the conductive material layer (e.g. polysilicon 43, para 76) to expose a top surface of the n-type semiconductor layer (claim 5);
performing a planarization process (see e.g. para 76) to the dielectric liner (e.g. gate insulating layer 41) and the conductive material layer (e.g. polysilicon 43, para 76) to expose a top surface of the n-type semiconductor layer (claim 12);
performing a planarization process (see e.g. para 76) to a bottom surface of the substrate to expose the conductive material layer, the bottom surface of the substrate being opposite to the top surface of the substrate; and forming a color filter (e.g. 70, see e.g. Fig. 6G) under the photodiode (claim 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Hwangbo to the invention of Sakurano and Shin. The motivation to do so is that the combination produces the predictable results of using a well-known CMP method (see e.g. para 76) that planarizes the surface (see e.g. para 76).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0126271 A1 (“Sakurano”) in view of US 2012/0199882 A1 (“Shin”) and US 8937272 B2 (“Hynecek”).
Sakurano and Shin teach claim 1 but do not teach: after the forming of the p-type well in the n-type semiconductor layer, forming a p-type doped region in the n-type semiconductor layer, wherein the p-type doped region is disposed directly under the n-type doped region (see Fig. 3 and associated text in e.g. col 4 lines 15-20, wherein under FD regions 310/212/213, a p+ region 217 is formed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Hynecek to the invention of Sakurano and Shin. The motivation to do so is that the combination produces the predictable results of using a photo-electron blocking layer that prevents pixel cross-talk (see e.g. col 4 lines 15-20).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0126271 A1 (“Sakurano”) in view of US 2012/0199882 A1 (“Shin”) and US 2011/0241079 A1 (“Oike”).
Sakurano and Shin teach claims 1 and 9, but do not further teach: wherein a dopant concentration of the floating diffusion region is greater than a dopant concentration of the p well.
Oike teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Sakurano and Shin wherein a dopant concentration of the floating diffusion region is greater than a dopant concentration of the p well (see e.g. para 135 and 193, wherein the well 132 surrounding the floating diffusion region 125 has a concentration of e.g. 1015 or 1016 cm-3; and para 137, wherein the floating diffusion region 125 has a concentration of e.g. 1019 to 1020 cm-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Oike to the invention of Sakurano and Shin. The motivation to do so is that the combination produces the predictable results of forming the floating diffusion region with a concentration well known in the art to permit electrical connection with wiring contacts (see e.g. para 137).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0126271 A1 (“Sakurano”) in view of US 2017/0373108 A1 (“Hwangbo”).
Sakurano teaches claims 21, but does not further teach: forming an interconnect structure over the first feature and the second feature; planarizing the substrate from its back to expose the conductive layer of the first feature; and forming color filters under the n-type semiconductor layer and the first feature.
Hwangbo teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Sakurano and Shin forming an interconnect structure (e.g. Sakurano’s 327; Hwangbo’s 43) over the first feature and the second feature; planarizing the substrate (e.g. see Hwangbo, para 76) from its back to expose the conductive layer of the first feature; and forming color filters (e.g. 70, see e.g. Fig. 6G) under the n-type semiconductor layer and the first feature.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Hwangbo to the invention of Sakurano. The motivation to do so is that the combination produces the predictable results of using a well-known CMP method (see e.g. para 76) that planarizes the surface (see e.g. para 76).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896