DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 6-20) in the reply filed on 1/21/2026 is acknowledged.
Claims 1-5 have been canceled. Newly added claims 21-25 are directed to elected Group II.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230171938, hereinafter “Xiao ‘938”) in view of Chen et al. (US 20240145591).
Regarding claim 6, Xiao ‘938 teaches, in Figs. 3-9 and 14-16, a method for forming a semiconductor device structure (Abstract), comprising:
forming a channel structure (Fig. 5, middle part of second to left 32, [0066], labelled as 312 in Fig. 4) over a substrate (10, [0052]);
forming a protective spacer (Figs. 3 and 5, 21, [0059]) over sidewalls of the channel structure (middle part of second to left 32) before the channel structure is formed (in Fig. 5);
forming, in Figs. 6-8, an insulating wall (Fig. 8, left 50/40, [0077]) adjacent to an end of the channel structure (middle part of second to left 32) (see Fig. 8);
removing, in Fig. 9, the protective spacer (21) to expose the channel structure (middle part of second to left 32) ([0082]); and
forming a metal gate stack (Fig. 16, 150/170/130, [0108], [0110]) surrounding an intermediate portion of the channel structure (now 112, [0125]).
Xiao ‘938 does not teach that the protective spacer is formed over sidewalls of the channel structure after forming the channel structure.
In a similar field of endeavor, Chen teaches, in Fig. 19, that the protective spacer (11, [0065]) is formed over sidewalls of the channel structure (4, labelled in Fig. 14, [0035]) after forming the channel structure (4 in Fig. 14), in order to protect the stack structure, which includes the channel structure 4 ([0065]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the order of forming a channel structure and forming a protective spacer of Xiao ‘938 with the order of forming a channel structure and forming a protective spacer of Chen, in order to protect the channel structure ([0065]).
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the protective spacer after the channels were formed, since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Regarding claim 7, Xiao ‘938 in view of Chen teaches the limitations of claim 6. Xiao ‘938 further teaches, in Fig. 11, partially removing the insulating wall (left 50/40, [0090]) after the removing of the protective spacer (21 in Fig. 9) and before the formation of the metal gate stack (in Fig. 16).
Regarding claim 8, Xiao ‘938 in view of Chen teaches the limitations of claim 7. Xiao ‘938 further teaches that the insulating wall (50/40) has a first insulating layer (50, [0077]) and a second insulating layer (40, [0077]), the first insulating layer (50) surrounds the second insulating layer (40) (see Fig. 8), and the first insulating layer can be silicon oxide or silicon nitride ([0071]), and the second insulating layer can include “a nitride, an oxide, a high-k dielectric material, or another proper insulating material” ([0076]).
Based on Xiao ‘938’s teachings of the list of materials for the first insulating layer and the second insulating layer described above, one of ordinary skill in the art would have experimented and used different materials for both of these layers, as choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success would be considered as an obvious to try rationale (see MPEP §2143-I E).
A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If the leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348, 82 USPQ2d 1321 (Fed. Cir. 2007).
Regarding claim 9, Xiao ‘938 in view of Chen teaches the limitations of claim 8. Xiao ‘938 further teaches that the partial removal of the insulating wall (50/40) comprises: in Fig. 11, partially removing the first insulating layer (50) to form a recess exposing the second insulating layer (40) (see Fig. 11, [0090]).
Regarding claim 10, Xiao ‘938 in view of Chen teaches the limitations of claim 9. Xiao ‘938 further teaches, in Fig 12, laterally etching the first insulating layer (50) so that the recess (120, [0093]) extends laterally towards a center of the end of the channel structure (middle of second to the left 32).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230171938, hereinafter “Xiao ‘938’”) in view of Chen et al. (US 20240145591), and further in view of Xie et al. (US 20240204100, hereinafter “Xie ‘100”).
Regarding claim 11, Xiao ‘938 in view of Chen teaches limitations of claim 6. Xiao ‘938 in view of Chen does not explicitly teach exposing a top of the channel structure; forming a first epitaxial structure over the top of the channel structure; removing the substrate after the formation of the first epitaxial structure; exposing a bottom of the channel structure; and forming a second epitaxial structure below the bottom of the channel structure.
In a similar field of endeavor, Xie ‘100 teaches, in Fig. 4A, exposing a top of the channel structure (304, [0044]) (by removing 302, [0046], [0056]);
forming a first epitaxial structure (410, [0057]) over the top of the channel structure (304) (see Fig. 4A);
in Fig. 5A, removing the substrate (102, [0066]) after the formation of the first epitaxial structure (410);
in Fig. 6A, exposing a bottom of the channel structure (304); and
in Fig. 9A, forming a second epitaxial structure (940, [0076]-[0077]) below the bottom of the channel structure (304),
because “by omitting the bottom source/drain module during frontside processes, the manufacturing process is simplified while improving device performance and reliability” ([0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of forming a semiconductor device structure of Xiao ‘938 in view of Chen with the epitaxial structure formation of Xie, because by omitting the bottom source/drain module during frontside processes, the manufacturing process is simplified while improving device performance and reliability ([0032]).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230171938, hereinafter “Xiao ‘938’”) in view of Chen et al. (US 20240145591), and further in view of Xie et al. (US 20230055297, hereinafter “Xie ‘297”).
Regarding claim 12, Xiao ‘938 in view of Chen teaches limitations of claim 6. Xiao ‘938 further teaches forming a second channel structure (Fig. 5, middle part of third to left 32, [0066]) over the substrate (10); and
forming a second metal gate stack (150/170/130) surrounding the second channel structure (see Fig. 16).
Xiao ‘938 in view of Chen does not explicitly teach forming a conductive structure between the metal gate stack and the second metal gate stack, wherein the conductive structure electrically connects the metal gate stack and the second metal gate stack.
In a similar field of endeavor, Xie ‘297 teaches, in Fig. 21, forming a conductive structure (154, [0091]) between the metal gate stack (left 142 contacting 154, [0064]) and the second metal gate stack (right 142 contacting 154, [0064]), wherein the conductive structure (154) electrically connects the metal gate stack and the second metal gate stack ([0091]), in order to have a thinner semiconductor structure ([0065]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of forming a semiconductor device structure of Xiao ‘938 in view of Chen with the forming a conductive structure between the metal gate stack and the second metal gate stack of Xie ‘297, in order to have a thinner semiconductor structure ([0065]).
Regarding claim 13, Xiao ‘938 in view of Chen and Xie ‘297 teaches the limitations of claim 12. Xiao ‘938 further teaches, in Fig. 8, forming an isolation structure (second to left 40/50), wherein a portion of the isolation structure is between the channel structure (middle part of second to left 32) and the second channel structure (middle part of third to left 32);
in Fig. 11, removing an upper portion of the isolation structure (second to left 40/50) so that the channel structure (middle part of second to left 32) and the second channel structures (middle part of third to left 32) are exposed ([0082]);
in Figs. 14-16, forming the metal gate stack and the second metal gate stack (150/170/130) surrounding the channel structure (middle part of second to left 32) and the second channel structure (middle part of third to left 32), respectively; and
in Fig. 21, forming a dielectric layer (210, [0121]) over the isolation structure (second to left 40/50) to cover the metal gate stack and the second metal gate stack (150/170/130) ([0121]).
Xie ‘297 further teaches in Figs. 3-4, partially removing the dielectric layer (116, Figs. 2-3, [0032]) to form an opening partially exposing the metal gate stack (114 to the left of the opening, Fig. 4, [0038]) and the second metal gate stack (114 to the right of the opening, Fig. 4, [0038]); and
in Fig. 17, forming the conductive structure (154) in the opening, wherein the conductive structure is in direct contact with the metal gate stack (left 142 contacting 154, [0064]) and the second metal gate stack (right 142 contacting 154, [0064]).
Regarding claim 14, Xiao ‘938 in view of Chen and Xie ‘297 teaches the limitations of claim 13. Xie ‘297 further teaches, in Fig. 18, forming a second conductive structure (158, [0083]) over the conductive structure (154); and forming a gate conductive via (160, [0083]) over the second conductive structure (158) (see Fig. 18).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230171938, hereinafter “Xiao ‘938’”) in view of Chen et al. (US 20240145591) and Xie et al. (US 20230055297, hereinafter “Xie ‘297”), and further in view of Xie et al. (US 20240021609, hereinafter “Xie ‘609”).
Regarding claim 15, Xiao ‘938 in view of Chen and Xie ‘297 teaches the limitations of claim 14. Xie ‘297 further teaches, in Fig. 8, forming a protective cap (134, [0088]) over the conductive structure (labelled as 122 in Fig. 8), wherein a top of the protective cap (134) is substantially level with a top of the dielectric layer (116), and
forming, in Fig. 21, the second conductive structure (158) in the protective cap (134) after an epitaxial structure (130, [0054], Fig. 8) is formed over the top of the channel structure (110, [0061]) (see Fig. 8), wherein the second conductive structure (158) is electrically connected to the conductive structure (154) (see Fig. 21),
Xiao ‘938 in view of Chen and Xie ‘297 does not teach exposing a top of the channel structure after the protective cap is formed.
In a similar field of endeavor, Xie ‘609 teaches, in Fig. 6A, exposing a top of the channel structure (111; [0024], [0031]; by removing hardmask 211 from Fig. 5A) after the protective cap (631, [0034]) is formed, in order to make a VFET with reduced parasitic capacitance ([0001]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of forming a semiconductor device structure of Xiao ‘938 in view of Chen and Xie ‘297 with the channel structure exposing order of Xie ‘609, in order to make a VFET with reduced parasitic capacitance ([0001]).
Claims 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230378064, hereinafter “Xiao ‘064”) in view of Cheng et al. (US 20230072305) and Xiao et al. (US 20230171938, hereinafter “Xiao ‘938”).
Regarding claim 16, Xiao ‘064 teaches, in Figs. 2A-7B, a method for forming a semiconductor device structure (Abstract), comprising:
forming a fin structure ([0044], 101 in Fig. 2A, labelled as 102 in Fig. 4A) over a substrate (see Fig. 2A), wherein the fin structure has a channel layer ([0050]),
forming an isolation feature (121, [0049]) laterally surrounding the fin structure (101) (see Fig. 3A);
partially removing (Fig. 4A, [0049], by trenches 13) the fin structure (101) and the isolation feature (121) (see Fig. 4A, [0048]) to form a first trench (Fig. 4B, b-b' cross-section, left 13, [0048]) and a second trench (Fig. 4B, middle 13, [0048]);
forming an insulating wall (middle 151, [0061]) in the second trench (see Figs. 5A-5B);
forming an isolation structure (left 151, [0061]) in the first trench (see Figs. 5A-5B);
recessing the isolation structure (left 151) to expose the channel layer (middle part of 102, [0050], [0068]) (see Fig. 6A); and
forming a word line structure (16, Fig. 7A, [0066]) surrounding the channel layer (middle part of 102) (see Fig. 7A).
Xiao ‘064 does not teach that the fin structure has a first sacrificial layer, a channel layer, and a second sacrificial layer, and the channel layer is between the first sacrificial layer and the second sacrificial layer, partially removing the channel layer to form a semiconductor nanostructure; and forming a metal gate stack surrounding the semiconductor nanostructure.
In a similar field of endeavor, Cheng teaches, in Fig. 3, that the fin structure (304, [0048]) has a first sacrificial layer (106a’), a channel layer (108a), and a second sacrificial layer (110a) ([0049]), and the channel layer (108a) is between the first sacrificial layer (106a’) and the second sacrificial layer (110a) (see Fig. 3), so that “sacrificial layers are employed in the process that serve as placeholders for the top and bottom source/drain regions” to allow VFET devices to be made with “a late source/drain epitaxy process” ([0038]), which has the advantage of having symmetry in bottom and top channel-to-source/drain junctions ([0086]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of forming a semiconductor device structure of Xiao ‘064 with the sacrificial layers within the fin of Cheng, so that sacrificial layers can act as placeholders for the top and bottom source/drain regions to allow VFET devices to be made with a late source/drain epitaxy process ([0038]), which has the advantage of having symmetry in bottom and top channel-to-source/drain junctions ([0086]).
Xiao ‘064 in view of Cheng does not explicitly teach partially removing the channel layer to form a semiconductor nanostructure; and forming a metal gate stack surrounding the semiconductor nanostructure.
In a similar field of endeavor, Xiao ‘938 teaches, in Fig. 12, partially removing ([0093], 120 is a trench) the channel layer (middle part of 32 in Fig. 11, [0091]) to form a semiconductor nanostructure (112, [0094]) (Fig. 12, [0091]); and,
in Figs. 15-16, forming a metal gate stack (150 and 130/170, Fig. 16, [0112], [0118]) surrounding the semiconductor nanostructure (112, [0094]) (see Fig. 16),
in order to reduce the area of the channel region, “which is beneficial to manufacturing the gate oxide layer subsequently, and can increase the area of the word line, thereby improving the transistor sensitivity” ([0095]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of forming a semiconductor device structure of Xiao ‘064 in view of Cheng with the partial removal of the channel layer and forming a metal gate stack of Xiao ‘938, in order to reduce the area of the channel region, which is beneficial to manufacturing the gate oxide layer subsequently, and can increase the area of the gate metal, thereby improving the transistor sensitivity ([0095]).
Regarding claim 19, Xiao ‘064 in view of Cheng and Xiao ‘938 teaches the limitations of claim 16. Cheng further teaches, in Fig. 19, removing the second sacrificial layer (110a) to expose a top of the semiconductor nanostructure (108a) (see Fig. 19, [0071]);
forming a first epitaxial structure (2104, Fig. 21, [0073]) over the top of the semiconductor nanostructure (108a) (see Fig. 19);
removing the substrate (see Fig. 19) (106” in Fig. 18 is the top part of the substrate that is underneath the fin 304, see Fig. 3 how 102 and 106” form one substrate);
removing the first sacrificial layer (106’) to expose a bottom of the semiconductor nanostructure (108a) (see Fig. 19); and
forming a second epitaxial structure (2102, [0073]) below the bottom of the semiconductor nanostructure (108a) (see Fig. 19).
Regarding claim 20, Xiao ‘064 in view of Cheng and Xiao ‘938 teaches the limitations of claim 16. Xiao ‘064 further teaches forming a dielectric layer (17, [0066]) over the isolation structure (left 15, which used to be 151 in Figs. 5A-5B, [0061]-[0062]) to cover the metal gate stack (16) (see Figs. 8A-8B);
partially removing the dielectric layer (17) to form an opening exposing the metal gate stack (16) (see Fig. 9, [0081]); and
forming a conductive structure (2, [0080]) in the opening, wherein the conductive structure is electrically connected to the metal gate stack (16) (see Fig. 9).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230378064, hereinafter “Xiao ‘064”) in view of Cheng et al. (US 20230072305) and Xiao et al. (US 20230171938, hereinafter “Xiao ‘938”), and further in view of Chen et al. (US 20240145591).
Regarding claim 17, Xiao ‘064 in view of Cheng and Xiao ‘938 teaches the limitations of claim 16. Xiao ‘938 further teaches forming protective spacers (Fig. 3, 21, [0059]) over sidewalls of the channel structure (middle part of second to left 32) before the channel structure is formed (in Fig. 5), and
in Fig. 9, removing the protective spacers (21) after the recessing of the isolation structure (left 40/50; Figs. 8-9; [0077], [0082]) and before the partial removal of the channel layer (middle part of 32 becomes 112) ([0092]-[0094], Fig. 12, 120 is a trench).
Xiao ‘064 in view of Cheng and Xiao ‘938 does not teach that the protective spacer is formed over sidewalls of the channel structure after forming the channel structure.
In a similar field of endeavor, Chen teaches, in Fig. 19, that the protective spacer (11, [0065]) is formed over sidewalls of the channel structure (4, labelled in Fig. 14, [0035]) after forming the channel structure (4 in Fig. 14), in order to protect the stack structure, which includes the channel structure 4 ([0065]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the order of forming a channel structure and forming a protective spacer of Xiao ‘938 with the order of forming a channel structure and forming a protective spacer of Chen, in order to protect the channel structure ([0065]).
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the protective spacer after the channels were formed, since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Regarding claim 18, Xiao ‘064 in view of Cheng, Xiao ‘938, and Chen teaches the limitations of claim 17. Xiao ‘938 further teaches, in Fig. 11, partially removing the insulating wall (second to left 40/50, [0090]) after the removal of the protective spacers (21 in Fig. 9) and before the formation of the metal gate stack (150/170/130 in Fig. 16).
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Xiao et al. (US 20230171938, hereinafter “Xiao ‘938”) in view of Cheng et al. (US 20230072305).
Regarding claim 21, Xiao ‘938 teaches, in Figs. 5-8, 11-12, and 15-16, a method for forming a semiconductor device structure ([Abstract]), comprising:
forming a protruding structure (Fig. 5, second to left 32, [0066]) having a channel layer (middle part of 32, labelled as 312 in Fig. 4) over a substrate (10, [0052]);
forming an insulating wall (Fig. 8, left 50/40, [0077]) beside the protruding structure (second to left 32);
forming an isolation structure (Fig. 8, second to left 50/40, [0077]) beside the protruding structure (second to left 32), wherein the protruding structure (second to left 32) is between the insulating wall (left 50/40) and the isolation structure (second to left 50/40);
in Fig. 11, recessing the isolation structure (second to left 50/40) to expose the channel layer (middle part of second to left 32);
in Fig. 12, partially removing the channel layer (middle part of second to left 32), wherein a remaining portion of the channel layer forms a semiconductor nanostructure (112, [0094]) (Fig. 12, [0091]); and
in Figs. 15-16, forming a gate stack (150 and 130/170, Fig. 16, [0112], [0118]) surrounding the semiconductor nanostructure (112, [0094]) (see Fig. 16).
Xiao ‘938 does not teach that the protruding structure has a first sacrificial layer and a second sacrificial layer over a substrate.
In a similar field of endeavor, Cheng teaches, in Fig. 3, that the protruding structure (304, [0048]) has a first sacrificial layer (106a’) and a second sacrificial layer (110a) ([0049]), so that “sacrificial layers are employed in the process that serve as placeholders for the top and bottom source/drain regions” to allow VFET devices to be made with “a late source/drain epitaxy process” ([0038]), which has the advantage of having symmetry in bottom and top channel-to-source/drain junctions ([0086]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of forming a semiconductor device structure of Xiao ‘938 with the sacrificial layers within the protruding structure of Cheng, so that sacrificial layers can act as placeholders for the top and bottom source/drain regions to allow VFET devices to be made with a late source/drain epitaxy process ([0038]), which has the advantage of having symmetry in bottom and top channel-to-source/drain junctions ([0086]).
Regarding claim 22, Xiao ‘938 in view of Cheng teaches the limitations of claim 21. Xiao ‘938 further teaches, in Fig. 16, that the semiconductor nanostructure (112) is adjacent to the gate stack (150/170/130) and the insulating wall (left 50/40).
Regarding claim 23, Xiao ‘938 in view of Cheng teaches the limitations of claim 21. Xiao ‘938 further teaches that the insulating wall (left 50/40) has a first insulating layer (50) and a second insulating layer (40), the first insulating layer (50) is between the second insulating layer (40) and the semiconductor nanostructure (212), and the method further comprising:
in Fig. 11, partially removing the first insulating layer (50) before the gate stack (150/170/130) is formed (in Fig. 16).
Regarding claim 24, Xiao ‘938 in view of Cheng teaches the limitations of claim 23. Xiao ‘938 further teaches, in Fig. 16, that the gate stack (150/170/130) is formed to laterally extend toward the first insulating layer (50) beyond a sidewall of the semiconductor nanostructure (212).
Regarding claim 25, Xiao ‘938 in view of Cheng teaches the limitations of claim 21. Cheng further teaches removing the second sacrificial layer (110a) (see Fig. 19, [0071]);
forming a first epitaxial structure (2104, Fig. 21, [0073]) over the top of the semiconductor nanostructure (108a) (see Fig. 19);
removing the first sacrificial layer (106’) (see Fig. 19); and
forming a second epitaxial structure (2102, [0073]) over the semiconductor nanostructure (108a), wherein the semiconductor nanostructure (108a) is between the first epitaxial structure (2104) and the second epitaxial structure (2102) (see Fig. 19).
Conclusion
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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