DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-22 are pending.
Claims 4, 6, 7, 15, 17, and 18 are withdrawn.
Claims 1, 9, 10, 21, and 22 are amended.
Claims 19 and 20 are cancelled.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/06/2026 has been entered.
Specification
Amendment of the title of the application in the arguments filed 07/06/2026 overcomes the objection of 03/17/2026. The objection has been withdrawn.
Response to Arguments
Applicant's arguments filed 07/06/2026 have been fully considered but they are not persuasive. Specifically, amendment of independent claim 1 to read “wherein the bottommost first semiconductor structure of the plurality of first semiconductor structures has a thickness less than a thickness of the topmost first semiconductor structure of the plurality of first semiconductor structures” does not overcome the prior art rejection of record. Bhuwalka (US PGPub 2017/0256609) teaches wherein the thickness of the semiconductor structures can decrease in a downward direction (i.e. the thickness of the semiconductor structures at the bottom of the stack is less than the thickness of the semiconductor structure at the top of the stack). The rejection of 03/17/2026 is maintained.
Applicant’s arguments, see pages 10-11, filed 07/06/2026, with respect to amended independent claim 10 have been fully considered and are persuasive. Specifically, introduction of the new claim limitation “wherein a bottommost second layer of the stack of first semiconductor strips has a thickness less than a thickness of a topmost second layer of the stack of first semiconductor strips” has not been considered and overcomes the prior art rejection of record. The rejection of 03/17/2026 has been withdrawn, however a new rejection is made in view of Bhuwalka (US PGPub 2017/0256609).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 8, 9-14, 16, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US PGPub 2022/0173214; herein known as Park) in view of Bhuwalka et al. (US PGPub 2017/0256609; herein known as Bhuwalka).
Regarding claim 1, Park teaches (Figs. 2A-2E) a semiconductor device, comprising: a substrate (Fig. 2C, 100, [0023]) comprising a first active region (Fig. 2C, PR1, [0024]) and a second active region (Fig. 2C, NR1, [0024]) thereon, wherein the first and second active regions extend along a first direction (Fig. 2C, D2); a plurality of first semiconductor structures (Fig. 2C, CH1, [0034]) stacked on the first active region; a plurality of second semiconductor structures (Fig. 2C, CH2, [0034]) stacked on the second active region; a first source/drain (S/D) region (Fig. 2D, SD1, [0060) abutting the plurality of first semiconductor structures; a second S/D region (Fig. 2D, SD2, [0060]) abutting the plurality of second semiconductor structures; a first gate stack (Fig. 2C, GE1, GI1, [0036]) wrapping the plurality of first semiconductor structures and extending along a second direction (Fig. 2C, D3) different from the first direction; and a second gate stack (Fig. 2C, GE1, GL2, [0080]) wrapping the plurality of second semiconductor structures and extending along the second direction, wherein a bottommost first semiconductor structure of the plurality of first semiconductor structures has a width (W1, annotated Fig. 2C below) in the second direction greater than a width (W2, annotated Fig. 2C below) of a topmost first semiconductor structure of the plurality of first semiconductor structures in the second direction (Fig. 2C, D3).
Park does not explicitly teach wherein the bottommost first semiconductor structure of the plurality of first semiconductor structures has a thickness less than a thickness of the topmost first semiconductor structure of the plurality of first semiconductor structures.
Bhuwalka teaches (Fig. 4) wherein the bottommost first semiconductor structure (127a, [0112]) of the plurality of first semiconductor structures has a thickness less than a thickness of the topmost first semiconductor structure (129a, [0112]) of the plurality of first semiconductor structures ([0112]).
Because Park and Bhuwalka are both directed toward GAA semiconductor structures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park and Bhuwalka to include wherein the bottommost first semiconductor structure of the plurality of first semiconductor structures has a thickness less than a thickness of the topmost first semiconductor structure of the plurality of first semiconductor structures in order to maintain desired current flow through the channels ([0112]).
Regarding claim 2, Park in view of Bhuwalka teaches the semiconductor device of claim 1, wherein a bottommost second semiconductor structure of the plurality of second semiconductor structures has a width (Park, W3, annotated Fig. 2C below) in the second direction greater than a width (W4, annotated Fig. 2C below) of a topmost second semiconductor structure of the plurality of second semiconductor structures in the second direction.
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Regarding claim 3, Park in view of Bhuwalka teaches (Park, Fig. 2C) the semiconductor device of claim 1, wherein a space (W4) between the bottommost first semiconductor structure (CH1-SP1, [0076]) and a bottommost second semiconductor structure (CH2-SP1, [0076]) of the plurality of second semiconductor structures is less than a space (W5) between the topmost first semiconductor structure (CH1- SP3, [0076]) and a topmost second semiconductor structure (CH2-SP3, [0076]) of the plurality of second semiconductor structures.
Regarding claim 5, Park in view of Bhuwalka teaches (Park, Fig. 2C) the semiconductor device of claim 1, wherein a trench (TR1, [0102]) formed between the plurality of first semiconductor structures (CH1, [0123]) and the plurality of second semiconductor structures (CH2, [0125]), and the trench has a wider top width (W5) and a narrower bottom width (W4).
Regarding claim 8, Park in view of Bhuwalka teaches (Park, Fig. 2C) the semiconductor device of claim 1, further comprising a dielectric wall (ST, [0026]) disposed in a trench (TR1, TR2, [0026]) between the plurality of first semiconductor structures (CH1, [0125]) and the plurality of second semiconductor structures (CH2, [0125]).
Regarding claim 9, Park in view of Bhuwalka teaches (Park, Fig. 2C) the semiconductor device of claim 1, wherein the plurality of first semiconductor structures (CH1, [0125]) and the plurality of second semiconductor structures (CH2, [0125]) comprise semiconductor wires ([0082]).
Regarding claim 10, Park teaches (annotated Fig. 2C below) a method of forming a semiconductor device, comprising: forming a semiconductor stack on a substrate, wherein the semiconductor stack comprises a plurality of first layers (SUP) and a plurality of second layers (CH1) stacked alternately; patterning the semiconductor stack ([0108]) and the substrate to form a stack of first semiconductor strips and a stack of second semiconductor strips, wherein the stack of first semiconductor strips (CH1) and the stack of second semiconductor strips (CH2) extend along a first direction, the stack of first semiconductor strips has a bottom width (W1) and a top width (W2) in a second direction different from the first direction, and the bottom width (W1) is greater than the top width (W2); forming a dummy gate stack across the stack of first semiconductor strips and the stack of second semiconductor strips; removing portions ([0122]) of the stack of first semiconductor strips (CH1) and the stack of second semiconductor strips (CH2) at opposite sides of the dummy gate stack (described as formed on opposite sides of a sacrificial pattern, [0122]) to form first source/drain (S/D) recesses (RS1, [0122]) and second S/D recesses (RS2, [0126]) exposing the substrate; and forming first S/D regions (SD1, [0123]) in the first S/D recesses and forming second S/D regions (SD2, [0125]) in the second S/D recesses.
Park does not explicitly teach wherein a bottommost second layer of the stack of first semiconductor strips has a thickness less than a thickness of a topmost second layer of the stack of first semiconductor strips.
The disclosure of the instant application fails to teach criticality of wherein a bottommost second layer of the stack of first semiconductor strips has a thickness less than a thickness of a topmost second layer of the stack of first semiconductor strips. Specifically, this limitation is taught (paragraph 0037) as an optional variation of “the second layers may have different thicknesses” and “the first layers and the second layers have the same or different thicknesses,” with the claimed configuration not distinctly pictured or stated as a desirable option, nor any reason given for why this configuration would be desirable or critical.
Bhuwalka teaches wherein first through third semiconductor patterns can have thickness variation in a vertical direction, as a result effective variable, with the result of modification of carrier mobility ([0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Park to include wherein a bottommost second layer of the stack of first semiconductor strips has a thickness less than a thickness of a topmost second layer of the stack of first semiconductor strips in order to modify the carrier mobility of the layers of the device, as a result effective variable, for improvement of carrier mobility of the device, improving switching speed and efficiency.
Regarding claim 11, Park in view of Bhuwalka teaches (Park, Fig. 2C) the method of claim 10, further comprising: removing the dummy gate stack (SAL, [0134]); performing an etching process ([0134]) to remove the plurality of first layers (SAL, [0134]) and form a plurality of gaps between the plurality of the second layers (SP1, SP2, [0133]); forming a gate dielectric layer (GI1, GI2, [0138]) wrapping the plurality of the second layers; forming a first gate electrode (GE1, [0139]) to cover the gate dielectric layer of the stack of first semiconductor strips; and forming a second gate electrode (GE2, [0139]) to cover the gate dielectric layer of the stack of second semiconductor strips.
Regarding claim 12, Park in view of Bhuwalka teaches (Park, Fig. 2C) the method of claim 11, wherein the plurality of first layers (SAL, [0133]) and the plurality of second layers (SP1, SP2, [0133]) have different etching selectivities in the etching process ([0133]).
Regarding claim 13, Park in view of Bhuwalka teaches (Park, Fig. 2C) the method of claim 10, further comprising forming a plurality of inner spacers (GS, [0039]) between the first and second S/D regions (SD1, SD2) and the plurality of first layers (CH1, CH2).
Regarding claim 14, Park in view of Bhuwalka teaches (Park, annotated Fig. 2C below) the method of claim 10, wherein after patterning the semiconductor stack and the substrate, the method further comprises: forming an isolation structure (ST, [0026]) to laterally surround bottom portions of the stack of first semiconductor strips (CH1, [0027]) and the stack of second semiconductor strips (CH2, [0027]); and performing a trimming process ([0122]), so that an upper sidewall of the stack of first semiconductor strips is trimmed to form a first inclined sidewall (FISW, [0027])) and an upper sidewall of the stack of second semiconductor strips is trimmed to form a second inclined sidewall (SISW, [0027]).
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Regarding claim 16, Park in view of Bhuwalka teaches (Park, Fig. 2C) the method of claim 10, wherein after patterning the semiconductor stack and the substrate, the method further comprises: forming a dielectric wall (GI1, [0026]) in a trench between the stack of first semiconductor strips (CH1, [0027]) and the stack of second semiconductor strips (CH2, [0027]).
Regarding claim 21, Park teaches (Figs. 2A-2E) a semiconductor device, comprising : a substrate (Fig. 2C, 100, [0023]) comprising an active region (Fig. 2C, PR1, [0024]) extending along a first direction (Fig. 2C, D2) thereon; a plurality of semiconductor structures (Fig. 2C, CH1, [0034]) stacked on the active region; a source/drain (S/D) region (Fig. 3D, SD1, [0060]) abutting the plurality of semiconductor structures; and a gate stack (Fig. 2C, GE1, GI1, [0036]) wrapping the plurality of semiconductor structures and extending along a second direction (D1) different from the first direction, wherein a bottommost semiconductor structure of the plurality of semiconductor structures has a width (annotated Fig. 2C below, W1) in the second direction (D1) different from a width (annotated Fig. 2C below, W2) of a topmost semiconductor structure of the plurality of semiconductor structures in the second direction.
Park does not explicitly teach wherein the bottommost semiconductor structure of the plurality of semiconductor structures has a thickness less than a thickness of the topmost semiconductor structure of the plurality of semiconductor structures.
Bhuwalka teaches wherein the bottommost first semiconductor structure (127a, [0112]) of the plurality of first semiconductor structures has a thickness less than a thickness of the topmost first semiconductor structure (129a, [0112]) of the plurality of first semiconductor structures ([0112]).
Because Park and Bhuwalka are both directed toward GAA semiconductor structures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park and Bhuwalka to include wherein the bottommost first semiconductor structure of the plurality of first semiconductor structures has a thickness less than a thickness of the topmost first semiconductor structure of the plurality of first semiconductor structures in order to maintain desired current flow through the channels ([0112]).
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Regarding claim 22, Park in view of Bhuwalka teaches (annotated 2C above) the semiconductor device of claim 1, wherein the width of the bottommost semiconductor structure (W2) of the plurality of semiconductor structures is greater than the width of the topmost semiconductor structure (W1) of the plurality of semiconductor structures.
Conclusion
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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