DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Applicant states the “trench surrounds the TSV and the bond pad” in claim 2. The specification does not adequately define how that is represented. Figure 7 shows this, but the corresponding Figure 6 does not show how the trench “surrounds” the bond pad. As a result, the scope of the claim is unclear as to whether the term “surrounds” should be read to enclose all sides as represented in Figure 7 or if the trench extends to the edge or margin of the bond pad as shown in Figure 6. The specification does not provide a standard for ascertaining the structure, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2021/0066222 A1).
Regarding claim 1, Chen et al. discloses a semiconductor device comprising:
a first semiconductor die (400) hybrid bonded (¶0057) to a second semiconductor die (300);
a bond pad (316) comprised in the second semiconductor die (300);
a through-silicon-via (TSV) (408) extending entirely through the first semiconductor die (400) and to the bond pad comprised in the second semiconductor die (300);
a trench formed entirely through the first semiconductor die and to the bond pad comprised in the second semiconductor die (trench is formed in creation of the via 408).
wherein the trench forms an edge seal (444, 450 or 454, 408 as detailed in applicant’s specification which defines the edge seal as a stacked metal layers, see annotated drawing below).
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Regarding claim 3, Chen et al. discloses the semiconductor device of claim 1, further comprising a tungsten grid (108, see paragraph [0017]) at least partially overlapping the trench.
Regarding claim 8, Chen et al. discloses the semiconductor device of claim 1, wherein the trench is present on at least two sides of the TSV (see annotated Figure above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al.
Chen et al. discloses the semiconductor device of claim 1, however the trench as defined above does not surrounds the TSV (408) and the bond pad (316).
As best understood for claim 2, the trench in Chen et al. can be defined to include the bond pad under the TSV because that extends the trench and surrounds the bond pad. It would have been obvious to position the trench in a surrounding arrangement relative to the TSV and bond pad region as a routine design choice to enhance protection and isolation of the interconnect area.
Claims 4 and 7 are rejected under 35 U.S.C. § 103 as being unpatentable over Chen et al. as applied to claim 1, in view of Fujii et al. (US 2020/0020733 A1).
Chen et al. teaches the semiconductor structure of claim 1, including the hybrid-bonded dies, TSV, and trench/edge-seal region. Chen does not expressly disclose that the trench is filled with a nitride material.
Fujii et al. teaches semiconductor through-via / stacked-device structures including nitride-containing films used as protective, insulating, or barrier materials on sidewalls and in via-related structures.
It would have been obvious to one of ordinary skill in the art to use a nitride material in the trench region of Chen because nitride materials were well known for their insulating, barrier, and passivation properties and would have predictably improved protection and reliability of the trench region. Accordingly, claim 4 merely recites an obvious substitution of a known semiconductor dielectric/barrier material into the trench of Chen.
Regarding claim 7, Chen et al. discloses the semiconductor device of claim 1, however, does not expressly disclose a nitride layer coupled over a plurality of sidewalls of the TSV and an encapsulant coupled over sidewalls of the nitride layer, as recited in claim 7.
Fujii et al. teaches TSV-type semiconductor structures having nitride-containing sidewall protection and barrier features associated with the through-via structure. Ref. F further teaches or suggests protective materials and encapsulation techniques for improving via reliability and environmental isolation in stacked semiconductor devices. It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen’s TSV structure to include a nitride layer on the TSV sidewalls, and to further provide an encapsulant over the sidewalls of the nitride layer, in order to improve structural protection, passivation, and reliability of the TSV region. Accordingly, claim 7 merely recites an obvious variation of known TSV sidewall protection and encapsulation structures.
Claims 5 and 6 are rejected under 35 U.S.C. § 103 as being unpatentable over Chen et al. in view of Fujii et al. as applied to claim 4, further in view of Huang et al. (US 2016/0379962 A1).
Chen et al. in view Fujii et al. discloses the semiconductor device of claim 4, does not expressly disclose that the device further comprises a light block material comprised in the trench.
Huang et al. discloses a semiconductor/image-sensor structure having a photodetector configured to receive light and a passivation structure that includes a blocking layer, for example comprising Ti, TiN, or W, disposed in the semiconductor stack to inhibit unwanted light transmission. Huang et al. thus teaches that blocking materials are used in light-sensitive semiconductor structures to reduce light leakage and improve optical isolation.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the trench/edge-seal structure of Chen et al. to include a light block material as taught by Huang et al., because using a blocking layer or light-blocking material in a semiconductor structure exposed to incident light would have predictably improved optical isolation of the photodetector region and reduced undesired light penetration into the trench region. The proposed modification would merely apply a known light-blocking technique to the trench structure of Chen for its expected benefit of suppressing unwanted light ingress. Accordingly, claim 5 merely recites an obvious combination of known semiconductor trench and light-blocking teachings.
Regarding Claim 6, Chen et al. in view of Fujii et al. and further in view of Huang et al. discloses the semiconductor device of claim 5, including the hybrid-bonded semiconductor die structure, TSV, bond pad, and trench/edge-seal arrangement. Chen et al. in view of Fujii et al., however, does not expressly disclose that the light block layer extends over a first side of the first semiconductor die.
Huang et al. discloses a photodetector-based semiconductor structure having a passivation structure that includes a blocking layer disposed over a semiconductor surface in the light-receiving stack. Huang further teaches that such blocking layers may comprise materials such as Ti, TiN, or W, and are used to reduce unwanted light transmission and improve optical isolation in image-sensor structures.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to extend the light block layer over a first side of the first semiconductor die as taught by Huang et al., in order to suppress light leakage, improve optical isolation, and protect the light-sensitive region of the semiconductor device. Applying Huang’s blocking layer arrangement to Chen’s trench/edge-seal structure would have been a predictable modification yielding the expected result of improved light shielding.
Accordingly, claim 6 merely recites an obvious variation of known light-blocking structures in semiconductor devices.
Conclusion
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/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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