DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/17/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10, 13 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2023/0290784 to Do et al (hereinafter Do).
Regarding Claim 1, Do discloses a semiconductor structure, comprising:
a hybrid unit cell (Fig. 2A), comprising:
at least one first sub-cell (R2) having a first cell height (H2), wherein the first sub-cell comprises a plurality of first gate-all-around (GAA) nanosheet transistors (Fig. 1B); and
at least one second sub-cell (R1) having a second cell height (H1), wherein the second sub-cell comprises a plurality of second GAA nanosheet transistors (Fig. 1B),
wherein the first cell height is higher than the second cell height (H2 is greater than H1), and the first GAA nanosheet transistor has a wider nanosheet width than the second GAA nanosheet transistor (A31, for example, is wider than A11).
Regarding Claim 2, Do discloses the semiconductor structure as claimed in Claim 1, wherein the first sub-cell and the second sub-cell have the same cell width (Fig. 2B, for example, A22 and A32 appear to have the same widths).
Regarding Claim 3, Do discloses the semiconductor structure as claimed in Claim 1, wherein the hybrid unit cell is divided into a first group of first sub-cells and a second group of second sub-cells, wherein the number of the first sub-cells in the first group is equal to the number of the second sub-cells in the second group (Fig. 2A).
Regarding Claim 4, Do discloses the semiconductor structure as claimed in Claim 1, wherein the hybrid unit cell is divided into a first group of first sub-cells and a second group of second sub-cells, wherein the number of the first sub-cells in the first group is different from the number of the second sub-cells in the second group [0020]-[0021].
Regarding Claim 5, Do discloses the semiconductor structure as claimed in Claim 1, wherein the first sub-cell comprises a first P-type GAA nanosheet transistor and a first N-type GAA nanosheet transistor, and the second sub-cell comprises a second P-type GAA nanosheet transistor and a second N-type GAA nanosheet transistor (Fig. 2A).
Regarding Claim 6, Do discloses the semiconductor structure as claimed in Claim 5, wherein the first P-type GAA nanosheet transistor and the first N-type GAA nanosheet transistor in the first sub-cell have a first nanosheet width, and the second P-type GAA nanosheet transistor and the second N-type GAA nanosheet transistor in the second sub-cell have a second nanosheet width, wherein the first nanosheet width is greater than the second nanosheet width (Fig. 2A).
Regarding Claim 7, Do discloses the semiconductor structure as claimed in Claim 5, wherein a first nanosheet width of the first P-type GAA nanosheet transistor is greater than a second nanosheet width of the first N-type GAA nanosheet transistor, and a third nanosheet width of the second P-type GAA nanosheet transistor is greater than a fourth nanosheet width of the second N-type GAA nanosheet transistor (Fig. 2A).
Regarding Claim 8, Do discloses the semiconductor structure as claimed in Claim 7, wherein the second nanosheet width is greater than the third nanosheet width (Figs. 6A-6F).
Regarding Claim 9, Do discloses the semiconductor structure as claimed in Claim 7, wherein the second nanosheet width is greater than the fourth nanosheet width and less than the third nanosheet width (Figs. 6A-6F).
Regarding Claim 10, Do discloses a semiconductor structure, comprising:
a hybrid cell array (Fig. 2A) comprising a plurality of hybrid unit cells in a row, wherein each of the hybrid unit cells comprises:
a first sub-cell having a first cell height (H2) and arranged in a first sub-row of the row; and
a second sub-cell having a second cell height (H1) and arranged in a second sub-row of the row,
wherein the first cell height is higher than the second cell height (Fig. 2A),
wherein a plurality of first gate-all-around (GAA) nanosheet transistors of the first sub-cells in the first sub-row have different nanosheet widths (Fig. 4), and a plurality of second GAA nanosheet transistors of the second sub-cells in the second sub-row have different nanosheet widths (Fig. 4).
Regarding Claim 13, Do discloses the semiconductor structure as claimed in Claim 10, wherein nanosheet structures of the first GAA nanosheet transistors of the first sub-cells in the first sub-row are aligned on the same edges of the nanosheet structures that are away from or close to an interface between an N-type well region and a P-type well region of the first sub-cells (Fig. 4).
Regarding Claim 14, Do discloses the semiconductor structure as claimed in Claim 10, wherein nanosheet structures of the first GAA nanosheet transistors of the first sub-cells in the first sub-row are aligned along a centerline of the nanosheet structures (Figs, 1B & 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 12 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Do.
Regarding Claims 11 and 12, Do discloses the semiconductor structure as claimed in Claim 10 but does not explicitly disclose the minimum and maximum nanosheet widths required by Applicant.
However, it would have been obvious to one of ordinary skill, before the effective filing date of the invention, to have modified the nanosheets of Do wherein either (1) a minimum nanosheet width of the first GAA nanosheet transistors in the first sub-row is greater than a maximum nanosheet width of the second GAA nanosheet transistors in the second sub-row, or (2) a maximum nanosheet width of the second GAA nanosheet transistors in the second sub-row is greater than a minimum nanosheet width of the first GAA nanosheet transistors in the first sub-row and less than a maximum nanosheet width of the first GAA nanosheet transistors in the first sub-row. Do notes that the channels have a driving capability corresponding to the channel widths [0021]. Given the teachings and embodiments of Do, it would have been obvious to create sub-cells with varying channel widths depending on the circuit designs desired for a semiconductor device.
Regarding Claim 15, Do discloses a semiconductor structure, comprising:
a hybrid cell array, comprising:
a plurality of hybrid unit cells (Fig. 2A), wherein each of the hybrid unit cells comprises:
a first sub-cell having a first cell height (H2); and
a second sub-cell having a second cell height (H1), wherein a cell height of the hybrid unit cell is equal to a sum of the first and second cell heights; and
a regular cell array, comprising:
a plurality of logic cells (Fig. 4) having a third cell height, wherein the third cell height is greater than the second cell height and less than the first cell height,
wherein a plurality of first gate-all-around (GAA) nanosheet transistors in the first sub-cells have wider nanosheet widths than a plurality of second GAA nanosheet transistors in the second sub-cells (Fig. 2A).
Do does not explicitly wherein the third cell height is greater than the second cell height and less than the first cell height.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the cells of Do such that the third cell height is greater than the second cell height and less than the first cell height. Do notes that the channels have a driving capability corresponding to the channel widths [0021]. Given the teachings and embodiments of Do, it would have been obvious to create sub-cells with varying channel widths depending on the circuit designs desired for a semiconductor device.
Regarding Claim 16, Do makes obvious the semiconductor structure as claimed in Claim 15, wherein the hybrid cell array and the regular cell array have the same array height (Figs. 2A & 4).
Regarding Claims 11 and 12, Do discloses the semiconductor structure as claimed in Claim 15 but does not explicitly disclose the minimum and maximum nanosheet widths required by Applicant.
However, it would have been obvious to one of ordinary skill, before the effective filing date of the invention, to have modified the nanosheets of Do wherein either (1) a minimum nanosheet width of the first GAA nanosheet transistors in the first sub-row is greater than a maximum nanosheet width of the second GAA nanosheet transistors in the second sub-row, or (2) a maximum nanosheet width of the second GAA nanosheet transistors in the second sub-row is greater than a minimum nanosheet width of the first GAA nanosheet transistors in the first sub-row and less than a maximum nanosheet width of the first GAA nanosheet transistors in the first sub-row. Do notes that the channels have a driving capability corresponding to the channel widths [0021]. Given the teachings and embodiments of Do, it would have been obvious to create sub-cells with varying channel widths depending on the circuit designs desired for a semiconductor device.
Regarding Claim 19, Do makes obvious the semiconductor structure as claimed in Claim 15, wherein the first GAA nanosheet transistors of the first sub-cells in the same row of the hybrid cell array have the same nanosheet widths, and the second GAA nanosheet transistors of the second sub-cells in the same row of the hybrid cell array have the same nanosheet widths (Fig. 3B).
Regarding Claim 20, Do makes obvious the semiconductor structure as claimed in Claim 15, wherein the first GAA nanosheet transistors of the first sub-cells in the same row of the hybrid cell array have different nanosheet widths, and the second GAA nanosheet transistors of the second sub-cells in the same row of the hybrid cell array have different nanosheet widths (Fig. 2A).
Conclusion
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893