DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Prosecution on the merits of this application is reopened on claims 1 and 3-7 considered unpatentable for the reasons indicated below: claims 1 and 4-7 are anticipated by or unpatentable over one of the items contained in the IDS filed on December 11, 2025 - International Application No. PCT/US2024/019410, International Preliminary Report on Patentability mailed on October 2, 2025, which cites Cao (CN 112838087 A) as follows:
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cao (CN 112838087 A).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cao (CN 112838087 A) in view of Inaba (United States Patent Application Publication No. US 2021/0202485 A1) and further in view of Zang et al. (USPN 10,134,739 B1).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cao (CN 112838087 A) in view of Zang et al. (USPN 10,134,739 B1).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cao (CN 112838087 A) in view of Iyer et al. (USPN 6,340,615 B1).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cao (CN 112838087 A, hereinafter “Cao”).
In reference to claim 1, Cao discloses a device which meets the claim. Fig. 2-10 of Cao disclose a two-dimensional (2D) dynamic random access memory (DRAM) array which comprises a plurality of bit lines (22) arranged in a first horizontal direction, a plurality of word lines (23) arranged in a second horizontal direction, and a plurality of transistors (21) arranged in a vertical direction that is orthogonal to the first horizontal direction and the second horizontal direction. The plurality of bit lines (22) only partially intersect with bottom source/drain regions (not explicitly shown in figures but disclosed – p. 8 of the machine translation) of the plurality of transistors (21). Fig, 2, 5B, 6D, 8B, 9B, and 10 show that the plurality of transistors (21) are arranged in a honeycomb pattern. The plurality of word lines (23) intersect with gate regions (otherwise known as channel regions) of the plurality of transistors (21).
With regard to claim 7, fig, 2, 5B, 6D, 8B, 9B, and 10 of Cao discloses that the honeycomb pattern arranges the plurality of transistors such that a transistor (21) in the plurality of transistors is neighbored by six other transistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cao in view of Inaba (United States Patent Application Publication No. US 2021/0202485 A1, hereinafter “Inaba”) and further in view of Zang et al. (USPN 10,134,739 B1, hereinafter “Zang”).
In reference to claim 4, Cao does not disclose that the pitch of the bit lines is greater than 2F (F being the feature size). However Inaba discloses that the pitch between adjacent bit lines has a direct impact on the amount of undesired coupling noise (p. 4, paragraph 57). Thus Inaba makes it clear that the pitch of the bit lines is a result effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the pitch of the bit lines, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). In view of the above, adjusting the pitch of the bit lines to be greater than 2F would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to reduce bit line coupling noise. Therefore this limitation is not patentable over Cao and Inaba.
Cao discloses that the unit cell area for the vertical transistor 2D DRAM array in fig. 10 is less than 4F2 by 13% (p. 9 of the machine translation); thus Cao does not disclose that the unit cell area for the 2D DRAM array is 4F2. However Zang discloses that the unit cell area/footprint for a vertical transistor DRAM array can be increased in order to reduce the negative impact of coupling between adjacent bit lines (column 5, lines 66-67, column 6, lines 1-27). Thus Zang makes it clear that the footprint/area of a unit cell is a result effective variable. A smaller footprint increases undesired coupling noise, while a large footprint reduces the coupling noise. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the unit cell area/footprint since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore claim 4 is not patentable over Cao and Zang.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cao in view of Zang.
With regard to claim 5, fig, 2, 5B, 6D, 8B, 9B, and 10 of Cao show that the unit cell area is defined as a non-rectangular parallelogram or as a hexagon in the honeycomb pattern. Cao discloses that the unit cell area for the vertical transistor 2D DRAM array in fig. 10 is less than 4F2 by 13% (p. 9 of the machine translation); thus Cao does not disclose that the unit cell area for the 2D DRAM array is 4F2. However Zang discloses that the unit cell area/footprint for a vertical transistor DRAM array can be increased in order to reduce the negative impact of coupling between adjacent bit lines (column 5, lines 66-67, column 6, lines 1-27). Thus Zang makes it clear that the footprint/area of a unit cell is a result effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the unit cell area/footprint, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore claim 5 is not patentable over Cao and Zang.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cao in view of Iyer et al. (USPN 6,340,615 B1, hereinafter “Iyer”).
In reference to claim 6, fig. 2, 9B, and 10 of Cao disclose a plurality of capacitors (24) that are arranged at top source/drain regions (not explicitly shown in figures but understood to be present) of the plurality of transistors (21). Cao does not disclose the exact footprint/area of each of the capacitors as that claimed by the applicant. However Iyer discloses that the footprint/area of a capacitor in DRAM memory cells can be adjusted for a desired stored charge in the capacitor (column 1, lines 21-48). Thus Iyer makes it clear that the footprint/area of a capacitor is a result effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the footprint/area of a capacitor, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore claim 6 is not patentable over Cao and Iyer.
Allowable Subject Matter
Claims 8-11, 14-16, and 18-22 were allowed in a previous Office action.
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a 2D DRAM array with vertical transistors with bit lines orthogonal to word lines with the suggested structures of the bit lines and spacer as described by the applicant in claim 3. The reasons for the allowability of claims 8-11, 14-16, and 18-22 were discussed in a previous Office action.
Conclusion
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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