Prosecution Insights
Last updated: July 17, 2026
Application No. 18/186,209

PACKAGE STRUCTURE

Final Rejection §102§103§112
Filed
Mar 20, 2023
Priority
Sep 16, 2022 — provisional 63/407,177
Examiner
ESIABA, NKECHINYERE OTUOMASIRICH
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
10 granted / 14 resolved
+3.4% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
31 currently pending
Career history
49
Total Applications
across all art units

Statute-Specific Performance

§103
85.8%
+45.8% vs TC avg
§102
10.2%
-29.8% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Notice is responsive to communication filed on 03/18/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed on 03/18/2026 under 37 C.F.R. 1.111 has been entered. Claims 1-17 remain pending in the application. Claim Rejections - 35 USC § 112 Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites the limitation "the electronic device" in line 9. There is insufficient antecedent basis for this limitation in the claim. The electronic device has antecedent basis in the next section of claim 10, after the limitation was recited in line 9. For the purpose of this Office Action, the examiner will interpret “the electronic device” limitation of line 9 as the electronic device defined subsequently. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 5, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kwon (US 20240055362). Regarding claim 1, Kwon teaches a package structure Fig. 9: 300A, comprising: a semiconductor die Fig. 9: 120 laterally encapsulated by an insulating encapsulation Fig. 9: 130 (para. 0057); a redistribution circuit structure Fig. 9: 161+163+165P+171+175P disposed on the semiconductor die Fig. 9: 120 and the insulating encapsulation Fig. 9: 130, the redistribution circuit structure comprising a colored dielectric layer Fig. 9: 171, inter-dielectric layers Fig. 9: 161 and redistribution conductive layers Fig. 9: 163+165P+175P embedded in the inter-dielectric layers Fig. 9: 161; and an electronic device Fig. 9: 200A disposed over the colored dielectric layer Fig. 9: 171 and electrically connected to the redistribution circuit structure, wherein the colored dielectric layer Fig. 9: 171 is spaced apart from the semiconductor die Fig. 9: 120 by the inter-dielectric layers Fig. 9: 161, and the colored dielectric layer Fig. 9: 171 is between the semiconductor die Fig. 9: 120 and the electronic device Fig. 9: 200A (shown in Fig. 9). Regarding claim 2, Kwon teaches the package structure of claim 1 further comprising conductive terminals Fig. 9: 290 penetrating through the colored dielectric layer Fig. 9: 171, wherein the conductive terminals Fig. 9: 290 are electrically connected to the redistribution circuit structure and the electronic device Fig. 9: 200A (para. 0084). Regarding claim 5, Kwon teaches the package structure of claim 1, wherein the colored dielectric layer Fig. 9: 171 is thicker than each of the inter-dielectric layers Fig. 9: 161 (shown in Fig. 9). Regarding claim 9, Kwon teaches the package structure of claim 1, wherein the insulating encapsulation Fig. 9: 130 encapsulates and is in contact with sidewalls of the semiconductor die Fig. 9: 120 (shown in Fig. 9). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20240055362) as applied to claim 1 above, and further in view of Lin et al. (US 20250210568). Regarding claim 3, Lin discloses the following claim limitations not disclosed by Kwon: The package structure of claim 2 further comprising an underfill Fig. 1: 250 disposed between the colored dielectric layer Fig. 2: 317 and the electronic device Fig. 1: 100 (para. 0015). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kwon with Lin in order to include an underfill for the purpose of reducing thermal resistance form the semiconductor package to the electronic device, and to compensate for differing coefficients of thermal expansion between adjacent semiconductor dies, the RDL structure, the conductive structures, and the substrate (para. 0023). Regarding claim 4, Lin further discloses the following claim limitations not disclosed by Kwon: The package structure of claim 3, wherein the conductive terminals Fig. 1: 322 are laterally encapsulated by the underfill Fig. 1: 250. Regarding claim 10, Kwon discloses a package structure, comprising: a semiconductor die Fig. 9: 120; an insulating encapsulation Fig. 9: 130 laterally encapsulating the semiconductor die Fig. 9: 120; a redistribution circuit structure disposed on the semiconductor die Fig. 9: 120 and the insulating encapsulation Fig. 9: 130, the redistribution circuit structure Fig. 9: 161+163+165P+171+175P comprising a colored dielectric layer Fig. 9: 171, inter-dielectric layers Fig. 9: 161 and redistribution conductive layers Fig. 9: 163+165P+175P embedded in the inter-dielectric layers Fig. 9: 161, wherein the colored dielectric layer Fig. 9: 171 is spaced apart from the insulating encapsulation Fig. 9: 130 by the inter-dielectric layers Fig. 9: 161, and the colored dielectric layer Fig. 9: 171 is between the insulating encapsulation Fig. 9: 130 and the electronic device Fig. 9: 200A; an electronic device Fig. 9: 200A disposed over the colored dielectric layer Fig. 9: 171 and electrically connected to the redistribution circuit structure; and an underfill disposed between the colored dielectric layer and the electronic device. Lin discloses the following claim limitations not disclosed by Kwon: an underfill Fig. 1: 250 disposed between the colored dielectric layer Fig. 2: 317 and the electronic device Fig. 1: 200. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kwon with Lin in order to include an underfill for the purpose of reducing thermal resistance form the semiconductor package to the electronic device, and to compensate for differing coefficients of thermal expansion between adjacent semiconductor dies, the RDL structure, the conductive structures, and the substrate (para. 0023). Regarding claim 11, Kwon teaches the package structure of claim 10 further comprising conductive terminals Fig. 9: 290 penetrating through the colored dielectric layer Fig. 9: 171, wherein the conductive terminals Fig. 9: 290 are electrically connected to the redistribution circuit structure (via 175P) and the electronic device Fig. 9: 200A. Regarding claim 12, Lin further discloses the following claim limitations not disclosed by Kwon: The package structure of claim 11 further comprising an underfill Fig. 1: 250 disposed between the colored dielectric layer Fig. 2: 317 and the electronic device Fig. 1: 200. Regarding claim 13, Lin further discloses the following claim limitations not disclosed by Kwon: The package structure of claim 12, wherein the conductive terminals Fig. 1: 322 are laterally encapsulated by the underfill Fig. 1: 250. Regarding claim 14, Kwon teaches the package structure of claim 10, wherein the colored dielectric layer Fig. 9: 171 is thicker than each of the inter-dielectric layers Fig. 9: 161 (shown in Fig. 9). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20240055362) as applied to claim 1 above, and further in view of Yu (US 20140264930). Regarding claim 6, Yu discloses the following claim limitations not disclosed by Kwon: The package structure of claim 5, wherein a thickness of the colored dielectric layer Fig. 2D: 106 ranges from about 11 micrometers to about 30 micrometers (col. 2, lines 63-67 and col. 3, lines 49-60 disclose a polymer layer over the die 102 having a thickness of 5µm to 15µm. This range is overlapping with the range taught in claim 6.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kwon with Yu in order to have a polymer layer that acts as a shield for contact pads and dies during the grinding process, reducing manufacturing costs (col. 4, lines 57-61). Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20240055362) as applied to claim 1 above, and further in view of Han et al. (US 20200111742). Regarding claim 7, Kwon teaches the package structure of claim 1: wherein the colored dielectric layer Fig. 9: 171 comprises polybenzoxazole-based material layers or polyimide-based material layers (para. 0036 teaches a material including prepreg, an Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), a solder resist, or PID, some of which are polyimides), and the colored dielectric layer and the inter-dielectric layers are different in color. Han discloses the following claim limitations not disclosed by Kwon: The colored dielectric layer Fig. 9: 132 and the inter-dielectric layers Fig. 9: 190 are different in color (i.e. black ABF of the colored dielectric layer and transparent resin of the inter-dielectric layers taught in para. 0066). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kwon with Han in order to secure visibility of a mark of identification information formed on the surface of the colored dielectric layer (para. 0066). Regarding claim 8, Kwon teaches the package structure of claim 1: wherein the colored dielectric layer Fig. 9: 171 comprises a polybenzoxazole-based material layers or a polyimide-based material layers, and a material of the inter-dielectric layers is different from a material of the colored dielectric layer. Han further discloses the following claim limitations not disclosed by Kwon: a material of the inter-dielectric layers Fig. 9: 190 is different from a material of the colored dielectric layer Fig. 9: 132 (i.e. black ABF of the colored dielectric layer and transparent resin of the inter-dielectric layers taught in para. 0066). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kwon and Lin with Han in order to secure visibility of a mark of identification information formed on the surface of the colored dielectric layer (para. 0066). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20240055362) and Lin et al. (US 20250210568) as applied to claim 10 above, and further in view of Yu et al. (US 20140264930). Regarding claim 15, Yu discloses the following claim limitations not disclosed by Kwon: The package structure of claim 14, wherein a thickness of the colored dielectric layer Fig. 2D: 106 ranges from about 11 micrometers to about 30 micrometers (col. 2, lines 63-67 and col. 3, lines 49-60 disclose a polymer layer over the die 102 having a thickness of 5µm to 15µm. This range is overlapping with the range taught in claim 6.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kwon and Lin with Yu in order to have a polymer layer that acts as a shield for contact pads and dies during the grinding process, reducing manufacturing costs (col. 4, lines 57-61). Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20240055362) and Lin et al. (US 20250210568) as applied to claim 10 above, and further in view of Han et al. (US 20200111742). Regarding claim 16, Kwon teaches the package structure of claim 10: wherein the colored dielectric layer Fig. 9: 171 comprises polybenzoxazole-based material layers or polyimide-based material layers (para. 0036 teaches a material including prepreg, an Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), a solder resist, or PID, some of which are polyimides), and the colored dielectric layer and the inter-dielectric layers are different in color. Han discloses the following claim limitations not disclosed by Kwon: The colored dielectric layer Fig. 9: 132 and the inter-dielectric layers Fig. 9: 190 are different in color (i.e. black ABF of the colored dielectric layer and transparent resin of the inter-dielectric layers taught in para. 0066). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kwon and Lin with Han in order to secure visibility of a mark of identification information formed on the surface of the colored dielectric layer (para. 0066). Regarding claim 17, Kwon teaches the package structure of claim 10: wherein the colored dielectric layer Fig. 9: 171 comprises a polybenzoxazole-based material layers or a polyimide-based material layers, and a material of the inter-dielectric layers is different from a material of the colored dielectric layer. Han further discloses the following claim limitations not disclosed by Kwon: a material of the inter-dielectric layers Fig. 9: 190 is different from a material of the colored dielectric layer Fig. 9: 132 (i.e. black ABF of the colored dielectric layer and transparent resin of the inter-dielectric layers taught in para. 0066). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kwon and Lin with Han in order to secure visibility of a mark of identification information formed on the surface of the colored dielectric layer (para. 0066). Response to Arguments Applicant’s arguments with respect to claim(s) 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nkechinyere Esiaba/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 20, 2023
Application Filed
Dec 18, 2025
Non-Final Rejection mailed — §102, §103, §112
Mar 18, 2026
Response Filed
May 13, 2026
Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
99%
With Interview (+33.3%)
3y 6m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allowance rate.

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