DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 3-5, filed May 18, 2026, with respect to the rejections of claims 1, 16, and 21 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Applicant's request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Horch (US 10446562 B1), Wong et al. (US 9613714 B1), Smith (US 20110248356 A1), and Booth et al. (US 20100032732 A1).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-10, 15, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horch (US 10446562 B1).
Regarding claim 1, Figs. 3 and 4 of Horch disclose a cell (Fig. 4, OTP bitcell 400, col. 7, line 40) comprising:
a first insulating layer (Fig. 4, I/O gate oxide 435, core gate oxide 445, col. 7, lines 54-56) located between a semiconductor body (“substrate”, col. 2, lines 45-47) and a second conductive or semi-conductive layer (Fig. 4, select gate 430, anti-fuse gate 440, col. 7, lines 54-56),
wherein the first insulating layer (435, 445) comprises a peripheral portion (435) and a central portion (445),
wherein the peripheral portion (435) has a greater thickness (Fig. 4, “the I/O gate oxide 435 is about twice as thick as the core gate oxide 445”, col. 7, lines 61-62) than the central portion (445) (Fig. 3 shows that portion 445 is towards the center of the device 300),
wherein the cell (400) is a programmable read-only memory (“Embodiments relate to a one-time programmable (OTP) memory device”, col. 2, lines 36-37), and
wherein, during a programming of the cell, a current flows through the cell between the second conductive or semi-conductive layer (430, 440) and a region of the semiconductor body (“substrate”), through the first insulating layer (435, 445), with a value sufficiently high to damage the first insulating layer (435, 445) in a predetermined location within the central portion (445) (“This high voltage difference between the anti-fuse gate 440 and the drain region 410 ruptures a portion of the core gate oxide 445, creating a short or an “anti-fuse”…, the rupture will form in the core gate oxide 445 because it is thinner than the I/O gate oxide 435”, col. 8, lines 6-13).
Regarding claim 2, Figs. 3 and 4 of Horch disclose the cell of claim 1 as applied above, and Fig. 4 of Horch further discloses wherein the semiconductor body (“substrate”) is in direct contact with the first insulating layer (435, 445), and wherein the second conductive or semi-conductive layer (430, 440) is in direct contact with the first insulating layer (435, 445).
Regarding claim 3, Figs. 3 and 4 of Horch disclose the cell of claim 1 as applied above, and Fig. 4 of Horch further discloses wherein the semiconductor body (“substrate”) and the second conductive or semi-conductive layer (430, 440) are not in direct contact with each other.
Regarding claim 4, Figs. 3 and 4 of Horch disclose the cell of claim 1 as applied above, and Fig. 4 of Horch further discloses wherein a thickness of the central portion (445) is substantially constant, and wherein a thickness of the peripheral portion (435) is substantially constant.
Regarding claim 5, Figs. 3 and 4 of Horch disclose the cell of claim 1 as applied above, and Fig. 4 of Horch further discloses wherein a thickness of the peripheral portion (435) is at least one and a half times greater than a thickness of the central portion (445) (“the I/O gate oxide 435 is about twice as thick as the core gate oxide 445”, col. 7, lines 61-62).
Regarding claim 6, Figs. 3 and 4 of Horch disclose the cell of claim 1 as applied above, and Fig. 4 of Horch further discloses wherein the semiconductor body (“substrate”) comprises a first region (Fig. 4, low doped region 350, col. 7, 12) and a second region (Fig. 4, high doped region 355, col. 7, 13), the second region (355) being more heavily doped than the first region (350), and wherein the central portion (445) is in direct contact with the second region (355).
Regarding claim 8, Fig. 4 of Horch discloses the cell of claim 6 as applied above, and Fig. 4 of Horch further discloses wherein a peripheral portion of the second region (355) is covered with the peripheral portion (435).
Regarding claim 9, Fig. 4 of Horch discloses the cell of claim 6 as applied above, and Fig. 4 of Horch further discloses wherein a portion of the second region (355), which is not covered with the central portion (445), is covered with the peripheral portion (435).
Regarding claim 10, Fig. 4 of Horch discloses the cell of claim 6 as applied above, and Fig. 4 of Horch further discloses wherein a dopant concentration of the second region (355) is at least twice as much as a dopant concentration of the first region (350) (“The high doped region 155 may have at least twice the doping concentration of the low doped region 150”, col. 5, lines 30-32).
Regarding claim 15, Figs. 3 and 4 of Horch disclose the cell of claim 1 as applied above, and Fig. 4 of Horch further discloses wherein the second conductive or semi-conductive layer (430, 440) covers only the first insulating layer (435, 445).
Regarding claim 21, Figs. 3 and 4 of Horch disclose a programmable read-only memory cell (400), comprising:
a semiconductor body (“substrate”);
a conductive layer or a semi-conductive layer (430, 440); and
a first insulating layer (435, 445) located between the semiconductor body (“substrate”) and the conductive layer or semi-conductive layer (430, 440), the first insulating layer (435, 445) comprising a central portion (445) and a peripheral portion (435) having a thickness greater than the central portion (445),
wherein, during a programming of the programmable read-only memory cell (400), a current flows through the programmable read-only memory cell (400) between the conductive layer or the semi-conductive layer (430, 440) and a region of the semiconductor body (“substrate”), through the first insulating layer (435, 445), with a value sufficiently high to damage the first insulating layer (435, 445) in a predetermined location within the central portion (445) (“This high voltage difference between the anti-fuse gate 440 and the drain region 410 ruptures a portion of the core gate oxide 445, creating a short or an “anti-fuse”…, the rupture will form in the core gate oxide 445 because it is thinner than the I/O gate oxide 435”, col. 8, lines 6-13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Horch (US 10446562 B1) in view of Wong et al. (US 9613714 B1) herein after “Wong”.
Regarding claim 7, Fig. 4 of Horch discloses the cell of claim 6 as applied above, and Figs. 5-6 of Horch disclose using doped regions to control the location of the rupture. But Horch fails to disclose wherein the second region surrounds a portion of the first region, the central portion only resting on the second region and on the portion of the first region.
In the similar field of endeavor of one time programming memory cells, Fig. 8B of Wong discloses wherein the second region (Fig. 8B, doped regions 310, 320, col. 17, lines 9-10) surrounds a portion of the first region (Fig. 8B, channel portion of P-well region PW, col. 17, lines 5-7), the central portion (Fig. 8B, thin portion of gate oxide layer 352, col. 17, line 6) only resting on the second region (310, 320) and on the portion of the first region (channel).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Horch with the regions as disclosed by Wong, to obtain the desired rupture properties when programming the cell (see Wong, col. 17, lines 64-66).
Claims 12-13, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Horch (US 10446562 B1) in view of Smith (US 20110248356 A1).
Regarding claim 12, Fig. 4 of Horch discloses the cell of claim 6 as applied above, and Fig. 4 of Horch further discloses wherein the semiconductor body (“substrate”) further comprises a third region (Fig. 4, drain region 410, col. 7, lines 47-48), wherein the third region (410) surrounds the second region (355), and wherein the third region (410) comprises at least a portion that is not covered with the first insulating layer (435, 445).
Horch fails to explicitly disclose wherein the third region is more heavily doped than the second region.
In the similar field of endeavor of OTP memory devices, Fig. 1 of Smith discloses wherein the third region (Fig. 1, implant regions 111, ¶ [0019]) is more heavily doped than the second region (Fig. 1, lightly doped extension regions 113, ¶ [0019]) (“Lightly doped extension regions 113 and 114 can be, for example, lightly doped N type implant region extensions of implant regions 111 and 112 respectively”, ¶ [0034]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Horch with the regions as disclosed by Smith, to obtain the desired electric field properties (see Smith, ¶ [0034]).
Regarding claim 13, Horch and Smith together disclose the cell of claim 12 as applied above, and Fig. 4 of Horch further discloses further comprising at least one conductive contact (Fig. 4, bitline contact 425, col. 7, line 49) in direct contact with the third region (410).
Regarding claim 16, Figs. 3 and 4 of Horch disclose a cell (300) comprising:
a semiconductor body (“substrate”) comprising an upper surface, a lower surface, a side surface, two first doped regions (410) and two second doped regions (355), and wherein the first doped regions (410) are closer to the side surface than the second doped regions (355);
a first insulating layer (435, 445) arranged directly on the semiconductor body (“substrate”) the first insulating layer (435, 445) comprising a peripheral portion (435) and a central portion (445); and
a second conductive or semi-conductive layer (430, 440) arranged directly on the first insulating layer (435, 445),
wherein the peripheral portion (435) has a greater thickness than the central portion (445),
wherein the peripheral portion (435) is in direct contact with the first (410) and second doped regions (355),
wherein the central portion (445) is in direct contact with the semiconductor body (“substrate”) and the second doped regions (355) but not with the first doped regions (410),
wherein the cell (400) is a programmable read-only memory, and
wherein, during a programming of the cell, a current flows through the cell between the second conductive or semi-conductive layer (430, 440) and a region of the semiconductor body (“substrate”), through the first insulating layer (435, 445), with a value sufficiently high to damage the first insulating layer (435, 445) in a predetermined location within the central portion (445) (“This high voltage difference between the anti-fuse gate 440 and the drain region 410 ruptures a portion of the core gate oxide 445, creating a short or an “anti-fuse””, col. 8, lines 6-9).
Horch fails to disclose wherein each of the first doped regions extends more from the upper surface to the lower surface than each of the second doped regions.
In the similar field of endeavor of OTP memory devices, Fig. 1 of Smith discloses wherein each of the first doped regions (111) extends more from the upper surface to the lower surface than each of the second doped regions (113).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Horch with the regions as disclosed by Smith, to obtain the desired electric field properties (see Smith, ¶ [0034]).
Regarding claim 17, Horch and Smith together disclose the cell of claim 16 as applied above, and Fig. 4 of Horch further discloses wherein a thickness of the central portion (445) is substantially constant, and wherein a thickness of the peripheral portion (435) is substantially constant.
Regarding claim 18, Horch and Smith together disclose the cell of claim 16 as applied above, the combination fails to explicitly disclose wherein a thickness of the central portion is at least equal to 0.5 µm.
However, it would have been obvious to one of ordinary skill in the art before the time of the effecting filing date of the invention to modify the insulating layer of Horch such that the thickness was at least equal to 0.5 µm through optimization of the production process within the prior art and/or because it has been ruled that changes of relative dimensions are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV(A)).
Regarding claim 19, Horch and Smith together disclose the cell of claim 16 as applied above, and Fig. 4 of Horch further discloses wherein a ratio between a width of the peripheral portion (435) and a width of the central portion (445) is greater than or equal to 2 (“the I/O gate oxide 435 is about twice as thick as the core gate oxide 445”).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Horch (US 10446562 B1) in view of Booth et al. (US 20100032732 A1) herein after “Booth”.
Regarding claim 14, Figs. 3 and 4 of Horch disclose the cell of claim 1 as applied above, but Horch fails to explicitly disclose wherein a ratio between a width of the peripheral portion and a width of the central portion is greater than or equal to 2.
In the similar field of endeavor of electrical antifuses, Fig. 9B of Booth discloses wherein a ratio between a width of the peripheral portion (32) and a width of the central portion (34) is greater than or equal to 2 (Fig. 8B shows that the combined width of the peripheral portion is at least twice greater than the width of the central portion).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Horch with the insulating layer as disclosed by Booth, to control the position of the breakdown during programming (see Booth, ¶ [0060]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Horch (US 10446562 B1) and Smith (US 20110248356 A1) in further view of Booth (US 20100032732 A1).
Regarding claim 20, Horch and Smith together disclose the cell of claim 16 as applied above, but Horch and Smith fail to disclose comprising:
a spacer arranged on the first doped regions and covering side surfaces of the first insulating layer and the second conductive or semi-conductive layer;
first vias directly contacting the first doped regions; and
a second via directly contacting the second conductive or semi-conductive layer.
In the similar field of endeavor of electrical antifuses, Fig. 9B of Booth discloses comprising:
a spacer (Fig. 9B, gate spacer 44, ¶ [0055]) arranged on the first doped regions (Fig. 9B, drain region 14, ¶ [0055]) and covering side surfaces of the first insulating layer (Fig. 9B, gate dielectric 30, ¶ [0050]) and the second conductive or semi-conductive layer (Fig. 9B, gate electrode 40, ¶ [0054]);
first vias (Fig. 9B, drain contact via 84, ¶ [0057]) directly contacting the first doped regions (14); and
a second via (Fig. 9B, gate contact via 86, ¶ [0057]) directly contacting the second conductive or semi-conductive layer (40).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Horch with the spacers and vias as disclosed by Booth, to allow interconnection to the device (see Booth, ¶ [0057]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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