DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed January 6, 2025. Claims 1-4, 12, 15-17, and 20 have been amended. Claim 21 has been added. Claim 11 has been canceled. Currently, claims 1-10, and 12-21 are pending.
Applicant’s amendments to the Specification overcome the specification objection outlined in the previous Office Action. The Specification objection has been withdrawn.
Applicant’s amendments to claims 4, 16, and 17 overcome the claim objections outlined in the previous Office Action. The objections to claims 4, 16, and 17 have been withdrawn.
Applicant’s amendments to claims 2-3, 11-13, 15, and 20 overcome the 112(b) rejections outlined in the previous Office Action. The 112(b) rejections of claims 2-3, 11-13, 15, and 20 have been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 14-15, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Eitan (US 6201282 B1) in view of Eltoukhy et al. (US 5163180 A) herein after “Eltoukhy”.
Regarding claim 1, Figs. 2 and 7 of Eitan disclose a cell (Fig. 7, cell 10, col. 3, line 14) comprising:
a first insulating layer (Fig. 7, gate oxide layer 20, col. 3, lines 9-10) located between a semiconductor body (Fig. 2, substrate 18, col. 3, line 7) and a second conductive or semi-conductive layer (Fig. 7, gate layer 22, col. 5, line 3),
wherein the first insulating layer (20) comprises a peripheral portion (see Annotation 1, Fig. 7 of Eitan, “20b”) and a central portion (see Annotation 1, Fig. 7 of Eitan, “20a”),
wherein the peripheral portion (20b) has a greater thickness (Fig. 7, “This provides two different gate oxide thicknesses to the periphery and the array areas, where the gate oxide in the array is thicker than that of the periphery.”, col. 7, lines 20-22) than the central portion (20a), and
wherein the cell (10) is a programmable read-only memory (“mask programmable, dual bit array”, col. 2, line 67).
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Annotation 1, Fig. 7 of Eitan
Eitan fails to disclose wherein, during a programming of the cell, a current flows through the cell between the second conductive or semi-conductive layer and a region of the semiconductor body, through the first insulating layer, with a value sufficiently high to damage the first insulating layer in a predetermined location within the central portion.
In the similar field of endeavor of programmable read only memory devices, Fig. 1 of Eltoukhy discloses wherein, during a programming of the cell (Fig. 1, antifuse 10, col. 4, line 29), a current flows through the cell (10) between the second conductive or semi-conductive layer (Fig. 1, gate 16, col. 4, line 56) and a region of the semiconductor body (Fig. 1, silicon substrate 12, col. 4, line 29), through the first insulating layer (Fig. 1, gate dielectric layer 14, col. 4, line 33), with a value sufficiently high to damage the first insulating layer in a predetermined location within the central portion (“energetic holes (or hot holes as they are commonly called) are injected into the dielectric 14. It is known that hole injection into a dielectric such as S.sub.i O.sub.2 causes or accelerates the dielectric breakdown process”, col. 5, lines 57-61).
It would have been obvious to one of ordinary skill in the art before the time of the effective filing date of the invention to substitute the mask programming of Eitan for the fusible programming disclosed by Eltoukhy. The fusible programming method was known in the art and could have been employed in the device disclosed by Eitan with no change in the devices function, and the combination would have yielded the predictable result of programming the cell to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007) (MPEP 2141).
Regarding claim 2, Eitan and Eltoukhy together disclose the cell according to claim 1 as applied above, and Fig. 7 of Eitan further discloses wherein the semiconductor body (18) is in direct contact with the first insulating layer (20), and wherein the second conductive or semi-conductive layer (22) is in direct contact with the first insulating layer (20).
Regarding claim 3, Eitan and Eltoukhy together disclose the cell according to claim 1 as applied above, and Fig. 7 of Eitan further discloses wherein the semiconductor body (18) and the second conductive or semi-conductive layer (22) are not in direct contact with each other.
Regarding claim 4, Eitan and Eltoukhy together disclose the cell according to claim 1 as applied above, and Fig. 7 of Eitan further discloses wherein a thickness of the central portion (20a) is substantially constant, and wherein a thickness of the peripheral portion (20b) is substantially constant.
Regarding claim 5, Eitan and Eltoukhy together disclose the cell according to claim 1 as applied above, and Fig. 7 of Eitan further discloses wherein a thickness of the peripheral portion (20b) is at least one and a half times greater (“the gate oxide layer 20 is 2-3 times thicker over the bit lines 16”, col. 7, lines 9-10) than a thickness of the central portion (20a).
Regarding claim 6, Eitan and Eltoukhy together disclose the cell according to claim 1 as applied above, and Fig. 7 of Eitan further discloses wherein the semiconductor body (18) comprises a first region (Fig. 7, channel 14, col. 3, line 6) and a second region (Fig. 7, bit lines 16, col. 3, line 7), the second region (16) being more heavily doped than the first region (14) (“the bit lines 16 are implanted”, col. 4, line 39), and wherein the central portion (20a) is in direct contact with the second region (16).
Regarding claim 7, Fig. 7 of Eitan disclose the cell according to claim 6 as applied above, and Fig. 7 of Eitan further discloses wherein the second region (16) surrounds a portion of the first region (14), the central portion (20a) only resting on the second region (16) and on the portion of the first region (14).
Regarding claim 8, Fig. 7 of Eitan disclose the cell according to claim 6 as applied above, and Fig. 7 of Eitan further discloses wherein a peripheral portion of the second region (16) is covered with the peripheral portion (20b).
Regarding claim 9, Fig. 7 of Eitan disclose the cell according to claim 6 as applied above, and Fig. 7 of Eitan further discloses wherein a portion of the second region (16), which is not covered with the central portion (20a), is covered with the peripheral portion (20b).
Regarding claim 14, Eitan and Eltoukhy together disclose the cell according to claim 1 as applied above, and Fig. 7 of Eitan further discloses wherein a ratio between a width of the peripheral portion (20b) and a width of the central portion (20a) is greater than or equal to 2 (“the gate oxide layer 20 is 2-3 times thicker over the bit lines 16”, col. 7, lines 9-10).
Regarding claim 15, Eitan and Eltoukhy together disclose the cell according to claim 1 as applied above, and Fig. 7 of Eitan further discloses wherein the second conductive or semi-conductive layer (22) covers only the first insulating layer (20).
Regarding claim 21, Figs. 2 and 7 of Eitan disclose a programmable read-only memory cell (10), comprising:
a semiconductor body (18);
a conductive layer or a semi-conductive layer (22); and
a first insulating layer (20) located between the semiconductor body (18) and the conductive layer or semi-conductive layer (22), the first insulating layer (20) comprising a central portion (20a) and a peripheral portion (20b) having a thickness greater than the central portion (20a).
Eitan fails to disclose wherein, during a programming of the cell, a current flows through the cell between the second conductive or semi-conductive layer and a region of the semiconductor body, through the first insulating layer, with a value sufficiently high to damage the first insulating layer in a predetermined location within the central portion.
In the similar field of endeavor of programmable read only memory devices, Fig. 1 of Eltoukhy discloses wherein, during a programming of the cell (10), a current flows through the cell (10) between the second conductive or semi-conductive layer (16) and a region of the semiconductor body (12), through the first insulating layer (14), with a value sufficiently high to damage the first insulating layer in a predetermined location within the central portion (“energetic holes (or hot holes as they are commonly called) are injected into the dielectric 14. It is known that hole injection into a dielectric such as S.sub.i O.sub.2 causes or accelerates the dielectric breakdown process”, col. 5, lines 57-61).
It would have been obvious to one of ordinary skill in the art before the time of the effective filing date of the invention to substitute the mask programming of Eitan for the fusible programming disclosed by Eltoukhy. The fusible programming method was known in the art and could have been employed in the device disclosed by Eitan with no change in the devices function, and the combination would have yielded the predictable result of programming the cell to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007) (MPEP 2141).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Eitan (US 6201282 B1) and Eltoukhy (US 5163180 A) in further view of Horch (US 10446562 B1).
Regarding claim 10, Eitan and Eltoukhy disclose the cell according to claim 6 as applied above, but Eitan and Eltoukhy fail to explicitly disclose wherein a dopant concentration of the second region is at least twice as much as a dopant concentration of the first region.
In the similar field of endeavor of memory devices, Fig. 2 of Horch discloses wherein a dopant concentration of the second region (Fig. 2, high doped region 155, col. 4, line 23) is at least twice (Fig. 2, “The high doped region 155 may have at least twice the doping concentration of the low doped region 150”, col. 5, lines 30-32) as much as a dopant concentration of the first region (Fig. 2, low doped region 150, col. 4, line 23).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the cell of Eitan with the doping concentrations as disclosed by Horch, to reduce drain leakage (see Horch, col. 4, lines 1-3).
Claims 12-13, 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Eitan (US 6201282 B1) and Eltoukhy (US 5163180 A) in further view of Yoshikawa (US 20030034518 A1).
Regarding claim 12, Eitan and Eltoukhy disclose the cell according to claim 6 as applied above, but Eitan and Eltoukhy fail to explicitly disclose wherein the semiconductor body further comprises a third region, wherein the third region is more heavily doped than the second region, wherein the third region surrounds the second region, and wherein the third region comprises at least a portion that is not covered with the first insulating layer.
In the similar field of endeavor of semiconductor memory devices, Fig. 5A of Yoshikawa discloses wherein the semiconductor body (Fig. 5A, semiconductor substrate 1, ¶ [0063]) further comprises a third region (Fig. 5A, diffusion layer 11, ¶ [0063]), wherein the third region (11) is more heavily doped than the second region (Fig. 5A, diffusion layer 10, ¶ [0063]) (“n.sup.--type diffusion layer 10 of a low impurity concentration adjacent to a channel area and an n.sup.+-type diffusion layer 11 of a high impurity concentration”, ¶ [0075]), wherein the third region (11) surrounds the second region (10), and wherein the third region (11) comprises at least a portion that is not covered with the first insulating layer (Fig. 5A, first gate insulation film 13, ¶ [0075]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the cell of Eitan with the doping as disclosed by Yoshikawa, to improve the breakdown voltages (see Yoshikawa, ¶ [0077]).
Regarding claim 13, Eitan, Eltoukhy and Yoshikawa together disclose the cell according to claim 12 as applied above, but Eitan fails to disclose further comprising at least one conductive contact in direct contact with the third region.
In the similar field of endeavor of semiconductor memory devices, Fig. 5A of Yoshikawa discloses further comprising at least one conductive contact (Fig. 5A, conductive layers 12, ¶ [0063]) in direct contact with the third region (11).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the cell of Eitan with the conductive contact as disclosed by Yoshikawa, to electrically connect the device (see Yoshikawa, ¶ [0063]).
Regarding claim 16, Figs. 2 and 7 of Eitan disclose a cell comprising:
a semiconductor body (18) comprising an upper surface, a lower surface, a side surface, two first doped regions (50) and two second doped regions (16);
a first insulating layer (20) arranged directly on the semiconductor body (18), the first insulating layer (20) comprising a peripheral portion (20b) and a central portion (20a); and
a second conductive or semi-conductive layer (22) arranged directly on the first insulating layer (20),
wherein the peripheral portion (20b) has a greater thickness than the central portion (20a),
wherein the peripheral portion (20b) is in direct contact with the first (50) and second doped regions (16),
wherein the central portion (20a) is in direct contact with the semiconductor body (18) and the second doped regions (16) but not with the first doped regions (50), and
wherein the cell (10) is a programmable read-only memory (“mask programmable, dual bit array”, col. 2, line 67).
Eitan fails to disclose wherein each of the first doped regions extends more from the upper surface to the lower surface than each of the second doped regions, and wherein the first doped regions are closer to the side surface than the second doped regions, and
wherein, during a programming of the cell, a current flows through the cell between the second conductive or semi-conductive layer and a region of the semiconductor body, through the first insulating layer, with a value sufficiently high to damage the first insulating layer in a predetermined location within the central portion.
In the similar field of endeavor of semiconductor memory devices, Fig. 5A of Yoshikawa discloses wherein each of the first doped regions (11) extends more from the upper surface to the lower surface than each of the second doped regions (10), and wherein the first doped regions (11) are closer to the side surface than the second doped regions (10).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the cell of Eitan with the doped regions as disclosed by Yoshikawa, to improve the breakdown voltages (see Yoshikawa, ¶ [0077]).
Yoshikawa fails to disclose wherein, during a programming of the cell, a current flows through the cell between the second conductive or semi-conductive layer and a region of the semiconductor body, through the first insulating layer, with a value sufficiently high to damage the first insulating layer in a predetermined location within the central portion.
In the similar field of endeavor of programmable read only memory devices, Fig. 1 of Eltoukhy discloses wherein, during a programming of the cell (10), a current flows through the cell (10) between the second conductive or semi-conductive layer (16) and a region of the semiconductor body (12), through the first insulating layer (14), with a value sufficiently high to damage the first insulating layer in a predetermined location within the central portion (“energetic holes (or hot holes as they are commonly called) are injected into the dielectric 14. It is known that hole injection into a dielectric such as S.sub.i O.sub.2 causes or accelerates the dielectric breakdown process”, col. 5, lines 57-61).
It would have been obvious to one of ordinary skill in the art before the time of the effective filing date of the invention to substitute the mask programming of Eitan for the fusible programming disclosed by Eltoukhy. The fusible programming method was known in the art and could have been employed in the device disclosed by Eitan with no change in the devices function, and the combination would have yielded the predictable result of programming the cell to one of ordinary skill in the art at the time of the invention. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007) (MPEP 2141).
Regarding claim 17, Eitan, Eltoukhy and Yoshikawa together disclose the cell according to claim 16 as applied above, and Fig. 7 of Eitan further discloses wherein a thickness of the central portion (20a) is substantially constant, and wherein a thickness of the peripheral portion (20b) is substantially constant.
Regarding claim 19, Eitan, Eltoukhy and Yoshikawa together disclose the cell according to claim 16 as applied above, and Fig. 7 of Eitan further discloses wherein a ratio between a width of the peripheral portion (20b) and a width of the central portion (20a) is greater than or equal to 2 (“the gate oxide layer 20 is 2-3 times thicker over the bit lines 16”, col. 7, lines 9-10).
Regarding claim 20, Eitan, Eltoukhy and Yoshikawa together disclose the cell according to claim 16 as applied above, but Eitan and Eltoukhy fail to disclose further comprising:
a spacer arranged on the first doped regions and covering side surfaces of the first and second conductive or semi-conductive layers;
first vias directly contacting the first doped regions; and
a second via directly contacting the second conductive or semi-conductive layer.
In the similar field of endeavor of semiconductor memory devices, Fig. 5A of Yoshikawa discloses a spacer (Fig. 5A, side wall spacer 9, ¶ [0063]) arranged on the first doped regions (11) and covering side surfaces of the first (13) and second conductive or semi-conductive layers (Fig. 5A, first gate electrode 3, ¶ [0063]);
first vias (12) directly contacting the first regions (11); and
a second via (12) directly contacting the second conductive or semi-conductive layer (3).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the cell of Eitan with the spacer and vias regions as disclosed by Yoshikawa, to electrically connect the device and improve charge retention (see Yoshikawa, ¶ [0063] and [0246]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Eitan (US 6201282 B1), Eltoukhy (US 5163180 A) and Yoshikawa (US 20030034518 A1) in view of Sakii (US 20210083214 A1).
Regarding claim 18, Eitan, Eltoukhy and Yoshikawa together disclose the cell according to claim 16 as applied above, but the combination fails to disclose wherein a thickness of the central portion is at least equal to 0.5 µm.
In the similar field of endeavor of field-effect transistors, Fig. 1 of Sakii discloses wherein a thickness of the central portion (3) is at least equal to 0.5 µm. (Fig. 1, “the thickness of the gate insulating layer is preferably 1000 nm or less”, ¶ [0112]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the cell of Eitan with the gate insulating layer as disclosed by Sakii, to decrease leak current (see Sakii, ¶ [0112]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893