DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendments have been entered. Claims 1-10, 12-18, and 20-22 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 20160322481 A1) hereinafter “Chan” in view of Jain et al. (US 20230064512 A1) hereinafter “Jain” and Malinowski et al. (US 20230275083 A1) hereinafter “Malinowski”.
Regarding Claim 1, Figure 8 of Chan teaches: A method (Paragraph 0021), comprising: forming a dielectric layer (2) on a substrate (1); forming a superlattice structure (12) on the dielectric layer; implanting selected regions (Paragraph 0049) of the superlattice structure with dopants to form emitter (13), base (middle region of the superlattice; Paragraph 0049), and collector regions (14) of a bipolar junction transistor (BJT) (Paragraph 0045); wherein implanting the selected regions comprises forming the base region between the emitter and collector regions (Figure 8)
Chan does not teach: forming the base region separated from the emitter and collector regions
Figure 11 of Jain teaches: a lateral bipolar transistor structure (160) comprising an emitter region (130a), a base region (150), and collector region (130b), wherein the base region is formed between and separated (via region 120) from the emitter and collector regions
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have forming the base region separated from the emitter and collector regions because Jain teaches separating structures are formed to electrically and physically insulate from other components (Jain Paragraph 0037).
Chan does not teach: forming a metallization structure on the emitter, base, and collector regions of the BJT.
Figure 1C of Malinowski teaches: a BJT (120) with an emitter region (121), a base region (126/127), a collector region (122), and a metallization structure (176) on the emitter, base, and collector regions of the BJT
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a metallization structure formed on the emitter, base, and collector regions of the BJT because Malinowski teaches middle of the line processing is formed on BJT regions to act as contacts to the terminals of the BJTs (Malinowski Paragraph 0074).
Regarding Claim 2, Figure 8 of Chan teaches: forming the superlattice structure (12) comprises forming alternating stacked layers of silicon (Si) and silicon germanium (SiGe) (Paragraph 0021).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 20160322481 A1) hereinafter “Chan” in view of Jain et al. (US 20230064512 A1) hereinafter “Jain,” Malinowski et al. (US 20230275083 A1) hereinafter “Malinowski” and Isobe et al. (US 20210111172 A1) hereinafter “Isobe.”
Regarding Claim 3, the combination of Chan, Jain, and Malinowski teaches all of the limitations of the claimed invention as stated above.
Chan does not teach: implanting selected other regions of the superlattice structure with dopants at a lower dose than that of dopants in the emitter, base, and collector regions of the BJT.
Figure 5 of Isobe teaches: a BJT (Paragraph 0001) with an emitter (217), a base (216), and a collector (214), and wherein selected other regions (215; N-well) are implanted with dopants at a lower dose (Paragraph 0082) than that of dopants in the emitter, base, and collector regions
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implant selected other regions of the superlattice structure with dopants at a lower dose than that of dopants in the emitter, base, and collector regions of the BJT because Isobe teaches wells are used in BJTs to prevent static electricity from flowing into the circuit (Isobe Paragraph 0050).
Regarding Claim 4, the combination of Chan, Jain, and Malinowski teaches all of the limitations of the claimed invention as stated above.
Chan does not teach: implanting the selected other regions comprises implanting an n-well surrounding the BJT.
Figure 5 of Isobe teaches: a BJT (Paragraph 0001) with an emitter (217), a base (216), and a collector (214), and wherein selected other regions (215; N-well) are implanted as an N-well
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that implanting the selected other regions comprises implanting an n-well surrounding the BJT because Isobe teaches wells are used in BJTs to prevent static electricity from flowing into the circuit (Isobe Paragraph 0050).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 20160322481 A1) hereinafter “Chan” in view of Jain et al. (US 20230064512 A1) hereinafter “Jain,” Malinowski et al. (US 20230275083 A1) hereinafter “Malinowski,” and Chiu et al. (US 20240128262 A1) hereinafter “Chiu.”
Regarding Claim 9, the combination of Chan, Jain, and Malinowski teaches all of the limitations of the claimed invention as stated above.
Chan does not teach: forming the metallization structure comprises forming at least one back side metal layer and at least one front side metal layer.
Figure 3 of Chiu teaches: lateral BJT devices (BJT1 and BJT2) with a metallization structure that comprises forming at least one back side metal layer (166 and 162) and at least one front side metal layer (110, 120, and 130)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have forming the metallization structure comprises forming at least one back side metal layer and at least one front side metal layer because Chiu teaches back-side power technology is used to decrease front-side routing, so as to decrease back end of line (BEOL) capacitance and IR drop, thereby improving performance of IC (Chiu Paragraph 0015).
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 20160322481 A1) hereinafter “Chan” in view of Jain et al. (US 20230064512 A1) hereinafter “Jain,” Malinowski et al. (US 20230275083 A1) hereinafter “Malinowski,” Isobe et al. (US 20210111172 A1) hereinafter “Isobe,” and Wang et al. (US 20210273061 A1) hereinafter “Wang”.
Regarding Claim 10, Figure 8 of Chan teaches: A method (Paragraph 0020), comprising: forming a dielectric layer (2) on a substrate (1); forming a superlattice structure (12) on the dielectric layer implanting second and third regions (Paragraph 0049) of the superlattice structure with a second dose of dopants to form emitter (13), base (middle region of the superlattice; Paragraph 0049), and collector terminals (14).
Chan does not teach: implanting a first region of the superlattice structure with a first dose of dopants to form a well; wherein the second dose is higher than the first dose
Figure 5 of Isobe teaches: a BJT (Paragraph 0001) with an emitter (217), a base (216), and a collector (214), and wherein selected other regions (215; N-well) are implanted with dopants at a lower dose (Paragraph 0082) than that of dopants in the emitter, base, and collector regions to form wells
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implant selected other regions of the superlattice structure with dopants at a lower dose than that of dopants in the emitter, base, and collector regions of the BJT to form wells because Isobe teaches wells are used in BJTs to prevent static electricity from flowing into the circuit (Isobe Paragraph 0050).
Chan does not teach: a pair of bipolar junction transistors (BJTs)
Figure 30 of Wang teaches: a Pair of bipolar junction transistors (BJTs; Fig. 30) formed adjacent to each other
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a pair of bipolar junction transistors (BJTs) because Wang teaches the formation of both BJT devices on a single chip can reduce the power requirements of a system-on-chip device (Wang Paragraph 0003).
Chan does not teach: wherein the first region is separated from the second and third regions
Figure 11 of Jain teaches: a lateral bipolar transistor structure (160) comprising an emitter region (130a), a base region (150), and collector region (130b), wherein the base region is formed between and separated (via region 120) from the emitter and collector regions
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the first region is separated from the second and third regions because Jain teaches separating structures are formed to electrically and physically insulate from other components (Jain Paragraph 0037).
Chan does not teach: forming a metallization structure on the emitter, base, and collector regions of the BJT.
Chan does not teach: forming a metallization structure on the emitter, base, and collector terminals of the pair of BJTs.
Figure 1C of Malinowski teaches: a BJT (120) with an emitter region (121), a base region (126/127), a collector region (122), and a metallization structure (176) on the emitter, base, and collector regions of the BJT
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a metallization structure formed on the emitter, base, and collector regions of the BJT because Malinowski teaches middle of the line processing is formed on BJT regions to act as contacts to the terminals of the BJTs (Malinowski Paragraph 0074).
Regarding Claim 12, the combination of Chan, Jain, Isobe, Malinowski, and Wang teaches all of the limitations of the claimed invention as stated above.
Figure 8 of Chan teaches: implanting the second and third regions comprises implanting the emitter (13) and collector (14) terminals with p-type dopants (Paragraph 0049).
The combination of adjacent connected BJTs of Wang with the structure of Chan will yield a structure such that the pair of BJTs are two P - N - P transistors.
Regarding Claim 13, the combination of Chan, Jain, Isobe, Malinowski, and Wang teaches all of the limitations of the claimed invention as stated above.
Figure 8 of Chan teaches: implanting the second and third regions comprises implanting the emitter (13) and collector (14) terminals with n-type dopants (Paragraph 0049).
The combination of adjacent connected BJTs of Wang with the structure of Chan will yield a structure such that the pair of BJTs are two N - P - N transistors.
Regarding Claim 22, the combination of Chan, Jain, Isobe, Malinowski, and Wang teaches all of the limitations of the claimed invention as stated above.
Chan does not teach: implanting the second and third regions comprises forming the emitter, base, and collector terminals on separated sections of the superlattice structure.
The combination of the structure of Chan with the separation structures of Jain, will yield a structure such that implanting the second and third regions comprises forming the emitter, base, and collector terminals on separated sections of the superlattice structure.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 20160322481 A1) hereinafter “Chan” in view of Jain et al. (US 20230064512 A1) hereinafter “Jain,” Malinowski et al. (US 20230275083 A1) hereinafter “Malinowski,” Isobe et al. (US 20210111172 A1) hereinafter “Isobe,” Wang et al. (US 20210273061 A1) hereinafter “Wang,” and Hekmatshoartabari et al. (US 20230123050 A1) hereinafter “Hekmatshoartabari.”
Regarding Claim 14, the combination of Chan, Jain, Isobe, Malinowski, and Wang teaches all of the limitations of the claimed invention as stated above.
Chan does not teach: forming the metallization structure comprises electrically connecting the pair of BJTs are in a Darlington circuit configuration.
Figure 44 of Hekmatshoartabari teaches: a dual BJT device (Paragraph 0222) connected in a Darlington circuit configuration (Paragraph 0072).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have forming the metallization structure comprises electrically connecting the pair of BJTs are in a Darlington circuit configuration because Hekmatshoartabari teaches Darlington circuit configurations enables= dense and area-efficient integration with semiconductor circuitry, using standard semiconductor processing methods (Hekmatshoartabari Paragraph 0077).
Claims 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 20160322481 A1) hereinafter “Chan” in view of Hobbs et al. (US 20160184821 A1) hereinafter “Hobbs,” Wang et al. (US 20210273061 A1) hereinafter “Wang,” and Ikeuchi (US 20220291707 A1) hereinafter “Ikeuchi.”
Regarding Claim 15, Figure 8 of Chan teaches: a first bipolar junction transistor (BJT) (Paragraph 0021) formed on a superlattice structure (12), the first BJT comprises a first base (middle region of the superlattice; Paragraph 0049), a first emitter (13), and a first collector (14);
Chan does not teach: a second BJT, wherein the second BJT having a second base, a second emitter, and a second collector.
Figure 30 of Wang teaches: a Pair of bipolar junction transistors (BJTs; Fig. 30) formed adjacent to each other
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a pair of bipolar junction transistors (BJTs) because Wang teaches the formation of both BJT devices on a single chip can reduce the power requirements of a system-on-chip device (Wang Paragraph 0003).
The combination of dual bipolar junction transistors as taught by Wang, with the structure of Chan will yield a structure such that the second BJT is formed on the superlattice structure and wherein the second BJT has a second base, a second emitter, and a second collector.
Chan does not teach: the second BJT is separated from the first BJT
Figure 3A of Hobbs teaches: a first BJT (leftmost combination of 220, 230, and 240) and a second BJT (rightmost combination of 220, 230, and 240) are separated (Via item 212)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second BJT is separated from the first BJT because Hobbs teaches an electrically insulating barrier can be utilized to physically and electrically separate transistor structures (Hobbs Paragraph 0058).
Chan does not teach: A circuit; and wherein the first emitter is electrically coupled to the second base, and the first and second collectors are electrically coupled to one another.
Figure 1 of Ikeuchi teaches: a Darlington pair circuit (10A; Paragraph 0022) comprising a first BJT (11) and a second BJT (12) wherein the first emitter is electrically coupled to the second base (Figure 1), and the first and second collectors are electrically coupled to one another (Paragraph 0022; Figure 1).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a circuit; and wherein the first emitter is electrically coupled to the second base, and the first and second collectors are electrically coupled to one another because Ikeuchi teaches a circuit configuration that includes a Darlington pair of BJTs reduces an influence of base resistance (Ikeuchi Paragraph 0029).
Regarding Claim 16, Figure 8 of Chan teaches: the superlattice structure (12) comprises an alternating stack of silicon (Si) and silicon germanium (SiGe) layers (Paragraph 0021).
Regarding Claim 17, the combination of Chan, Hobbs, Wang, and Ikeuchi teaches all of the limitations of the claimed invention as stated above.
Figure 8 of Chan teaches: the first BJT is a P - N - P type BJT (Paragraph 0049).
The combination of adjacent connected BJTs of Wang with the structure of Chan will yield a structure such that the pair of BJTs are two P - N - P transistors.
Regarding Claim 18, the combination of Chan, Hobbs, Wang, and Ikeuchi teaches all of the limitations of the claimed invention as stated above.
Figure 8 of Chan teaches the first BJT is a N - P - N type BJT (Paragraph 0049).
The combination of adjacent connected BJTs of Wang with the structure of Chan will yield a structure such that the pair of BJTs are two N - P - N transistors
Regarding Claim 20, the combination of Chan, Hobbs, Wang, and Ikeuchi teaches all of the limitations of the claimed invention as stated above.
Figure 8 of Chan teaches: the emitter (13), base (12), and collector (14) regions of the first BJT are within the superlattice structure (12).
The combination of adjacent connected BJTs of Wang with the structure of Chan will yield a structure such that the emitter, base, and collector regions of the second BJT are within the superlattice structure.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 20160322481 A1) hereinafter “Chan” in view of Hobbs et al. (US 20160184821 A1) hereinafter “Hobbs,” Wang et al. (US 20210273061 A1) hereinafter “Wang,” Ikeuchi (US 20220291707 A1) hereinafter “Ikeuchi,” and Isobe et al. (US 20210111172 A1) hereinafter “Isobe.”
Regarding Claim 21, the combination of Chan, Hobbs, Wang, and Ikeuchi teaches all of the limitations of the claimed invention as stated above.
Chan does not teach: a doped well in the superlattice structure and between the first and second BJTs, wherein the doped well is separated from the first and second BJTs.
Figure 8A/B of Isobe teaches: implanting select regions to create doped wells (NWL and PWL) between adjacent BJTs (Figure 8B)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to a doped well in the superlattice structure and between the first and second BJTs, wherein the doped well is separated from the first and second BJTs because Isobe teaches wells are used in BJTs to prevent static electricity from flowing into the circuit (Isobe Paragraph 0050).
The combination of the superlattice structure of Chan, with the isolation regions of Hobbs and the doped wells of Isobe, will yield a structure such that a doped well is in the superlattice structure and between the first and second BJTs, wherein the doped well is separated from the first and second BJTs.
Allowable Subject Matter
Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 5, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have implanting the selected regions comprises implanting the selected regions of the superlattice structure with the dopants to form the emitter, base, and collector regions according to a width ratio of about 5 : 1 : 5 along with all the other limitations of Claim 1.
Regarding Claim 6, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have implanting the selected regions comprises implanting the selected regions of the superlattice structure with the dopants to form the emitter, base, and collector regions according to a width ratio of about 1 :5:1 along with all the other limitations of Claim 1.
Regarding Claim 7, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have implanting the selected regions comprises forming undoped regions between terminals of the BJT that are about half as wide as doped regions corresponding to the emitter and collector regions along with all the other limitations of Claim 1.
Regarding Claim 8, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have implanting the selected regions comprises implanting the superlattice structure with n-type dopants and p-type-dopants to form n-type regions that are wider than p-type regions along with all the other limitations of Claim 1.
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed 12/31/2025, with respect to the rejection of Claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chan, Jain and Malinowski.
Applicant’s arguments, see Applicant’s Remarks, filed 12/31/2025, with respect to the rejection of Claim 10 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chan, Jain, Malinowski, Isobe, and Wang.
Applicant’s arguments, see Applicant’s Remarks, filed 12/31/2025, with respect to the rejection of Claim 15 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chan, Hobbs, Wang, and Ikeuchi.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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