DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 3, claims 1-5, 8-12 and 21-30, in the reply filed on September 24, 2025 is acknowledged. However, after inspection, the Examiner notes due to the claims associated, the election is really Group II, Species 3, claims 1-5, 8-12 and 21-30. Claims 6, 7, and 13-20 have cancelled by the Applicant. Action on the merits is as follow:
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-5, 8-12, 21-26 and 28-30 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-14 of copending Application No. 19/290,450 (published as US 2025/0364437 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because:
In regards to claim 1, 19/290,450 (claim 1) discloses a method, comprising: forming a device layer on a first substrate; forming an interconnect layer on the device layer; forming an oxide structure on a top surface and along a sidewall surface of the interconnect layer; forming a bonding layer on the oxide structure and the interconnect layer; and bonding the device layer to a second substrate with the bonding layer.
In regards to claim 2, 19/290,450 (claims 3, 9) discloses further comprising trimming edge portions of the first substrate, the device layer, the interconnect layer, and the oxide structure.
In regards to claim 3, 19/290,450 (claims 5, 9, 10) discloses forming a protection layer on the first substrate, the second substrate, and sidewalls of the device layer, the oxide structure, and the interconnect layer; removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer.
In regards to claim 4, 19/290,450 (claim 7, 11) discloses forming an additional oxide structure on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 5, 19/290,450 (claims 6, 7, 13) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
In regards to claim 8, 19/290,450 (claims 8, 14) discloses forming an additional interconnect layer on the top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure
In regards to claim 9, 19/290,450 (claims 1, 3, 9) discloses a method, comprising: forming an oxide structure on a first substrate, wherein the first substrate comprises a device layer and an interconnect layer on the device layer, and wherein the oxide structure is on top and sidewall surfaces of the interconnect layer; bonding the first substrate to a second substrate with a bonding layer; trimming edge portions of the first substrate, the device layer, the oxide structure. and the interconnect layer; and forming a protection layer on the first substrate, the second substrate, and sidewalls of the device layer, the oxide structure, and the interconnect layer.
In regards to claim 10, 19/290,450 (claims 5, 10) discloses removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer.
In regards to claim 11, 19/290,450 (claims 6, 7, 13) discloses co-planarizing top surfaces of the device layer, the protection layer, and the oxide layer.
In regards to claim 12, 19/290,450 (claims 8, 14) discloses forming an additional interconnect layer on the top surfaces of the device layer, the protection layer, and the oxide layer.
In regards to claim 21, 19/290,450 (claims 2) discloses wherein forming the oxide structure comprises: covering a center region of the first substrate with a plate; and depositing an oxide material on the interconnect layer at the edge region of the first substrate.
In regards to claim 22, 19/290,450 (claims 7, 11, 12) discloses forming an additional oxide structure on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 23, 19/290,450 (claims 7, 12) discloses wherein forming the additional oxide structure comprises: covering a center region of the first substrate with a plate; and depositing an oxide material on the oxide layer at the edge region of the first substrate.
In regards to claim 24, 19/290,450 (claims 6, 7, 13) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
In regards to claim 25, 19/290,450 (claims 1, 3, 9) discloses a method, comprising: forming a device wafer comprising a device layer on a first substrate and an interconnect layer on the device layer; forming an oxide structure on an edge region of the device wafer, wherein the oxide structure covers a portion of top and sidewall surfaces of the interconnect layer; forming a bonding layer on the oxide structure and the interconnect layer; bonding the device wafer to a second substrate with the bonding layer; and trimming edge portions of the first substrate, the device layer, the interconnect layer, and the oxide structure.
In regards to claim 26, 19/290,450 (claim 2) discloses wherein forming the oxide structure comprises- covering a center region of the device wafer with a plate; and depositing an oxide material on the interconnect layer at the edge region of the device wafer.
In regards to claim 28, 19/290,450 (claims 5, 9, 10) discloses forming a protection layer on the first substrate, the second substrate, and sidewalls of the device layer, the oxide structure, and the interconnect layer; removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer
In regards to claim 29, 19/290,450 (claims 5, 9, 10) discloses forming an additional oxide structure on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 30, 19/290,450 (claims 6, 7, 13) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-12, 21-26 and 28-30 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sung et al. (Sung) (US 2023/0178446 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In regards to claim 1, Sung (Figs. 1-9 and associated text) discloses a method, comprising: forming a device layer (item 40) on a first substrate (items 22 or 32); forming an interconnect layer (items 52 plus 50 or 34) on the device layer (item 40); forming an oxide structure (items 62A, 62B or 62) on a top surface and along a sidewall surface of the interconnect layer (item 34); forming a bonding layer (item 54) on the oxide structure (items 62A, 62B or 62) and the interconnect layer (items 52 plus 50 or 34); and bonding the device layer (item 40) to a second substrate (items 22 or 32) with the bonding layer (items 54). Examiner notes that the Applicant has not given any criticality to the order.
In regards to claim 2, Sung (Figs. 1-9 and associated text) discloses further comprising trimming edge portions of the first substrate (items 22 or 32), the device layer (item 40), the interconnect layer (items 52 plus 50 or 34), and the oxide structure (items 62A, 62B or 62).
In regards to claim 3, Sung (Figs. 1-9 and associated text) discloses forming a protection layer (item 64) on the first substrate (items 22 or 32), the second substrate (items 22 or 32), and sidewalls of the device layer (item 40), the oxide structure (items 62A, 62B or 62), and the interconnect layer (items 52 plus 50 or 34); removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer.
In regards to claim 4, Sung (Figs. 1-9 and associated text) discloses forming an additional oxide structure (item 72) on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 5, Sung (Figs. 1-9 and associated text) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
In regards to claim 8, Sung (Figs. 1-9 and associated text) discloses forming an additional interconnect layer on the top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure
In regards to claim 9, Sung (Figs. 1-9 and associated text and items) discloses a method, comprising: forming an oxide structure (items 62A, 62B or 62) on a first substrate (item 30), wherein the first substrate (item 30) comprises a device layer (items 40) and an interconnect layer (items 52 plus 50 or 34) on the device layer (item 40), and wherein the oxide structure (items 62A, 62B or 62) is on top and sidewall surfaces of the interconnect layer; bonding the first substrate (item 32) to a second substrate (item 22) with a bonding layer (items 24 or 54); trimming edge portions of the first substrate (item 32), the device layer (item 40), the oxide structure (items 62A, 62B or 62), and the interconnect layer (items 52 plus 50 or 34); and forming a protection layer (item 64) on the first substrate (item 32), the second substrate (item 22), and sidewalls of the device layer (item 40), the oxide structure items 62A, 62B or 62), and the interconnect layer (items 52 plus 50 or 34).
In regards to claim 10, Sung (Figs. 1-9 and associated text and items) discloses removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer.
In regards to claim 11, Sung (Figs. 1-9 and associated text and items) discloses co-planarizing top surfaces of the device layer, the protection layer, and the oxide layer.
In regards to claim 12, Sung (Figs. 1-9 and associated text and items) discloses forming an additional interconnect layer on the top surfaces of the device layer, the protection layer, and the oxide layer.
In regards to claim 21, Sung (Figs. 1-9 and associated text and items) discloses wherein forming the oxide structure comprises: covering a center region of the first substrate with a plate; and depositing an oxide material on the interconnect layer at the edge region of the first substrate.
In regards to claim 22, Sung (Figs. 1-9 and associated text and items) discloses forming an additional oxide structure on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 23, Sung (Figs. 1-9 and associated text and items) discloses wherein forming the additional oxide structure comprises: covering a center region of the first substrate with a plate; and depositing an oxide material on the oxide layer at the edge region of the first substrate.
In regards to claim 24, Sung (Figs. 1-9 and associated text and items) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
In regards to claim 25, Sung (Figs. 1-9 and associated text and items) discloses a method, comprising: forming a device wafer comprising a device layer on a first substrate and an interconnect layer on the device layer; forming an oxide structure on an edge region of the device wafer, wherein the oxide structure covers a portion of top and sidewall surfaces of the interconnect layer; forming a bonding layer on the oxide structure and the interconnect layer; bonding the device wafer to a second substrate with the bonding layer; and trimming edge portions of the first substrate, the device layer, the interconnect layer, and the oxide structure.
In regards to claim 26, Sung (Figs. 1-9 and associated text and items) discloses wherein forming the oxide structure comprises- covering a center region of the device wafer with a plate; and depositing an oxide material on the interconnect layer at the edge region of the device wafer.
In regards to claim 28, Sung (Figs. 1-9 and associated text and items) discloses forming a protection layer on the first substrate, the second substrate, and sidewalls of the device layer, the oxide structure, and the interconnect layer; removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer
In regards to claim 29, Sung (Figs. 1-9 and associated text and items) discloses forming an additional oxide structure on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 30, Sung (Figs. 1-9 and associated text and items) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
Allowable Subject Matter
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 February 11, 2026