DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed June 25, 2026 have been fully considered but they are not persuasive. Applicant has failed to file a proper terminal disclaimer, therefore the nonstatutory doubled patenting rejection is maintained.
Applicant’s arguments, see pages 6-7, filed June 25, 2026, with respect to the rejection(s) of claim(s) 1-5, 8-12, 21-26 and 28-30 under 35. U.S.C. § 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further search and consideration, a new ground(s) of rejection is made in view of Li et al. (Li) (US 2020/0006145 A1).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “covering a center region of the first substrate with a plate” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-5, 8-12, 21-26 and 28-30 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-14 of copending Application No. 19/290,450 (published as US 2025/0364437 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because:
In regards to claim 1, 19/290,450 (claim 1) discloses a method, comprising: forming a device layer on a first substrate; forming an interconnect layer on the device layer; forming an oxide structure on a top surface and along a sidewall surface of the interconnect layer; forming a bonding layer on the oxide structure and the interconnect layer; and bonding the device layer to a second substrate with the bonding layer.
In regards to claim 2, 19/290,450 (claims 3, 9) discloses further comprising trimming edge portions of the first substrate, the device layer, the interconnect layer, and the oxide structure.
In regards to claim 3, 19/290,450 (claims 5, 9, 10) discloses forming a protection layer on the first substrate, the second substrate, and sidewalls of the device layer, the oxide structure, and the interconnect layer; removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer.
In regards to claim 4, 19/290,450 (claim 7, 11) discloses forming an additional oxide structure on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 5, 19/290,450 (claims 6, 7, 13) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
In regards to claim 8, 19/290,450 (claims 8, 14) discloses forming an additional interconnect layer on the top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure
In regards to claim 9, 19/290,450 (claims 1, 3, 9) discloses a method, comprising: forming an oxide structure on a first substrate, wherein the first substrate comprises a device layer and an interconnect layer on the device layer, and wherein the oxide structure is on top and sidewall surfaces of the interconnect layer; bonding the first substrate to a second substrate with a bonding layer; trimming edge portions of the first substrate, the device layer, the oxide structure. and the interconnect layer; and forming a protection layer on the first substrate, the second substrate, and sidewalls of the device layer, the oxide structure, and the interconnect layer.
In regards to claim 10, 19/290,450 (claims 5, 10) discloses removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer.
In regards to claim 11, 19/290,450 (claims 6, 7, 13) discloses co-planarizing top surfaces of the device layer, the protection layer, and the oxide layer.
In regards to claim 12, 19/290,450 (claims 8, 14) discloses forming an additional interconnect layer on the top surfaces of the device layer, the protection layer, and the oxide layer.
In regards to claim 21, 19/290,450 (claims 2) discloses wherein forming the oxide structure comprises: covering a center region of the first substrate with a plate; and depositing an oxide material on the interconnect layer at the edge region of the first substrate.
In regards to claim 22, 19/290,450 (claims 7, 11, 12) discloses forming an additional oxide structure on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 23, 19/290,450 (claims 7, 12) discloses wherein forming the additional oxide structure comprises: covering a center region of the first substrate with a plate; and depositing an oxide material on the oxide layer at the edge region of the first substrate.
In regards to claim 24, 19/290,450 (claims 6, 7, 13) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
In regards to claim 25, 19/290,450 (claims 1, 3, 9) discloses a method, comprising: forming a device wafer comprising a device layer on a first substrate and an interconnect layer on the device layer; forming an oxide structure on an edge region of the device wafer, wherein the oxide structure covers a portion of top and sidewall surfaces of the interconnect layer; forming a bonding layer on the oxide structure and the interconnect layer; bonding the device wafer to a second substrate with the bonding layer; and trimming edge portions of the first substrate, the device layer, the interconnect layer, and the oxide structure.
In regards to claim 26, 19/290,450 (claim 2) discloses wherein forming the oxide structure comprises- covering a center region of the device wafer with a plate; and depositing an oxide material on the interconnect layer at the edge region of the device wafer.
In regards to claim 28, 19/290,450 (claims 5, 9, 10) discloses forming a protection layer on the first substrate, the second substrate, and sidewalls of the device layer, the oxide structure, and the interconnect layer; removing the first substrate to expose the device layer; and forming an oxide layer on the protection layer and the device layer
In regards to claim 29, 19/290,450 (claims 5, 9, 10) discloses forming an additional oxide structure on the oxide layer adjacent to the sidewalls of the device layer, the oxide structure, and the interconnect layer, wherein the additional oxide structure is in contact with a sidewall surface of the oxide layer.
In regards to claim 30, 19/290,450 (claims 6, 7, 13) discloses co-planarizing top surfaces of the device layer, the protection layer, the oxide layer, and the additional oxide structure.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 9, 25 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (Li) (US 2020/0006145 A1).
In regards to claim 1, Li (Figs. 3-7, 9A-9K, 11A-14J and associated text and equivalent items) discloses a method, comprising: forming a device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302) on a first substrate (items 102, 102a); forming an interconnect layer (items 316c plus 314) on the device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302); forming an oxide structure (items 318 or 318 plus 110) on a top surface and along a sidewall surface of the interconnect layer (items 316c plus 314); forming a bonding layer (items 320, 322, 324, 326, 320 plus 322, 320 plus 322 plus 324 or 320 plus 322 plus 324 plus 326) on the oxide structure (items 318 or 318 plus 110) and the interconnect layer (items 316c plus 314); and bonding the device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302) to a second substrate (items 102, 102b, 102c or 102d) with the bonding layer (items 320, 322, 324, 326, 320 plus 322, 320 plus 322 plus 324 or 320 plus 322 plus 324 plus 326). Examiner notes that the Applicant has not given any criticality to the order.
In regards to claim 2, Li (Figs. 3-7, 9A-9K, 11A-14J and associated text and equivalent items) discloses further comprising trimming edge portions of the first substrate (items 102, 102a), the device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302), the interconnect layer (items 316c plus 314), and the oxide structure (items 318 or 318 plus 110).
In regards to claim 9, Li (Figs. 3-7, 9A-9K, 11A-14J and associated text and equivalent items) discloses a method, comprising: forming an oxide structure (items 318 or 318 plus 110) on a first substrate (items 102/102a plus items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302 plus items 316c plus 314), wherein the first substrate (items 102/102a plus items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302 plus items 316c plus 314) comprises a device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302) and an interconnect layer (items 316c plus 314) on the device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302), and wherein the oxide structure (items 318 or 318 plus 110) is on top and sidewall surfaces of the interconnect layer (items 316c plus 314); bonding the first substrate (items 102, 102a) to a second substrate (item 102b, 102c, 102d) with a bonding layer (items 320, 322, 324, 326, 320 plus 322, 320 plus 322 plus 324 or 320 plus 322 plus 324 plus 326); trimming edge portions of the first substrate (item 102, 102a), the device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302), the oxide structure (items 318 or 318 plus 110), and the interconnect layer (items 316c plus 314); and forming a protection layer (item 118) on the first substrate (item 102, 102a), the second substrate (item 102b, 102c or 102d), and sidewalls of the device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302), the oxide structure (items 318 or 318 plus 110), and the interconnect layer (items 316c plus 314).
In regards to claim 25, Li (Figs. 3-7, 9A-9K, 11A-14J and associated text and equivalent items) discloses a method, comprising: forming a device wafer (items 102/102a plus items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302 plus items 316c plus 314) comprising a device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302) on a first substrate (items 102, 102a) and an interconnect layer (items 316c plus 314) on the device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302); forming an oxide structure (items 318 or 318 plus 110) on an edge region of the device wafer (items 102/102a plus items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302 plus items 316c plus 314), wherein the oxide structure (items 318 or 318 plus 110) covers a portion of top and sidewall surfaces of the interconnect layer (items 316c plus 314); forming a bonding layer (items 320, 322, 324, 326, 320 plus 322, 320 plus 322 plus 324 or 320 plus 322 plus 324 plus 326) on the oxide structure (items 318 or 318 plus 110) and the interconnect layer (items 316c plus 314); bonding the device wafer (items 102/102a plus items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302 plus items 316c plus 314) to a second substrate (items 102b, 102c or 102d) with the bonding layer (items 320, 322, 324, 326, 320 plus 322, 320 plus 322 plus 324 or 320 plus 322 plus 324 plus 326); and trimming edge portions of the first substrate (items 102, 102a), the device layer (items 316 plus 302, 316a plus 302, 316a plus 316b plus 302 or 316a plus 316b plus 316c plus 302), the interconnect layer (items 316c plus 314), and the oxide structure (items 318 or 318 plus 110).
In regards to claim 27, Li (Figs. 3-7, 9A-9K, 11A-14J and associated text and equivalent items) discloses planarizing (paragraph 92) the top surface of the bonding layer (items 320, 322, 324, 326, 320 plus 322, 320 plus 322 plus 324 or 320 plus 322 plus 324 plus 326) on the interconnect layer (items 316c plus 314), and the oxide structure (items 318 or 318 plus 110).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 July 21, 2026
Prosecution Insights