DETAILED ACTION
This correspondence is in response to the communications received 12/16/2025. Claim 22 has been added. Claims 1, 6-8, 16 and 20 have been amended. Claim 18 has been canceled. Claims 1-17 and 19-22 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/25/2025 and 12/16/2025 have been considered by the examiner and made of record in the application file.
Response to Amendment
Applicant’s amendments to claims 6 and 7 overcomes the objections outlined in the previous Office Action. The objections are withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1-15, 20 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 12/16/2025 regarding claim 16 have been fully considered but they are not persuasive. Applicant asserts that the prior art of Ishino et al. (US 9,240,371 B2) in combination with Bitz et al. (US 9,960,150 B2) fails to disclose or otherwise suggest “a cover including … a wall surrounding at least one of the plurality of protrusions; and
a grooved in the surface of the wall, a sealing mechanism being disposed in the groove.”
However, as seen in Fig. 15 of Ishino, “case 61” is a cover including walls surrounding “fins 60”. The walls of 61 are thus the outer vertical portions of 61 that laterally surround 60. Ishino does not disclose a groove, however, Bitz does teach a groove, “structural feature 159”, where “structural feature 159 is a sealing groove for accommodating a sealing member 156, embodied as O-ring”, col. 11, lines 34-36, where 156 is a sealing mechanism. As seen in Fig. 2 of Bitz, 159 is in the bottom surface of a wall similar to the wall of Ishino. Therefore, Ishino in combination with Bitz discloses the limitations of independent claim 16.
Claim Objections
Claim 16 is objected to because of the following informalities: Line 7 terminates with a comma, it appears a semicolon should be used instead. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Mamitsu et al. (US 8125781 B2) in view of Bitz et al. (US 9,960,150 B2).
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Regarding claim 1, Figs. 4 and 5A of Mamitsu disclose an apparatus (“semiconductor device 200”, col. 12, line 23), comprising:
a first module (together the left instances of “solder 41, 42”, col. 6, line 19, and “first semiconductor chip 11”, col. 6, line 16, as seen in Fig. 5A form a first module, hereinafter “FM”) including a first semiconductor die (11 is a “semiconductor chip”, see col. 1, lines 52-53, Mamitsu does not specify that 11 is semiconductor die, however a secondary reference will be utilized to teach this limitation below, the left instance of 11 as seen in Fig. 5A is hereinafter “11A”);
a first heatsink (“upper heat sink 30”, col. 12, line 31, specifically, the left instance of 30 denoted “30A” in Fig. 5A is a first heatsink) coupled to the first module (“the electrodes on the front surfaces of the first and second semiconductor chips 11, 12 are electrically connected to the upper heat sink 30”, col. 7, lines 28-30), the first heatsink including a substrate (the portion of 30 denoted “30SA” in Fig. 5A is a substrate), and a first plurality of protrusions (“fins 83a”, col. 12, line 38, specifically the instance of 83a denoted “83PA” seen in Fig. 5A is a first plurality of protrusions);
a second module (together the right instances of “solder 41, 42”, col. 6, line 19,and “first semiconductor chip 11”, col. 6, line 16, as seen in Fig. 5A form a second module, hereinafter “SM”) including a second semiconductor die (as discussed previously, 11 is a semiconductor chip, and a secondary reference will be used to teach a semiconductor die, and the right instance of 11 as seen in Fig. 5A is hereinafter “11B”);
a second heatsink (“lower heat sink 20”, col. 12, line 31, specifically, the right instance of 20 denoted “20B” in Fig. 5A is a second heatsink) coupled to the second module (“The electrodes on the rear surfaces of the first and second semiconductor chips 11, 12 are electrically connected to the lower heat sink 20”, col. 7, lines 25-27) and including a second plurality of protrusions (“fins 83a”, col. 12, line 38, specifically the instance of 83a denoted “83PB” seen in Fig. 5A is a second plurality of protrusions); and
a cover (“molded resin 50a”, col. 13, line 46, as seen in Fig. 5A, 50a forms a cover) defining a channel (as seen in Fig. 5A, 50a defines a channel between 30A and 20B), the first plurality of protrusions of the first heatsink and the second plurality of protrusions of the second heatsink being disposed within the channel (as seen in Fig. 5A, 83PA and 83PB are in the channel between 30A and 20B), the cover being in direct contact with the first module and the second module (as seen in Fig. 5A, 50a is in direct contact with FM and SM).
Figs. 4 and 5A of Mamitsu fail to disclose “a first semiconductor die; and
a second semiconductor die”.
However, in a similar field of endeavor, Bitz teaches a first module including a first semiconductor die (“packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased and in a plastic protective covering”, col. 1, lines 11-14, therefore 11 of Mamitsu are semiconductor dies, and 11A is a first semiconductor die); and
a second module including a second semiconductor die (as per above, 11B of Mamitsu is a second semiconductor die).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first semiconductor die; and
a second semiconductor die” as taught by Bitz in the system of Mamitsu for the purpose of defining what is included in the phrase “semiconductor dies”.
Regarding claim 2, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose wherein the cover includes an inlet opening and an outlet opening (“openings 53a”, one instance of 53a is an inlet opening, and the second instance of 53a is an outlet opening) in fluid communication with the inlet opening via the channel (“the openings 53a are used as a refrigerant path”, col. 8, lines 54-55).
Regarding claim 3, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose wherein
the cover is a first cover (50a is a first cover),
the channel is a first channel (the channel between 30A and 20B is a first channel),
the first cover and the first heatsink are on a first side of the first module (50a and the channel between 30A and 20B are on the right side of FM as seen in Fig. 5a),
the apparatus, further comprising:
a third heatsink (“lower heat sink 20”, specifically, the left instance of 20 denoted “20A” in Fig. 5A is a third heatsink) coupled to a second side of the first module (as seen in Fig. 5a, 20A is on the left side of FM).
Mamitsu does not directly disclose “the apparatus, further comprising:
a second cover including a second channel, the third heatsink being disposed within the second channel.”
However, Mamitsu does state “The semiconductor device 200 shown in FIGS. 4, 5A, 5B is also configured of a plurality of semiconductor modules 1 connected to each other” (col. 12, lines 44-46). Therefore, an additional semiconductor module 1 can be added to the left side of the stack shown in Fig. 5A as a plurality of semiconductor modules 1 is not limited to the two modules shown in Fig. 5A. Thus, Mamitsu teaches the apparatus, further comprising:
a second cover (the additional instance of 1 includes a new 50a, hereinafter “50a2” that is a second cover) including a second channel (the channel to the left of 20A and enclosed by 50a2 and the additional instance of 1 is a second channel), the third heatsink being disposed within the second channel (as described above, 20A is in the second channel).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the apparatus, further comprising:
a second cover including a second channel, the third heatsink being disposed within the second channel” as taught by Mamitsu in the system of Mamitsu in combination with Bitz for the purpose of including additional semiconductor modules and thus increasing the functionality of the semiconductor device.
Regarding claim 4, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 3, Figs. 4 and 5A of Mamitsu further disclose wherein the first cover is coupled to the second cover via a coupling mechanism disposed lateral to the first module (“Further, the connecting surface of the wall part [52] has a positioning concave or convex form, and therefore the wall parts (52) can be connected easily to each other. The wall parts [52] can be connected to each other by adhesive.”, col. 3, lines 49-53, where 50a comprises 52 as seen in Fig. 5A, thus the positioning concave or convex form of 52 together with adhesive are a coupling mechanism that is lateral to FM).
Regarding claim 5, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose wherein the first heatsink and the second heatsink are aligned along the channel (as seen in Fig. 5A, FM and SM are aligned along the channel between 30A and 20B).
Regarding claim 6, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose wherein the first plurality of protrusions includes at least one protrusion having an end separated from an inner surface of the cover by a gap (as seen in Fig. 5A, 83PA has at least one protrusion having an end separated from an inner surface of 50a by a gap).
Regarding claim 8, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose wherein the cover has a portion in direct contact with the first heatsink (as seen in Fig. 5A, 50a has a portion in direct contact with 30A).
Regarding claim 9, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose further comprising a sealing mechanism (“sealing part 51a”) in contact with the substrate of the first heatsink (as seen in Fig. 5A, 51a is in contact with 30SA).
Regarding claim 10, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 9, Figs. 4 and 5A of Mamitsu further disclose wherein the first module is aligned along a first plane (as seen in Fig. 5A, FM is aligned along the vertical plane), the sealing mechanism is aligned along a second plane (as seen in Fig. 5A, 51a is aligned along the horizontal plane), the sealing mechanism is disposed along a perimeter of the first module (as per Merriam-Webster, along is defined as “in a line matching the length or direction of”, thus as seen in Fig. 5A, 51a is disposed along a perimeter of FA, as 51a and the horizontal portion of the perimeter of FA are in a line with matching directions).
Regarding claim 11, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose further comprising:
a coupling mechanism coupling the cover to the substrate of the first heatsink (“the molded resin 50a is filled in the gap and on the outer periphery of the heat sinks 20, 30 by the transfer molding or potting.”, col. 9, lines 34-26, as per [0062] of the instant specification “coupling mechanisms 162 are configured to couple (e.g., fixedly couple) the cover 120 to the substrate 132”, therefore as 50a is fixedly coupled to 30 via a molding process, the molded fit is a coupling mechanism coupling 50a to 30SA)
Regarding claim 12, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose wherein the first heatsink includes a first metal and a second metal (Mamitsu states “The fins 83 are made, for example, of cooper or aluminium. The fins 83 can be formed with the heat sinks 20, 30 by integral molding in press working. Alternately, the fins 83 can be separately made and joined to the heat sinks 20, 30”, col. 12, lines 41-43, therefore 30 or more specifically 30SA, is a first metal that is joined with a second metal of 83PA).
Regarding claim 20, Figs. 4 and 5A of Mamitsu disclose an apparatus (“semiconductor device 200”), comprising:
a first module (together the left instances of “solder 41, 42”, col. 6, line 19, and “first semiconductor chip 11”, col. 6, line 16, as seen in Fig. 5A form a first module, hereinafter “FM”) including a first semiconductor die (11 is a “semiconductor chip”, see col. 1, lines 52-53, Mamitsu does not specify that 11 is semiconductor die, however a secondary reference will be utilized to teach this limitation below, the left instance of 11 as seen in Fig. 5A is hereinafter “11A”);
a first heatsink (“upper heat sink 30”, col. 12, line 31, specifically, the left instance of 30 denoted “30A” in Fig. 5A is a first heatsink) coupled to the first module (“the electrodes on the front surfaces of the first and second semiconductor chips 11, 12 are electrically connected to the upper heat sink 30”, col. 7, lines 28-30);
a second module (together the right instances of “solder 41, 42”, col. 6, line 19,and “first semiconductor chip 11”, col. 6, line 16, as seen in Fig. 5A form a second module, hereinafter “SM”) including a second semiconductor die (as discussed previously, 11 is a semiconductor chip, and a secondary reference will be used to teach a semiconductor die, and the right instance of 11 as seen in Fig. 5A is hereinafter “11B”)
a second heatsink (“lower heat sink 20”, col. 12, line 31, specifically, the right instance of 20 denoted “20B” in Fig. 5A is a second heatsink) coupled to the second module (“The electrodes on the rear surfaces of the first and second semiconductor chips 11, 12 are electrically connected to the lower heat sink 20”, col. 7, lines 25-27); and
a cover (“molded resin 50a”, col. 13, line 46, as seen in Fig. 5A, 50a forms a cover) defining a channel (as seen in Fig. 5A, 50a defines a channel between 30A and 20B) and coupled to in direct contact with a top surface of the first module and a top surface of the second module such that the first heatsink and the second heatsink are disposed in the channel.
Figs. 4 and 5A of Mamitsu fail to disclose “a first semiconductor die; and
a second semiconductor die”.
However, in a similar field of endeavor, Bitz teaches a first module including a first semiconductor die (“packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased and in a plastic protective covering”, col. 1, lines 11-14, therefore 11 of Mamitsu are semiconductor dies, and 11A is a first semiconductor die); and
a second module including a second semiconductor die (as per above, 11B of Mamitsu is a second semiconductor die).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first semiconductor die; and
a second semiconductor die” as taught by Bitz in the system of Mamitsu for the purpose of defining what is included in the phrase “semiconductor dies”.
Regarding claim 21, Figs. 4 and 5A of Mamitsu in combination with Bitz discloses the apparatus of claim 20, Figs. 4 and 5A of Mamitsu further disclose wherein the cover includes an inlet opening and an outlet opening (“openings 53a”, one instance of 53a is an inlet opening, and the second instance of 53a is an outlet opening) in fluid communication with the inlet opening via the channel (“the openings 53a are used as a refrigerant path”, col. 8, lines 54-55).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mamitsu et al. (US 8125781 B2) in view of Bitz et al. (US 9,960,150 B2) in view of Grassmann et al. (US 11,244,886 B2).
Regarding claim 13, Figs. 4 and 5A of Mamitsu in combination with Bitz disclose the apparatus of claim 1, Figs. 4 and 5A of Mamitsu further disclose wherein the first module is a dual-sided module (as seen in Fig. 5A, FM has a heat sink on two opposite surfaces, and is therefore a dual-sided module).
Figs. 4 and 5A of Mamitsu in combination with Bitz fail to disclose “wherein the first module is a dual-sided module including a direct bonded metal substrate.”
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However, in a similar field of endeavor, Fig. 2 of Grassmann teaches wherein the first module is a dual-sided module (together “electronic chips 102”, and “first heat removal body 108”, and “a second heat removal body 110 is thermally coupled to a second main surface of the electronic chips 102 via the spacer bodies 130” form a dual sided module equivalent to FM of Mamitsu) including a direct bonded metal substrate (“A first heat removal body 108, which is here embodied as Direct Copper Bonding (DCB) substrate”, col. 9, lines 55-56).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first module is a dual-sided module including a direct bonded metal substrate” as taught by Grassmann in the system of Mamitsu in combination with Bitz for the purpose of improving heat removal capabilities as “Direct Copper Bonding (DCB) substrate [are] used for removing heat from the encapsulated chip(s)” (col. 8, lines 34-35).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Mamitsu et al. (US 8125781 B2) in view of Bitz et al. (US 9,960,150 B2) in view of Grassmann et al. (US 11,244,886 B2) in view of Robert (US 8,804,339 B2).
Regarding claim 14, Figs. 4 and 5A of Mamitsu in combination with Bitz disclose the apparatus of claim 1.
Figs. 4 and 5A of Mamitsu in combination with Bitz fail to disclose “wherein the first module includes a direct bonded metal substrate in contact with the first semiconductor die, the direct bonded metal substrate includes a dielectric layer disposed between a pair of metal layers.”
However, in a similar field of endeavor, Fig. 2 of Grassmann teaches wherein the first module (together “electronic chips 102”, and “first heat removal body 108”, and “second heat removal body 110” form a first module equivalent to FM of Mamitsu) includes a direct bonded metal substrate (“A first heat removal body 108, which is here embodied as Direct Copper Bonding (DCB) substrate”, col. 9, lines 55-56) in contact with the first semiconductor die (“108, which is here embodied as Direct Copper Bonding (DCB) substrate, is thermally and mechanically coupled to a first main surface of the electronic chips 102”, col. 9, lines 55-58), the direct bonded metal substrate includes a dielectric layer disposed between a pair of metal layers (“The first heat removal body 108 comprises a central electrically insulating and thermally conductive layer 112, here made of ceramic material, having a first main surface covered by a first electrically conductive layer 114, which is here embodied as a copper layer, and having an opposing second main surface covered by a second electrically conductive layer 116”, col. 9, lines 65-67, col. 10, lines 1-4, 112 is not specifically a dielectric layer, however a secondary reference will be utilized for this limitation below).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first module includes a direct bonded metal substrate in contact with the first semiconductor die, the direct bonded metal substrate includes a dielectric layer disposed between a pair of metal layers” as taught by Grassmann in the system of Mamitsu in combination with Bitz for the purpose of improving heat removal capabilities as “Direct Copper Bonding (DCB) substrate [are] used for removing heat from the encapsulated chip(s)” (col. 8, lines 34-35).
Figs. 4 and 5A of Mamitsu in combination with Bitz and Fig. 2 of Grassmann fail to disclose “a dielectric layer.”
However, in a similar field of endeavor, Fig. 2C of Robert teaches a dielectric layer (“The dielectric layer 114 may be made of an electrically insulative, thermally conductive material such that there is no electrical connection between the first and second metal layers 112, 116. The dielectric layer 114 may comprise a ceramic material, such as alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), beryllium oxide (BeO), silicon carbide (SiC), and the like”, col. 3, lines 66-67 and col. 4, lines 1-5, therefore 112 of Grassmann can be a dielectric layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a dielectric layer” as taught by Robert in the system of Mamitsu in combination with Bitz and Grassmann for the purpose of providing specific dielectric ceramic materials.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ishino et al. (US 9,240,371 B2) in view of Bitz et al. (US 9,960,150 B2) in view of Grassmann et al. (US 11,244,886 B2).
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Regarding claim 16, Fig. 15 of Ishino discloses an apparatus (“semiconductor module 4”, col. 19, lines 66-67), comprising:
a first module (together “heat radiation substrates 12-13”, col. 11, line 27, “lead frame 9”, col. 8, line 41, the left half of “lead frame 10”, col. 8, line 56, as seen in Fig. 15, “joining materials 20, 23, 29, and 30”, col. 11, line 56, and “semiconductor chip 7a”, col. 7, line 60, form a first module, hereinafter “M1”)including a first semiconductor die (7a is a semiconductor chip, see col. 7, line 60, however a secondary reference will be utilized to teach this limitation below) coupled to a first substrate (12 is a first substrate, where “The heat radiation substrates 12-15 are joined to the surfaces of the lead frames 9-11 on the sides opposite to the semiconductor chips 7, 8”, col. 11, lines 29-31, specifically 7a is coupled to 12 via 9);
a second module (together “heat radiation substrates 14-15”, col. 11, line 27, “lead frame 11”, col. 10, line 24, the right half of “lead frame 10”, col. 8, line 56, as seen in Fig. 15, “joining materials 25, 27, 31, and 32”, col. 11, line 56, and “semiconductor chip 7b” col. 7, lines 61-62, form a first module, hereinafter “M2”) including a second semiconductor die (7b is a semiconductor chip, see col. 7, lines 61-62, however a secondary reference will be utilized to teach this limitation below) coupled to a second substrate (15 is a second substrate, and as discussed above, 7b is coupled to 15 via 11); and
a cover (“case 61”, col. 19, line 66) including:
a channel (the space inside 61 is a channel, denoted in Fig. 15 as “CH”) in fluid communication (“In the inside of the case 61, a refrigerant such as a cooling water is circulated”, col. 20, lines 3-4) with an outside surface of the first module and an outside surface of the second module (as seen in Fig. 15, CH is in fluid contact with 13C and 14C which are outside surfaces of M1 and M2 respectively),
a plurality of protrusions (“fins 60”, col. 20, line 3) extending from an inner surface of the cover into the channel (“case 61 has an opening on the opposite side of the bottom wall, and fins 60 project from the bottom wall”, col. 20, lines 2-3, furthermore, as seen in Fig. 15, 60 extend from an inner surface of 61 into CH);
a wall surrounding at least one of the plurality of protrusions (as seen in Fig. 15, 61 has vertical walls surrounding 60).
Fig. 15 of Ishino fails to disclose “a first module including a first semiconductor die;
a second module including a second semiconductor die; and
a cover including:
a groove in a surface of the wall, a sealing mechanism being disposed in the groove.”
However, in a similar field of endeavor, Bitz teaches a first module including a first semiconductor die (“Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering”, col 1, lines 11-14, therefore 7a and 7b of Ishino are semiconductor dies, and 7A included in M1 is a first semiconductor die); and
a second module including a second semiconductor die (as per above, 7B included in MB of Ishino is a second semiconductor die).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first semiconductor die; and
a second semiconductor die” as taught by Bitz in the system of Ishino for the purpose of defining what is included in the phrase “semiconductor dies”.
Fig. 15 of Ishino in combination with Bitz fails to disclose “ a cover including:
a groove in a surface of the wall, a sealing mechanism being disposed in the groove.”
However, in a similar field of endeavor, Fig. 2 of Grassmann teaches a cover (“cooling member 152”, col. 12, line 17, where 152 of Grassmann is equivalent to 61 of Ishino) including:
a groove (“structural feature 159”, col. 12, line 12, where “structural feature 159 is a sealing groove for accommodating a sealing member 156, embodied as O-ring”, col. 11, lines 34-36) in a surface of the wall (as seen in Fig. 2, 159 is in the bottom surface of the end portions of 152, equivalent to the vertical walls of 61 of Ishino) , a sealing mechanism (“sealing member 156”, col. 11, line 35) being disposed in the groove (as seen in Fig. 2, 156 is disposed in 159).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first module including a first semiconductor die; and
a second module including a second semiconductor die
a cover including:
a groove in a surface of the wall, a sealing mechanism being disposed in the groove” as taught by Grassmann in the system of Ishino in combination with Bitz for the purpose of “promoting fluid-tightness of the cooling cavity 152”, col. 11, lines 36-37).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ishino et al. (US 9,240,371 B2) in view of Bitz et al. (US 9,960,150 B2) in view of Grassmann et al. (US 11,244,886 B2) in view of Walczyk et al. (US 10,566,263 B2).
Regarding claim 17, Fig. 15 of Ishino in combination with Bitz and Grassmann discloses the apparatus of claim 16.
Fig. 15 of Ishino in combination with Bitz and Grassmann fails to disclose “further comprising wherein an end of at least one of the plurality of protrusions is separated from a surface of the first module by a gap.”
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However, in a similar field of endeavor, Fig. 4 of Walczyk teaches further comprising wherein an end of at least one of the plurality of protrusions is separated from a surface of the first module by a gap (as seen in Fig. 4, “protrusions 180B” are separated from the bottom of “void 170”, together “protrusions 180A”, 180B, and “protrusions 180C” of Walczyk are equivalent to 60 of Ishino, therefore after substitution of at least one of 180B of Walczyk for some, but not all of 60 of Ishino, 180B is separated from 13C which is a surface of M1 by a gap, “the first set of protrusions 180A, the second set of protrusions 180B, and the third set of protrusions 180C may provide tunable rigidity and conformity to the first heat spreader 110”, col. 5, lines 57-60).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising wherein an end of at least one of the plurality of protrusions is separated from a surface of the first module by a gap” as taught by Walczyk in the system of Ishino in combination with Bitz and Grassmann for the purpose of providing tunability to the heat transfer apparatus structure.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ishino et al. (US 9,240,371 B2) in view of Bitz et al. (US 9,960,150 B2) in view of Grassmann et al. (US 11,244,886 B2) in view of Tustaniwskyj et al. (US 4,879,629 A).
Regarding claim 19, Fig. 15 of Ishino in combination with Bitz and Grassmann discloses the apparatus of claim 16.
Fig. 15 of Ishino in combination with Bitz and Grassmann fails to specify “wherein the cover includes an inlet opening and an outlet opening in fluid communication with the inlet opening via the channel, the first module and the second module are aligned along the channel between the inlet opening and the outlet opening.”
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However, in a similar field of endeavor, Figs. 1-4 of Tustaniwskyj teach wherein the cover (“cover 22”, 22 of Tustaniwskyj is equivalent to 61 of Ishino) includes an inlet opening (“input port 22B”) and an outlet opening (“output port 22C”) in fluid communication with the inlet opening via the channel (“Liquid enters the channels 33 through an input port 22B in cover 22; then it passes in the channels 33 past the heat sinks 27 to remove heat from them; and then it exits through an output port 22C”, col. 3, lines 45-48, 33 of Tustaniwskyj is equivalent to CH of Ishino), the first module (together “chips 11” and “a plurality of thermally conductive studs 21” form modules, as denoted in Fig. 3, “MA” is a first module comprising “11A” and “21A” which are specific instances of 11 and 21, MA of Tustaniwskyj is equivalent to M1 of Ishino) and the second module (as denoted in Fig. 3, “MB” is a second module comprising “11B” and “21B” which are specific instances of 11 and 21, MB of Tustaniwskyj is equivalent to M2 of Ishino) are aligned along the channel between the inlet opening and the outlet opening (as seen in the cutline in Fig. 1 representing the location of Fig. 3, MA and MB are aligned along 33 between 22B and 22C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the cover includes an inlet opening and an outlet opening in fluid communication with the inlet opening via the channel, the first module and the second module are aligned along the channel between the inlet opening and the outlet opening” as taught by Tustaniwskyj in the system of Ishino in combination with Bitz and Grassmann for the purpose of providing fresh cooling fluid to the apparatus.
Allowable Subject Matter
Claims 7, 15, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the apparatus as recited in the claims of the instant application.
Regarding claim 7, the prior art of Mamitsu et al. (US 8125781 B2) in combination with Bitz et al. (US 9,960,150 B2) discloses an apparatus but fails to disclose the specific claims of the instant application e.g. “wherein the first plurality of protrusions including includes at least one protrusion having an end in contact with an inner surface of the cover”. While the prior art of Ishino et al. (US 9,240,371 B2) does teach the claimed geometry, such an arrangement would be incompatible with the primary reference of Mamitsu.
Regarding claim 15, the prior art of Mamitsu et al. (US 8125781 B2) in combination with Bitz et al. (US 9,960,150 B2) discloses an apparatus but fails to disclose the specific claims of the instant application e.g. “the first heatsink further includes a second substrate disposed on a second side of the first plurality of protrusions”. While the prior art of Ishino et al. (US 9,240,371 B2) does teach the claimed geometry, such an arrangement would be incompatible with the primary reference of Mamitsu.
Regarding claim 22, the prior art of Ishino et al. (US 9,240,371 B2) in combination with Bitz et al. (US 9,960,150 B2) discloses an apparatus but fails to disclose the claimed structure of the instant application, specifically “wherein the plurality of first protrusions is separated from the plurality of second protrusions by the wall”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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