DETAILED ACTION
This application, 18/188082, attorney docket P20222797US01, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Taiwan Semiconductor Manufacturing Company, Ltd., and has an effective filing date of 3/3/2023 based the filing date.
Applicant's election without traverse of Group I, claims 1-16 in the reply filed on 11/19/2025 is acknowledged. Claims 17-20 have been cancelled by the applicant. Claims 1-16 and new claims 21-24 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Verma et al. (U.S. 2024/0136312, filed Nov. 11, 2022) in view of Zhang et al. (U.S. 2014/0291847).
As for claim 1,
Verma teaches in figure 3, integrated circuit (IC) structure, comprising:
a first substrate (14) having an integrated circuit (46) formed thereon;
a second substrate (12) bonded (at 30 [0025]) to the first substrate;
and a deep trench capacitor (20) formed on the second substrate and electrically connected to the integrated circuit (through 34/56) wherein the deep trench capacitor includes a stack of conductive layers (24/28) and dielectric layers (22/26) disposed in deep trenches, and conductive plugs (between the electrodes and vias 56) landing on the conductive layers, respectively,
Verma does not teach that each of the conductive plugs includes a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer, the first, second and third metal layers being different in composition.
However, Zhang teaches in figure 1B, a conductive interconnection structure that includes a first metal layer (18), a second metal layer (seed layer not shown) disposed on the first metal layer, and a third metal layer (fill 20) disposed on the second metal layer, the first, second and third metal layers being different in composition.(Zhang [0008])
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the materials of Zhang into Verma because “copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten for the conductive lines and vias” Zhang [0005]); cobalt improves adhesion and wetting of copper. [0008]; and CuMn provides a seed for the copper [0008]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 2,
Verma in view of Zhang makes obvious the IC structure of claim 1, and in the combination, Zhang teaches that the first metal layer includes one of cobalt and nickel;
the second metal layer includes an alloy of copper and manganese; and the third metal layer includes one of tungsten, copper, and an alloy of copper aluminum. ([0008])
As for claim 3,
Verma in view of Zhang makes obvious the IC structure of claim 1, and the conductive layers include a first number of the conductive layers, and the conductive plugs include a second number of the conductive plugs, and the second number equals to the first number. (two each in figure 3)
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of Zhang, and further in view of Chen et al (U.S. 2014/0374880).
As for claim 4,
Verma in view of Zhang makes obvious the IC structure of claim 3, but the combination does not teach that the conductive plugs have different heights landing on respective conductive layers.
However, Chen teaches in figure 3, plugs (308) with different heights.
It would have been obvious to one skilled in the art at the effective filing date of this application to arrange the plugs according to Chen in the device of Verma because it uses a horizontal “flange” to land the plugs, which is easier to hit than an edge of the conductive layer. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 5- 9, 11, 14, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of Zhang, and further in view of Tran et al. (U.S. 2013/0161792).
As for claim 5,
Verma in view of Zhang makes obvious the IC structure of claim 1,but does not teach a plurality of deep trench capacitors formed on the second substrate and configured as an array, wherein a first one of the deep trench capacitors disposed in first deep trenches longitudinally oriented in a first direction;
and a second one of the deep trench capacitors disposed in second deep trenches longitudinally oriented in a second direction being orthogonal to the first direction, the second one of the deep trench capacitors being adjacent to the first one of the trench capacitors in the array.
However, Tran teaches in figure 1E, DTC’s in orthogonal arrays.
It would have been obvious to one skilled in the art at the effective filing date of this application to arrange the DTCs according to Tran in the device of Verma because it “The device 100 may include seams 126 that are configured to facilitate lower stress (e.g., facilitate stress management) to the capacitor 108” Tran [0022]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 6,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 5, and in the combination, Tran teaches the first one of the deep trench capacitors includes a plurality of first conductive plugs disposed between adjacent two of the first deep trenches and aligned along the first direction. (contacts 326 are at the ends of the capacitor in figure 1A of Tran.)
As for claim 7,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 6, and in the combination, Tran makes obvious that the second one of the deep trench capacitors includes a plurality of second conductive plugs disposed between adjacent two of the second deep trenches and aligned along the second direction. Each capacitor must have the contacts at the ends that cross all the trenches to conform to figure 1A.)
As for claim 8,
Verma teaches in figure 3, an integrated circuit (IC) structure, comprising
deep trench capacitors (20) formed on a first substrate (12)
wherein each of the deep trench capacitors includes a stack of conductive layers (24/28) and dielectric layers (22/26) disposed in deep trenches, and
conductive plugs (between the conductors and vias 56) landing on the conductive layers, respectively,
Verma does not teach that each of the conductive plugs includes a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer, the first, second and third metal layers being different in composition.
However, Zhang teaches in figure 1B, a conductive interconnection structure that includes a first metal layer (18), a second metal layer (seed layer not shown) disposed on the first metal layer, and a third metal layer (fill 20) disposed on the second metal layer, the first, second and third metal layers being different in composition.(Zhang [0008])
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the materials of Zhang into Verma because “copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten for the conductive lines and vias.” Zhang [0005]); cobalt improves adhesion and wetting of copper. [0008]; and CuMn provides a seed for the copper [0008]. One skilled in the art would have combined these elements with a reasonable expectation of success.
Verma doesn’t teach that the capacitors are configured in an array, wherein the deep trench capacitors include a first deep trench capacitor disposed in first deep trenches longitudinally oriented in a first direction; and
a second deep trench capacitor being adjacent the first deep trench capacitor in the array and disposed in second deep trenches longitudinally oriented in a second direction that is orthogonal to the first direction.
However, Tran teaches in figure 1E, DTC’s in orthogonal arrays.
It would have been obvious to one skilled in the art at the effective filing date of this application to arrange the DTCs according to Tran in the device of Verma because it “The device 100 may include seams 126 that are configured to facilitate lower stress (e.g., facilitate stress management) to the capacitor 108” Tran [0022]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 9,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 8,
And in the combination, Verma teaches a second substrate (14) having an integrated circuit (46) formed thereon, wherein the second substrate is bonded to the first substrate; and the deep trench capacitors are electrically connected to the integrated circuit. (through vias 34/56)
Claims 10, 12, 13,21,2 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Verma in view of Zhang, and Tran and further in view of Chen.
As for claim 10,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 8, but does not teach that the conductive plugs of the first deep trench capacitor have different heights landing on the conductive layers, respectively.
However, Chen teaches in figure 3, plugs (308) with different heights.
It would have been obvious to one skilled in the art at the effective filing date of this application to arrange the plugs according to Chen in the device of Verma because it uses a horizontal “flange” to land the plugs, which is easier to hit than an edge of the conductive layer. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 11,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 8, and in the combination, Zhang teaches that the first metal layer includes one of cobalt and nickel; the second metal layer includes an alloy of copper and manganese; and the third metal layer includes one of tungsten, copper, and an alloy of copper aluminum. ([0008])
As for claim 12,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 11, and in the combination, And Tran teaches that that the stack of conductive layers and dielectric layers of the first deep trench capacitor includes a first segment extended beyond the first deep trenches in figure 1A;
And in the figure, Tran teaches that the first segment includes a step-wise structure with the conductive layers of the first deep trench capacitor laterally extending respective lengths different from each other; but the combination does not teach that the conductive plugs of the first trench capacitor landing on the conductive layers of the first deep trench capacitor, respectively.
However, Chen teaches in figure 3, conductive plugs of the first trench capacitor landing on the conductive layers of the first deep trench capacitor.
It would have been obvious to one skilled in the art at the effective filing date of this application to arrange the plugs according to Chen in the device of Verma because it uses a horizontal “flange” to land the plugs, which is easier to hit than an edge of the conductive layer, and allows multiple layers of electrodes, increasing the capacitor density. One skilled in the art would have combined these elements with a reasonable expectation of success.
The combination does not teach that the stack extends onto a dielectric feature because Tran extends onto a N-doped semiconductor.
However, Chen teaches that the stack extends onto a dielectric feature (306).
It would have been obvious to one skilled in the art at the effective filing date of this application to extend the dielectric 306 onto the horizontal surface of the substrate to isolate the substrate from the capacitor. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 13,
Verma in view of Zhang and Tran and Chen makes obvious the IC structure of claim 12, and in the combination, Chen teaches a dielectric material layer (116) laterally surrounding sidewalls of each of the conductive plugs of the first deep trench capacitor, wherein the dielectric material layer is different from the dielectric feature in composition (116 is Teos [0022], 306 is ONO. [0031]); and
the dielectric material layer is absent from bottom surfaces of the conductive plugs of the first deep trench capacitor.(bottom surface of the plugs of Chen are embedded in the electrodes)
It would have been obvious to one skilled in the art at the effective filing date of this application to use a different dielectric form the capacitor dielectric and the ILD because ONO can be thinner with a high dielectric constant, and TEOS can be formed very thick in a short time. One skilled in the art would have combined these elements with a reasonable expectation of success.
It would have been obvious to one skilled in the art at the effective filing date of this application to use prevent dielectric from forming in the via hole to make a good electrical connection between via and capacitor electrode. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 14,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 8, and in the combination, Tran teaches in figure 1A, that the conductive plugs of the first deep trench capacitor are disposed between adjacent two of the first deep trenches and aligned along the first direction in a top view. (shown in 1E)
As for claim 15,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 8, and in the combination, Tran teaches the conductive plugs of the first deep trench capacitor are disposed on a first side of the first deep trenches and aligned along the first direction in a top view. (shown in 1E).
As for claim 16,
Verma in view of Zhang and Tran makes obvious the IC structure of claim 8, and in the combination, Zhang makes obvious an interconnect structure (156/60) disposed on the first and second deep trench capacitors,
wherein the interconnect structure includes a first metal layer having first metal lines (156) connected to the conductive plugs, and wherein the first metal lines include a first subset of the first metal lines longitudinally oriented along the first direction and a second subset of the first metal lines longitudinally oriented along the second direction.
It would have been obvious to one skilled in the art at the effective filing date of this application to use a subset of the metal lines oriented the same as the capacitor trenches of Tran because it would allow the connecting wires to be formed in the same metal level. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 21,
Verma teaches in figure 3, an integrated circuit (IC) structure, comprising a first substrate (12);
a second substrate (14) having an integrated circuit (46) formed thereon and bonded to the first substrate (at 30 [0025]); and
deep trench capacitors (20) formed on the first substrate and electrically connected to the integrated circuit (through 34/56), wherein each of the deep trench capacitors includes a stack of conductive layers (24/28) and dielectric layers (22/26) disposed in deep trenches, and
conductive plugs (between the electrodes and vias 56) are landing on the conductive layers, respectively.
Verma does not teach that the capacitors are configured in an array wherein the deep trench capacitors include a first deep trench capacitor disposed in first deep trenches longitudinally oriented in a first direction, a second deep trench capacitor being adjacent the first deep trench capacitor in the array and disposed in second deep trenches longitudinally oriented in a second direction that is orthogonal to the first direction.
However, Tran teaches in figure 1E, DTC’s in orthogonal arrays.
It would have been obvious to one skilled in the art at the effective filing date of this application to arrange the DTCs according to Tran in the device of Verma because it “The device 100 may include seams 126 that are configured to facilitate lower stress (e.g., facilitate stress management) to the capacitor 108” Tran [0022]. One skilled in the art would have combined these elements with a reasonable expectation of success.
Verma does not teach that each of the conductive plugs includes a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer, the first, second and third metal layers being different in composition.
However, Zhang teaches in figure 1B, a conductive interconnection structure that includes a first metal layer (18), a second metal layer (seed layer not shown) disposed on the first metal layer, and a third metal layer (fill 20) disposed on the second metal layer, the first, second and third metal layers being different in composition.(Zhang [0008])
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the materials of Zhang into Verma because “copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten for the conductive lines and vias” Zhang [0005]); cobalt improves adhesion and wetting of copper. [0008]; and CuMn provides a seed for the copper [0008]. One skilled in the art would have combined these elements with a reasonable expectation of success.
Verma does not teach that the conductive plugs have different heights landing on respective conductive layers.
However, Chen teaches in figure 3, plugs (308) with different heights.
It would have been obvious to one skilled in the art at the effective filing date of this application to arrange the plugs according to Chen in the device of Verma because it uses a horizontal “flange” to land the plugs, which is easier to hit than an edge of the conductive layer. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 22,
Verma in view of Zhang and Tran and Chen makes obvious the IC structure of claim 21, and in the combination, Zhang teaches that the first metal layer includes one of cobalt and nickel; the second metal layer includes an alloy of copper and manganese; and
the third metal layer includes one of tungsten, copper, and an alloy of copper aluminum. ([0008])
As for claim 23,
Verma in view of Zhang and Tran and Chen makes obvious the IC structure of claim 21, an but the combination does not teach that the stack of conductive layers and dielectric layers of the first deep trench capacitor includes a first segment extended onto a dielectric feature beyond the first deep trenches; or that the first segment includes a step-wise structure with the conductive layers of the first deep trench capacitor laterally extending respective lengths different from each other;
the conductive plugs of the first trench capacitor landing on the conductive layers of the first deep trench capacitor, respectively; and the conductive plugs of the first deep trench capacitor are disposed between adjacent two of the first deep trenches and aligned along the first direction in a top view.
However, Chen teaches sin figure 3, a stack of conductive layers and dielectric layers of the first deep trench capacitor includes a first segment extended onto a dielectric feature beyond the first deep trenches (304A);
And that the first segment includes a step-wise structure with the conductive layers of the first deep trench capacitor laterally extending respective lengths different from each other;
the conductive plugs (308) of the first trench capacitor landing on the conductive layers of the first deep trench capacitor, respectively;
and the conductive plugs of the first deep trench capacitor are disposed between adjacent two of the first deep trenches and aligned along the first direction in a top view.(Taught by Tran in the combination as discussed above).
As for claim 24,
Verma in view of Zhang and Tran and Chen makes obvious the IC structure of claim 12, and in the combination, Chen teaches a dielectric material layer (116) laterally surrounding sidewalls of each of the conductive plugs of the first deep trench capacitor, wherein the dielectric material layer is different from the dielectric feature in composition (116 is Teos [0022], 306 is ONO. [0031]); and
the dielectric material layer is absent from bottom surfaces of the conductive plugs of the first deep trench capacitor. (The bottom surface of the plugs of Chen are embedded in the metal capacitor electrodes).
It would have been obvious to one skilled in the art at the effective filing date of this application to use a different dielectric form the capacitor dielectric and the ILD because ONO can be thinner with a high dielectric constant, and TEOS can be formed very thick in a short time. One skilled in the art would have combined these elements with a reasonable expectation of success.
It would have been obvious to one skilled in the art at the effective filing date of this application to use prevent dielectric from forming in the via hole to make a good electrical connection between via and capacitor electrode. One skilled in the art would have combined these elements with a reasonable expectation of success.
Zhang makes obvious an interconnect structure (156/60) disposed on the first and second deep trench capacitors,
wherein the interconnect structure includes a first metal layer having first metal lines (156) connected to the conductive plugs, and wherein the first metal lines include a first subset of the first metal lines longitudinally oriented along the first direction and a second subset of the first metal lines longitudinally oriented along the second direction.
It would have been obvious to one skilled in the art at the effective filing date of this application to use a subset of the metal lines oriented the same as the capacitor trenches of Tran because it would allow the connecting wires to be formed in the same metal level. One skilled in the art would have combined these elements with a reasonable expectation of success.
Conclusion
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893