Prosecution Insights
Last updated: May 29, 2026
Application No. 18/188,196

Metal-Insulator-Metal Capacitors And Methods Of Forming The Same

Final Rejection §103§DOUBLEPATENT
Filed
Mar 22, 2023
Priority
Sep 08, 2022 — provisional 63/404,653 +1 more
Examiner
NGUYEN, DUY T V
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
2 (Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
834 granted / 1060 resolved
+10.7% vs TC avg
Strong +17% interview lift
Without
With
+16.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
57 currently pending
Career history
1118
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
78.9%
+38.9% vs TC avg
§102
4.1%
-35.9% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1060 resolved cases

Office Action

§103 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application 1. Acknowledgement is made of the amendment received on 12/5/2025. Claims 1-16 & 21-24 are pending in this application. Claims 17-20 are canceled. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 2. Claims 1-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 2021/0343831) in view of Olsen et al. (US 2005/0260357). Re claim 1, Hu teaches, under BRI, Figs. 4-6, [0058, 0070, 0092, 0164, 0165, 0169], a method, comprising: -depositing a first conductive material layer (first electrode layer 300) over a substrate (100); -patterning the first conductive material layer (300) to form a first conductor plate over the substrate (100) [0058]; -forming a first high-K dielectric layer (410) over the first conductor plate (300); -forming a second high-K dielectric layer (420) on the first high-K dielectric layer; -forming a third high-K dielectric layer (430) on the second high-K dielectric layer; and -forming a second conductor plate (500) over the third high-K dielectric layer (430) and vertically overlapped with the first conductor plate (300), wherein a composition of the first high-K dielectric layer (410) is the same as a composition of the third high-K dielectric layer (430) (e.g., hafnium oxide) and is different from a composition of the second high-K dielectric layer (420) (e.g., aluminum oxide). PNG media_image1.png 268 495 media_image1.png Greyscale Hu further teaches the first electrode layer is made of nitrided metal [0015], but does not explicitly teach performing a nitridation process to the first conductor plate. Olsen teaches performing a nitridation process to the first conductor plate (502) [0051]. As taught by Olsen, one of ordinary skill in the art would utilize & modify the above teaching to obtain step of performing a nitridation process to the first conductor plate as claimed, because it aids in increasing wear/corrosion resistance and improving device performance. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Olsen in combination with Hu due to above reason. Re claim 2, Hu does not explicitly teach the first high-K dielectric layer and the third high-K dielectric layer comprises hafnium zirconium oxide (HZO). Olsen teaches “Dielectric layer 202 is generally a high-k dielectric material and includes combinations of hafnium, zirconium, titanium, tantalum, lanthanum, aluminum, silicon, oxygen and/or nitrogen” [0028]. As taught by Olsen, one of ordinary skill in the art would utilize & modify the above teaching into Hu to obtain the first high-K dielectric layer and the third high-K dielectric layer comprises hafnium zirconium oxide (HZO) as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Olsen in combination with Hu due to above reason. Re claim 3, Hu teaches the second high-K dielectric layer comprises aluminum oxide (Al2O3) [0169] or titanium oxide (TiO2). Re claim 9, Hu teaches a thickness of the third high-K dielectric layer (430) is substantially equal to a thickness of the first high-K dielectric layer (410) (Fig. 6). 3. Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hu as modified by Olsen as applied to claim 1 above, and further in view of Kang (US 2021/0359082). The teachings of Hu/Olsen have been discussed above. Re claims 7 & 8, Hu/Olsen does not teach forming a fourth high-K dielectric layer on the third high-K dielectric layer, wherein a composition of the fourth high-K dielectric layer is different from the composition of the first high-K dielectric layer, wherein the composition of the fourth high-K dielectric layer is the same as the composition of the second high-K dielectric layer. Kang teaches, Fig. 4D, forming a fourth high-K dielectric layer (LBL, Al2O3) on the third high-K dielectric layer (HK2), wherein a composition of the fourth high-K dielectric layer (LBL) is different from the composition of the first high-K dielectric layer (HK1 as Hf02), wherein the composition of the fourth high-K dielectric layer (LBL) is the same as the composition of the second high-K dielectric layer (HBG). As taught by Kang, one of ordinary skill in the art would utilize & modify the above teaching into Hu to obtain a fourth high-K dielectric layer as claimed, because it aids in achieving a desired multi-layer stack of high-k dielectric layers & a capacitor having a high dielectric constant, a low leakage current and high capacitance. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kang in combination with Hu/Olsen due to above reason. Double Patenting 4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-16 & 21-24 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 19/287,962 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because they both require similar process steps and limitations such as depositing/pattern a first conductive material layer, forming multi-high k dielectric layers (first-third high-k dielectric layers), forming a second conductive plate & forming first/second vias, etc. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. 18/188,196 1. A method, comprising: depositing a first conductive material layer over a substrate; patterning the first conductive material layer to form a first conductor plate over the substrate; performing a nitridation process to the first conductor plate; forming a first high-K dielectric layer over the first conductor plate; forming a second high-K dielectric layer on the first high-K dielectric layer; forming a third high-K dielectric layer on the second high-K dielectric layer; and forming a second conductor plate over the third high-K dielectric layer and vertically overlapped with the first conductor plate, wherein a composition of the first high-K dielectric layer is the same as a composition of the third high-K dielectric layer and is different from a composition of the second high-K dielectric layer. 4. The method of claim 1, wherein the patterning of the first conductive material layer comprises performing an etching process to the first conductive material layer, wherein the performing of the etching process further oxidizes sidewall and top surfaces of the first conductor plate to form an oxide layer. 19/287,962 1. A method, comprising: depositing a first conductive material layer over a substrate; patterning the first conductive material layer to form a first conductor plate over the substrate; conformally depositing an oxide layer over the first conductor plate; forming a first high-K dielectric layer over the oxide layer; forming a second high-K dielectric layer on the first high-K dielectric layer; forming a third high-K dielectric layer on the second high-K dielectric layer; and forming a second conductor plate over the third high-K dielectric layer and vertically overlapped with the first conductor plate, wherein a composition of the first high-K dielectric layer is the same as a composition of the third high-K dielectric layer and is different from a composition of the second high-K dielectric layer. Allowable Subject Matter 5. Claims 4-6 would be allowable if rewritten to overcome the rejection(s) under Double Patenting, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claims 10-16 & 21-24 would be allowable if rewritten or amended to overcome the rejection(s) under Double Rejection, set forth in this Office action. The allowable subject matters include the steps of “forming a second insulation layer extending along top and sidewall surfaces of the first conductor plate, wherein the first conductor plate spans a first width, the second insulation layer spans a second width greater than the first width; conformally forming a multi-layer dielectric structure over the first conductor plate, wherein the multi-layer dielectric structure extends contiguously on the first insulation layer and the second insulation layer, and wherein the multi-layer dielectric structure is formed of high-K dielectric layers; and forming a second conductor plate over the multi-layer dielectric structure and vertically overlapped with the first conductor plate” (claim 10); and “forming a first conductor plate over a substrate, the first conductor plate extending over a first lower contact feature in the substrate; forming an oxide layer on the first conductor plate; depositing a multi-layer structure formed of high-k dielectric materials over the oxide layer; forming a second conductor plate extending on the multi-layer structure, the second conductor plate extending over a second lower contact feature in the substrate; forming a first via extending through the first conductor plate to couple to the first lower contact feature; and forming a second via extending through the multi-layer structure and the second conductor plate to couple to the second lower contact feature, wherein the second via is physically separated from the oxide layer” (claim 21). Response to Arguments 6. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection. Conclusion 7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/9/26
Read full office action

Prosecution Timeline

Mar 22, 2023
Application Filed
Aug 27, 2025
Non-Final Rejection mailed — §103, §DOUBLEPATENT
Dec 05, 2025
Response Filed
Feb 12, 2026
Final Rejection mailed — §103, §DOUBLEPATENT
Apr 10, 2026
Response after Non-Final Action

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+16.8%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1060 resolved cases by this examiner. Grant probability derived from career allowance rate.

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