DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group II (claims 11-19), species I in Figs. 1-21F in the reply filed on 11/28/2025 is acknowledged. Claims 1-10 and 20 have been canceled. Claim 15 is withdrawn from consideration. Claims 21-31 have been added.
Claim 11 is allowable. The restriction requirement among species I-XV, as set forth in the Office action mailed on 10/01/2025, has been reconsidered in view of the allowability of claims to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Specifically, the restriction requirement of species I-XV is withdrawn. Claim 15, directed to non-elected species, is no longer withdrawn from consideration because the claim(s) requires all the limitations of an allowable claim.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Dias et al. (US 2017/0098709 A1) in view of Cheng et al. (US 10069015 B2).
Regarding claim 21, Dias teaches a method (method 600 in Fig. 6 of forming the device in Fig. 2B of Dias) comprising:
depositing a stacking structure (semiconductor layer mentioned in step 604 in method 600) over a substrate (substrate described in [0045] of Dias);
forming a mask layer (lithography mask including spacer in steps 601-603 of Fig. 6) over the stacking structure, wherein the mask layer comprises:
a first hard mask (portion of mask over the fin 231 in Fig. 2B) extending in a first direction (fin length direction in Fig. 2B) and having a first width (width of fin 231) in a second direction (fin width direction) different from the first direction in a top view;
a second hard mask (portion of mask over the fin 233 in Fig. 2B) extending in the first direction and having a second width (width of fin 233); and
a third hard mask (portion of mask over the connecting portion of fin 233 to the fins 231 and 232) interconnecting the first hard mask and the second hard mask and having a third width (width of the connecting mask) different from the first width and the second width in the second direction in the top view;
patterning the stacking structure (step 604) by using the mask layer as an etch mask to form a first fin structure (fin 231) patterned from the first hard mask, a second fin structure (fin 233) patterned from the second hard mask, and a third fin structure (portion of connecting portion of fin 233 to the fins 231 and 232) patterned from the third hard mask;
forming a first transistor (244-245-246) over the first fin structure; and
forming a second transistor (241-242-243) over the second fin structure.
But Dias does not teach that wherein the stacking structure comprises first semiconductor layers and second semiconductor layers alternately arranged; the second width is greater than the first width in the second direction in the top view; wherein the second semiconductor layers in the first fin structure are channel layers of the first transistor; and wherein the second semiconductor layers in the second fin structure are channel layers of the second transistor.
Dias teaches that the second width is different than the first width (see [0024] of Dias). There are only two possible choices: the second width is greater than the first width or the second width is smaller than the first width.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the second width greater than the first width in an application where the second transistor is required to handle more current than the first transistor.
But Dias does not teach that wherein the stacking structure comprises first semiconductor layers and second semiconductor layers alternately arranged; wherein the second semiconductor layers in the first fin structure are channel layers of the first transistor; and wherein the second semiconductor layers in the second fin structure are channel layers of the second transistor.
Cheng teaches a method of forming a nanowire device (Figs. 1-17 of Cheng). The method comprises: forming a stacking structure of first semiconductor layers (106a-d in Fig. 1) and second semiconductor layers (108a-d) alternately arranged (as shown in Fig. 1 of Cheng); patterning the stacking structure to form first fin and second fin (Figs. 2-3 of Cheng); forming a first transistor over the first fin and a second transistor over the second fin (see Figs. 4-16 of Cheng) wherein the second semiconductor layers are channel layers of the first and second transistors (see Fig. 16 of Cheng).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the nanosheet channel layers in the channel layers of the transistors in order to improve the performance of the transistors.
Regarding claim 22, Dias in view of Cheng teaches all limitations of the method of claim 21, and also teaches wherein the third width of the third hard mask is greater than the first width of the first hard mask and the second width of the second hard mask (as shown in Fig. 2B of Dias).
Regarding claim 23, Dias in view of Cheng teaches all limitations of the method of claim 21, and also teaches wherein a sidewall (outer sidewall) of the third hard mask is misaligned with a sidewall of the second hard mask (as shown in Fig. 2B of Dias).
Regarding claim 29, Dias teaches a method (method 600 in Fig. 6 of forming the device in Fig. 2B of Dias) comprising:
depositing a stacking structure (semiconductor layer mentioned in step 604 in method 600) over a substrate (substrate described in [0045] of Dias);
patterning the stacking structure to form a first fin structure (231 in Fig. 2B) extending in a first direction (fin length direction in Fig. 2B), a second fin structure (233) extending in the first direction in a top view, and a third fin structure (connecting portion of fin 233 to the fins 231 and 232) interconnecting the first fin structure and the second fin structure, wherein the first fin structure, the third fin structure, and the second fin structure are arranged in the first direction and have different widths (as shown in Fig. 2B and [0024] of Dias) in a second direction (fin width direction) different from the first direction in the top view, and a sidewall of the third fin structure is substantially aligned with a sidewall of the first fin structure and is misaligned with a sidewall of the second fin structure (as shown in Fig. 2B);
forming a first transistor (244-245-246) over the first fin structure; and
forming a second transistor (241-242-243) over the second fin structure.
But Dias does not teach that wherein the stacking structure comprises first semiconductor layers and second semiconductor layers alternately arranged; wherein the second semiconductor layers in the first fin structure are channel layers of the first transistor; wherein the second semiconductor layers in the second fin structure are channel layers of the second transistor.
Cheng teaches a method of forming a nanowire device (Figs. 1-17 of Cheng). The method comprises: forming a stacking structure of first semiconductor layers (106a-d in Fig. 1) and second semiconductor layers (108a-d) alternately arranged (as shown in Fig. 1 of Cheng); patterning the stacking structure to form first fin and second fin (Figs. 2-3 of Cheng); forming a first transistor over the first fin and a second transistor over the second fin (see Figs. 4-16 of Cheng) wherein the second semiconductor layers are channel layers of the first and second transistors (see Fig. 16 of Cheng).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the nanosheet channel layers in the channel layers of the transistors in order to improve the performance of the transistors.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Dias in view of Chang, and further in view of Zhang et al. (US 2021/0210489 A1).
Regarding claim 30, Dias in view of Chang teaches all limitations of the method of claim 29, but does not teach further comprising forming a dielectric fin in contact with the sidewall of the first fin structure and the sidewall of the third fin structure.
Zhang teaches a fork-sheet transistor structure that comprises: a dielectric fin (120 in Fig. 3) in between and in contact with sidewalls of two adjacent stacks of semiconductor nanosheets wherein the dielectric fin is taller than the stacks of semiconductor nanosheets; shallow isolation structure (110 in Fig. 3) on the outer sidewalls of the nanosheet stacks opposite with the dielectric fin.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a dielectric fin between two adjacent stacking structure as disclosed by Zhang in order to be able to further tune the channel width of the transistor.
Allowable Subject Matter
Claims 11-19 are allowed.
Claim 24-28 and 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art of record does not disclose or fairly suggest a method comprising: “patterning the epitaxial stack to form a first fin structure over a first device region of the substrate, a second fin structure over a second device region, and a third fin structure over a connecting region, wherein the third fin structure interconnects the first fin structure and the second fin structure, and the first fin structure is offset from the second fin structure; forming a dielectric fin over the substrate and in contact with the first fin structure and the second fin structure but spaced apart from the third fin structure; forming a first transistor over the first device region, wherein the second semiconductor layers of the first fin structure are channel layers of the first transistor; forming a second transistor over the second device region, wherein the second semiconductor layers of the second fin structure are channel layers of the second transistor; and forming a first dielectric gate structure over the substrate and between the first device region and the connecting region and a second dielectric gate structure over the substrate and between the second device region and the connecting region” along with other limitations of the claim.
Regarding claim 24, the prior art of record does not disclose or fairly suggest a method comprising: “forming a dielectric fin on a sidewall of the first fin structure and a sidewall of the third fin structure, wherein sidewalls of the second fin structure are uncovered by the dielectric fin” along with other limitations of the claim 21.
Regarding claim 27, the prior art of record does not disclose or fairly suggest a method comprising: “forming a dielectric gate structure between the first fin structure and the third fin structure after forming the first transistor” along with other limitations of the claim 21.
Regarding claim 28, the prior art of record does not disclose or fairly suggest a method comprising: “forming a dielectric gate structure between the second fin structure and the third fin structure after forming the second transistor” along with other limitations of the claim 21.
Regarding claim 31, the prior art of record does not disclose or fairly suggest a method comprising: “forming a dielectric gate structure between the second fin structure and the third fin structure after forming the second transistor” along with other limitations of the claim 29.
The closest prior art of record are Dias et al. (US 2017/0098709 A1), and Zhang et al. (US 2021/0210489 A1).
Dias teaches a method (method 600 in Fig. 6 of forming the device in Fig. 2B of Dias) comprising: depositing a stacking structure (semiconductor layer mentioned in step 604 in method 600) over a substrate (substrate described in [0045] of Dias); forming a mask layer over the stacking structure, wherein the mask layer comprises: a first hard mask (portion of mask over the fin 231 in Fig. 2B) extending in a first direction (fin length direction in Fig. 2B) and having a first width (width of fin 231) in a second direction (fin width direction) different from the first direction in a top view; a second hard mask (portion of mask over the fin 233 in Fig. 2B) extending in the first direction and having a second width (width of fin 233); and a third hard mask (portion of mask over the connecting portion of fin 233 to the fins 231 and 232) interconnecting the first hard mask and the second hard mask and having a third width (width of the connecting mask) different from the first width and the second width in the second direction in the top view; and patterning the stacking structure (step 604) by using the mask layer as an etch mask to form a first fin structure (fin 231) patterned from the first hard mask, a second fin structure (fin 233) patterned from the second hard mask, and a third fin structure (portion of connecting portion of fin 233 to the fins 231 and 232) patterned from the third hard mask; forming a first transistor (244-245-246) over the first fin structure; and forming a second transistor (241-242-243) over the second fin structure.
Zhang teaches a fork-sheet transistor structure that comprises: a dielectric fin (120 in Fig. 3) in between and in contact with sidewalls of two adjacent stacks of semiconductor nanosheets wherein the dielectric fin is taller than the stacks of semiconductor nanosheets; shallow isolation structure (110 in Fig. 3) on the outer sidewalls of the nanosheet stacks opposite with the dielectric fin.
However, neither Dias nor Zhang teaches that the dielectric fin is only formed between the first two fins and not the second fin (with larger width). None of these arts teaches a dielectric gate structure between the active device and the connecting fin structure either.
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898