DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 12/01/2025. Claims 1-20 are pending for this examination.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/01/2025 has been entered. An action on the RCE follows.
Response to Arguments
Applicant’s reply filed on 12/01/2025 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YU et al (US 2021/0098455 A1; hereafter YU).
Regarding claim 1. YU discloses a semiconductor structure, comprising:
a set of nanostructures (Fig. [16], nano-sheets 132, Para [ 0024]) on a substrate (substrate 102, Para [ 0024]);
a gate dielectric layer (Fig. [16], layers [140, 142], construed as gate dielectric layer, Para [ 0028]) wrapped around the set of nanostructures (Fig. [16], nano-sheets 132, Para [ 0024]), wherein the gate dielectric layer (Fig. [16], layers [140, 142], construed as gate dielectric layer, Para [ 0028]) comprises an interfacial layer (interfacial layer (IL) 140, Para [ 0028]) and a high-k dielectric layer (high-k gate dielectric layer 142, Para [ 0028]);
a work function metal layer (work function metal layer 153, Para [ 0050]) on the gate dielectric layer (Fig. [16], layers [140, 142], construed as gate dielectric layer, Para [ 0028]) and around the set of nanostructures (Fig. [16], nano-sheets 132, Para [ 0024]); and
an isolation structure (passivation layer 162, Para [ 0055]) on sidewalls of the set of nanostructures (Fig. [16], nano-sheets 132, Para [ 0024]), the high-k gate dielectric layer (high-k gate dielectric layer 142), and the work function metal layer (Fig. [16], work function metal layer 153, Para [ 0050]), wherein a portion of the work function metal layer (Fig. [16], work function metal layer 153, Para [ 0050]) is on a top surface of the isolation structure (passivation layer 162, Para [ 0055]).
Regarding claim 2. YU. Ando discloses the semiconductor structure of claim 1, YU further discloses wherein the isolation structure (Fig. [16], passivation layer 162, Para [ 0055]) has a sidewall adjacent to the work function metal layer (work function metal layer 153, Para [ 0050]), and wherein the sidewall includes concave and convex surfaces adjacent to each other (Fig. [16], passivation layer 162, Para [ 0055]).
Regarding claim 6. YU discloses the semiconductor structure of claim 1, YU further discloses wherein a height of the isolation structure (Fig. [16], passivation layer 162, Para [ 0055]) is less than a height of the set of nanostructures (Fig. [16], nano-sheets 132, Para [ 0024]).
Regarding claim 7. YU discloses the semiconductor structure of claim 1, Ando further discloses wherein the gate dielectric layer (Fig. [16], layers [140, 142], construed as gate dielectric layer, Para [ 0028]) comprises a high-k dielectric layer (high-k gate dielectric layer 142) between the isolation structure (passivation layer 162, Para [ 0055]) and the set of nanostructures (Fig. [16], nano-sheets 132, Para [ 0024]).
Allowable Subject Matter
Claims 3-5 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 3. The semiconductor structure of claim 1, an air gap between the gate dielectric layer and the isolation structure.
Regarding claim 4. The semiconductor structure of claim 1, further comprising a dielectric liner between the gate dielectric layer and the isolation structure.
Regarding claim 5. The semiconductor structure of claim 1, wherein an additional portion of the work function metal layer is between the gate dielectric layer and the isolation structure.
Regarding claim 8. The semiconductor structure of claim 1, wherein the work function metal layer comprises a first work function metal sublayer surrounding four sides of the set of nanostructures and a second work function metal sublayer surrounding three sides of the set of nanostructures.
Claims 9-20 are allowed.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
a first isolation structure between sidewalls of the first and second sets of nanostructures and in contact with the first and second work function metal layers, wherein the gate dielectric layer is on sidewall surfaces of the first isolation structure; and a second isolation structure on the first isolation structure and in contact with the first isolation structure, wherein a width of the first isolation structure is greater than a width of the second isolation structure, as recited in claim 9.
Claims 10-13 are allowed based on the dependency of claim 9.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
forming a dielectric liner on the first and second sets of nanostructures; forming a first isolation structure between sidewalls of the first set of nanostructures and the second set of nanostructures, wherein the first isolation structure is in contact with the dielectric liner; removing the dielectric plugs between each of the first set of nanostructures and between each of the second set of nanostructures; forming a first work function metal layer on the gate dielectric layer wrapped around the first set of nanostructures and on a top surface of the first isolation structure; and forming a second work function metal layer on the gate dielectric layer wrapped around the second set of nanostructures and on the top surface of the first isolation structure, as recited in claim 14.
Claims 15-20 are allowed based on the dependency of claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898