DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 5/13/2026 is acknowledged. Claims 1, 21, 28 have been amended. Claims 33-38 are added.
Response to Arguments
Applicant's arguments filed 5/13/2026 have been fully considered but they are not persuasive.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 21, 24, 28, 31, 33, 35 and 37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2021/0020786 A1).
Regarding claim 1, Lin teaches a semiconductor structure (900 in Figs. 2 & 9 of Lin), comprising:
a fin structure (613 in Fig. 9 or 213 in Fig. 2) on a substrate (201);
a gate dielectric layer (903, as shown in Fig. 2 of Lin, this gate dielectric layer 903 is on the top surface of the fin 213 as well as the two sidewalls 213B of the fin) on the fin structure, wherein:
the gate dielectric layer comprises a bottom portion (portion of 903 on top surface of the STI 215), sidewall portions (portions of 903 in the vicinity of sidewalls of the fin 213), and a top portion (portion of 903 on top surface of the fin 213) above the bottom and sidewall portions (as shown in Fig. 2 of Lin),
the top portion of the gate dielectric layer is crystalline (903B is crystalline) and comprises a crystalline high-k dielectric material (as stated in [0062]), and
the sidewall portions (the sidewall portions of 903 also include layers 903A1 in Fig. 9 of Lin) are amorphous and comprise an amorphous high-k dielectric material (as stated in [0062] of Lin), wherein the crystalline high-k dielectric material and the amorphous high-k dielectric material comprise a same high-k dielectric material (as described in [0021] of Lin, the high-k dielectric material is HfO2); and
a gate structure (617) on the gate dielectric layer.
Regarding claim 4, Lin teaches all limitations of the semiconductor structure of claim 1,and also teaches wherein a thickness of the gate dielectric layer ranges from about 0.1 nm to about 5 nm (as described in [0022] of Lin).
Regarding claim 33, Lin teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein the crystalline high-k dielectric material comprises crystalline hafnium oxide and the amorphous high-k dielectric material comprises amorphous hafnium oxide (as described in [0021] of Lin, the high-k dielectric material is HfO2).
Regarding claim 21, Lin teaches a semiconductor device (900 in Figs. 2 & 9 of Lin), comprising:
an interfacial layer (602) on a channel structure (fin 213 as shown in Fig. 2);
a gate dielectric layer (903, as shown in Fig. 2 of Lin, this gate dielectric layer 903 is on the top surface of the fin 213 as well as the two sidewalls 213B of the fin) on the interfacial layer, wherein
the gate dielectric layer comprises sidewall portions (portions of 903 in the vicinity of sidewalls of the fin 213) and a top portion (portion of 903 on top surface of the fin 213) above the sidewall portions,
the top portion of the gate dielectric layer is crystalline (903B is crystalline) and comprises a crystalline high-k dielectric material (as stated in [0062]), and
the sidewall portions (the sidewall portions of 903 also include layers 903A1 in Fig. 9 of Lin) are amorphous and comprise an amorphous high-k dielectric material (as stated in [0062] of Lin), wherein the crystalline high-k dielectric material and the amorphous high-k dielectric material comprise a same high-k dielectric material (as described in [0021] of Lin, the high-k dielectric material is HfO2); and
a gate structure (617) on the gate dielectric layer over the channel structure.
Regarding claim 24, Lin teaches all limitations of the semiconductor device of claim 21, and also teaches wherein a thickness of the gate dielectric layer ranges from about 0.1 nm to about 5 nm (as described in [0022] of Lin).
Regarding claim 35, Lin teaches all limitations of the semiconductor device of claim 21, and also teaches wherein the crystalline high-k dielectric material comprises crystalline hafnium oxide and the amorphous high-k dielectric material comprises amorphous hafnium oxide (as described in [0021] of Lin, the high-k dielectric material is HfO2).
Regarding claim 28, Lin teaches a semiconductor device (900 in Figs. 2 & 9 of Lin), comprising:
an isolation layer (215 in Fig. 2 of Lin) on a substrate (201);
a channel structure (portion of fin 213 extending above the isolation layer 215 and is overlapped by the gate) on the substrate extending above the isolation layer;
a gate dielectric layer (903, as shown in Fig. 2 of Lin, this gate dielectric layer 903 is on the top surface of the fin 213 as well as the two sidewalls 213B of the fin) on the channel structure and the isolation layer, wherein
the gate dielectric layer is on top surfaces of the channel structure and the isolation layer (as shown in Fig. 2 of Lin),
the gate dielectric layer comprises sidewall portions (portions of 903 in the vicinity of sidewalls of the fin 213) and a top portion (portion of 903 on top surface of the fin 213) over the sidewall portions;
the top portion is crystalline and comprises a crystalline high-k dielectric material (903B is crystalline, as described in [0062]), and
the sidewall portions (the sidewall portions of 903 also include layers 903A1 in Fig. 9 of Lin) are amorphous and comprise an amorphous high-k dielectric material (as stated in [0062] of Lin), wherein the crystalline high-k dielectric material and the amorphous high-k dielectric material comprise a same high-k dielectric material (as described in [0021] of Lin, the high-k dielectric material is HfO2); and
a gate structure (617) on the gate dielectric layer over the channel structure and the isolation layer.
Regarding claim 31, Lin teaches all limitations of the semiconductor device of claim 28, and also teaches wherein a thickness of the gate dielectric layer ranges from about 0.1 nm to about 5 nm (as described in [0022] of Lin).
Regarding claim 37, Lin teaches all limitations of the semiconductor device of claim 28, and also teaches wherein the crystalline high-k dielectric material comprises crystalline hafnium oxide and the amorphous high-k dielectric material comprises amorphous hafnium oxide (as described in [0021] of Lin, the high-k dielectric material is HfO2).
Allowable Subject Matter
Claims 5-8, 25-27, 32, 34, 36 and 38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art of record does not disclose or fairly suggest a semiconductor structure comprising “an additional gate dielectric layer between the gate dielectric layer and the gate structure, wherein a top portion of the additional gate dielectric layer is crystalline and comprises an additional crystalline high-k dielectric material different from the crystalline high-k dielectric material” along with other limitations of claim 1.
Regarding claim 25, the prior art of record does not disclose or fairly suggest a semiconductor device comprising “an additional gate dielectric layer between the gate dielectric layer and the gate structure, wherein a top portion of the additional gate dielectric layer is crystalline and comprises an additional crystalline high-k dielectric material different from the crystalline high-k dielectric material” along with other limitations of claim 21.
Regarding claim 32, the prior art of record does not disclose or fairly suggest a semiconductor device comprising “an additional gate dielectric layer between the gate dielectric layer and the gate structure, wherein: a top portion of the additional gate dielectric layer is crystalline and comprises an additional crystalline high-k dielectric material; the additional crystalline high-k dielectric material is different from the crystalline high-k dielectric material; and a thickness of the gate dielectric layer is greater than a thickness of the additional gate dielectric layer” along with other limitations of claim 28.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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