DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, and embodiment I in Figs. 2, 5-21 in the reply filed on 12/12/2025 is acknowledged. Claims 9-20 have been canceled. Claims 21-32 are added.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 21-24, 28-29 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2021/0020786 A1).
Regarding claim 1, Lin teaches a semiconductor structure (900 in Figs. 2 & 9 of Lin), comprising:
a fin structure (613 in Fig. 9 or 213 in Fig. 2) on a substrate (201);
a gate dielectric layer (903) on the fin structure, wherein a top portion (903B. The term “top” is part of the label, and/or relative to any other element, for example, relative to the fin, the portion 903B is on top of the fin) of the gate dielectric layer is crystalline (903B is crystalline) and comprises a crystalline high-k dielectric material (as stated in [0062]); and
a gate structure (617) on the gate dielectric layer.
Regarding claim 2, Lin teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein sidewall portions of the gate dielectric layer are crystalline (903A2 in Fig. 9 of Lin) and comprise the crystalline high-k dielectric material (as stated in [0062] of Lin).
Regarding claim 3, Lin teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein sidewall portions (903A1 in Fig. 9 of Lin) of the gate dielectric layer are amorphous and comprise an amorphous high-k dielectric material (as stated in [0062] of Lin).
Regarding claim 4, Lin teaches all limitations of the semiconductor structure of claim 1, and also teaches wherein a thickness of the gate dielectric layer ranges from about 0.1 nm to about 5 nm (as described in [0022] of Lin).
Regarding claim 21, Lin teaches a semiconductor device (900 in Figs. 2 & 9 of Lin), comprising:
an interfacial layer (602 in Fig. 9) on a channel structure;
a gate dielectric layer (903) on the interfacial layer, wherein a top portion (portion of 903B over the top surface of the fin) of the gate dielectric layer is crystalline (903B is crystalline) and comprises a crystalline high-k dielectric material (as stated in [0062]); and
a gate structure (617) on the gate dielectric layer over the channel structure.
Regarding claim 22, Lin teaches all limitations of the semiconductor device of claim 21, and also teaches wherein sidewall portions of the gate dielectric layer are crystalline (903A2 in Fig. 9 of Lin) and comprise the crystalline high-k dielectric material (as stated in [0062] of Lin).
Regarding claim 23, Lin teaches all limitations of the semiconductor device of claim 21, and also teaches wherein sidewall portions (903A1 in Fig. 9 of Lin) of the gate dielectric layer are amorphous and comprise an amorphous high-k dielectric material (as stated in [0062] of Lin).
Regarding claim 24, Lin teaches all limitations of the semiconductor device of claim 21, and also teaches wherein a thickness of the gate dielectric layer ranges from about 0.1 nm to about 5 nm (as described in [0022] of Lin).
Regarding claim 28, Lin teaches a semiconductor device (900 in Figs. 2 & 9 of Lin), comprising:
an isolation layer (215 in Fig. 2 of Lin) on a substrate (201);
a channel structure (portion of fin 213 extending above the isolation layer 215 and is overlapped by the gate) on the substrate extending above the isolation layer;
a gate dielectric layer (903) on the fin structure and the isolation layer, wherein the gate dielectric layer on top surfaces of the channel structure and the isolation layer is crystalline (903B) and comprises a crystalline high-k dielectric material (as stated in [0062]); and
a gate structure (617) on the gate dielectric layer over the channel structure and the isolation layer.
Regarding claim 29, Lin teaches all limitations of the semiconductor device of claim 28, and also teaches wherein the gate dielectric layer on sidewall surfaces of the channel structure is crystalline (903A2 in Fig. 9 of Lin) and comprises the crystalline high-k dielectric material (as stated in [0062] of Lin).
Regarding claim 31, Lin teaches all limitations of the semiconductor device of claim 28, and also teaches wherein a thickness of the gate dielectric layer ranges from about 0.1 nm to about 5 nm (as described in [0022] of Lin).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-8, 21, 25-28, 30 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Halliyall et al. (US 6645882 B1) in view of Lin.
Regarding claim 1, Halliyal teaches a semiconductor structure (100 in Fig. 1 of Halliyal), comprising:
an active region (112) on a substrate (102);
a gate dielectric layer (110) on the active region, wherein a top portion (layers from 110a to 110b in the gate composite dielectric layer 110) of the gate dielectric layer is crystalline (as indicated in column 10 line 40-45) and comprises a crystalline high-k dielectric material (hafnium oxide); and
a gate structure (108) on the gate dielectric layer.
But Halliyal does not teach that the active region is a fin structure.
Lin teaches a finfet structure (Fig. 2 of Lin formed by method in Figs. 6A-6D of Lin) which comprises: a fin structure (213 in Fig. 2, which is 613 in Figs. 6A-6D) on a substrate (201); a gate dielectric layer (603 in Fig. 6D) on the fin structure; and a gate structure (617 in Fig. 6D) on the gate dielectric layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the active region of Halliyal a fin structure as disclosed by Lin in order to reduce the size of the device.
As incorporated, the gate dielectric layer 110 of Halliyal covers the top and sidewall surfaces of the fin structure 213/613, and has a top portion over the top surface of the fin structure and two sidewall portions over the sidewalls of the fin structure.
Regarding claim 5, Halliyal in view of Lin teaches all limitations of the semiconductor structure of claim 1, and further comprising an additional gate dielectric layer (upper 110rp and 110c of Halliyal) between the gate dielectric layer and the gate structure, wherein a top portion (portion of 110c that is over the top surface of the fin structure) of the additional gate dielectric layer is crystalline (as indicated in column 10 line 40-45 of Halliyal) and comprises an additional crystalline high-k dielectric material different from the crystalline high-k dielectric material (110c of Halliyal has a different material than 110b).
Regarding claim 6, Halliyall in view of Lin teaches all limitations of the semiconductor structure of claim 5, and also teaches wherein sidewall portions (portion of 110c of Halliyal over the sidewall surfaces of the fin structure) of the additional gate dielectric layer are crystalline (as indicated in column 10 line 40-45 of Halliyal) and comprise the additional crystalline high-k dielectric material (material of the 110c of Halliyal).
Regarding claim 7, Halliyall in view of Lin teaches all limitations of the semiconductor structure of claim 5, and also teaches wherein sidewall portions (portion of 110rp of Halliyal over the sidewall surfaces of the fin structure) of the additional gate dielectric layer are amorphous (as indicated in column 10 line 52 of Halliyal) and comprise an additional amorphous high-k dielectric material (material of 110rp).
Regarding claim 8, Halliyall in view of Lin teaches all limitations of the semiconductor structure of claim 5, and also teaches wherein a ratio of a thickness of the gate dielectric layer to a thickness of the additional gate dielectric layer ranges from about 5 to about 15 (as described in column 7 lines 26-27 of Halliyal, there are six alternating sub-layers in the gate composite dielectric layer; the top layer and its reaction product layer is identified as the additional layer where the lower layers are the gate dielectric layer. So the thickness of the additional gate dielectric layer is about 1/5th of the thickness of the gate dielectric layer. The range of the prior art either lies inside or overlaps with the claimed range, a prima facie case of obviousness exists. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997)).
Regarding claim 21, Halliyal teaches a semiconductor device (100 in Fig. 1 of Halliyal), comprising:
a channel structure (112 in Fig. 1);
a gate dielectric layer (110a to 110b), wherein a top portion (layer 110b in the gate composite dielectric layer 110) of the gate dielectric layer is crystalline (as indicated in column 10 line 40-45) and comprises a crystalline high-k dielectric material (hafnium oxide); and
a gate structure (108) on the gate dielectric layer over the channel structure.
But Halliyal does not teach that the semiconductor structure comprising: an interfacial layer on the channel structure; and the gate dielectric layer is on the interfacial layer.
Lin teaches a finfet structure (Fig. 2 of Lin formed by method in Figs. 6A-6D of Lin) which comprises: an interfacial layer (602 in Fig. 6A) on a channel structure (fin 613); a fin structure (213 in Fig. 2, which is 613 in Figs. 6A-6D) on a substrate (201); a gate dielectric layer (603 in Fig. 6D) on the fin structure; and a gate structure (617 in Fig. 6D) on the gate dielectric layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the active region of Halliyal a fin structure as disclosed by Lin in order to reduce the size of the device.
As incorporated, the gate dielectric layer 110 of Halliyal covers the top and sidewall surfaces of the fin structure 213/613, and has a top portion over the top surface of the fin structure and two sidewall portions over the sidewalls of the fin structure (as shown in Fig. 2 of Lin).
Regarding claim 25, Halliyal in view of Lin teaches all limitations of the semiconductor device of claim 21, and further comprising an additional gate dielectric layer (upper 110rp and 110c of Halliyal) between the gate dielectric layer and the gate structure, wherein a top portion (portion of 110c that is over the top surface of the fin structure) of the additional gate dielectric layer is crystalline (as indicated in column 10 line 40-45 of Halliyal) and comprises an additional crystalline high-k dielectric material different from the crystalline high-k dielectric material (110c of Halliyal has a different material than 110b).
Regarding claim 26, Halliyal in view of Lin teaches all limitations of the semiconductor device of claim 25, and also teaches wherein the crystalline high-k dielectric material comprises hafnium oxide (as taught in column 9 line 6 of Halliyal) but does not teach that the additional crystalline high-k dielectric material comprises zirconium oxide.
However, Halliyal teaches that the selection of material composition, number and thickness of the layers of both the high-k dielectric material and standard k dielectric material can be modified to suit the desired gate composite dielectric layer (column 10 lines 24-39 of Halliyal). Halliyal also discloses examples in which the high-k dielectric materials can be different from layer to layer (see column 8 lines 46-51 of Halliyal).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the additional high-k dielectric material from zirconium oxide in order to have appropriate k value for the desired transistor.
Regarding claim 27, Halliyal in view of Lin teaches all limitations of the semiconductor device of claim 25, and also teaches wherein a thickness of the gate dielectric layer is greater than a thickness of the additional gate dielectric layer (thickness of layers 110a-100b is greater than the thickness of the top layer 110rp and 110c).
Regarding claim 28, Halliyal teaches a semiconductor device (100 in Fig. 1 of Halliyal), comprising:
a channel structure (112 in Fig. 1) on a substrate (102);
a gate dielectric layer (110a to 110b) on the fin structure, wherein the gate dielectric layer on top surfaces of the channel structure (as shown in Fig. 1) is crystalline (as indicated in column 10 line 40-45) and comprises a crystalline high-k dielectric material (hafnium oxide); and
a gate structure (108) on the gate dielectric layer over the channel structure.
But Halliyal does not teach the semiconductor device comprising: an isolation layer on a substrate; the channel structure extending above the isolation layer; the gate dielectric layer is on and the isolation layer, wherein the gate dielectric layer is on top surface of the isolation layer; and the gate structure is over the isolation layer.
Lin teaches a finfet structure (Fig. 2 of Lin formed by method in Figs. 6A-6D of Lin) which comprises: an interfacial layer (602 in Fig. 6A) on a channel structure (fin 613); a fin structure (213 in Fig. 2, which is 613 in Figs. 6A-6D) on a substrate (201); a gate dielectric layer (603 in Fig. 6D) on the fin structure; and a gate structure (617 in Fig. 6D) on the gate dielectric layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the active region of Halliyal a fin structure as disclosed by Lin in order to reduce the size of the device.
As incorporated, the gate dielectric layer 110 of Halliyal covers the top and sidewall surfaces of the fin structure 213/613, and has a top portion over the top surface of the fin structure and two sidewall portions over the sidewalls of the fin structure (as shown in Fig. 2 of Lin). The gate structure and gate dielectric layer are also over the top surface of the isolation structure (as shown in Fig. 2 of Lin).
Regarding claim 30, Halliyal in view of Lin teaches all limitations of the semiconductor device of claim 28, and also teaches wherein the gate dielectric layer on sidewall surfaces of the channel structure is amorphous and comprises an amorphous high-k dielectric material (110rp between 110a and 110b in Fig. 1 of Halliyal is also on sidewall surfaces of the fin structure. This 110rp is amorphous, as described in column 10 lines 50-54 of Halliyal).
Regarding claim 32, Halliyal in view of the semiconductor device of claim 28, and further comprising an additional gate dielectric layer (upper 110rp and 110c of Halliyal) between the gate dielectric layer and the gate structure, wherein:
a top portion (portion of 110c of Halliyal over the top surface of the fin structure of Lin) of the additional gate dielectric layer is crystalline and comprises an additional crystalline high-k dielectric material (as indicated in column 10 line 40-45 of Halliyal);
the additional crystalline high-k dielectric material is different from the crystalline high-k dielectric material (110c of Halliyal has a different material than 110b); and
a thickness of the gate dielectric layer is greater than a thickness of the additional gate dielectric layer (thickness of layers 110a-100b is greater than the thickness of the top layer 110rp and 110c).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898