DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 6/25/2026. Claims 1-17 & 19-21 are pending in this application. Claim 18 is canceled. Claim 21 is new.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1, 3-5, 7-17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US 2020/0227429) in view of Karda et al. (US 2021/0384354).
Re claims 1, 11 & 16, Ji teaches, under BRI, Figs. 1, 3, 7K-L & 8A-B, [0023, 0027, 0036, 0028, 0041, 0042, 0044, 0063, 0123, 0124, 0126], a system (802) comprising:
-a host apparatus (810) (Figs. 8A-B) including a storage controller (816) operatively coupled to one or more memory modules (820) having at least one three-dimensional (3D) memory device, comprising,
-a semiconductor substrate including a plurality of layers (Fig. 1);
-a plurality of wordlines (WL 140) formed in a 3D stack of multiple tiers;
-a plurality of vertical wordline drivers (vertical string drivers 834), each comprising,
a vertical transistor structure (170) formed in the semiconductor substrate (of circuit 100, 200 or 300 or within area of substrate 110) comprising a gate all around (GAA) structure or a double-gate structure (e.g., 320, 332, 334, 360, 340, Figs. 3 & 7L) including,
a gate oxide (consider outermost 334), the gate oxide forming an outer member or wall defining and surrounding an internal pillar space (defined between outermost 334) (Figs. 3 & 7K);
a channel (332), adjacent to the gate oxide (outermost 334);
a liner layer (360 & inside 334), adjacent to the channel (332);
a dielectric fill material (340) at least partially filling the internal pillar space created by the outer member or wall (of outermost 334);
wherein the liner layer (360 & inside 334) is disposed between the channel (332) and the dielectric fill material (340), and in direct physical contact with the channel (332) and the dielectric fill material (340);
an upper contact (160), electrically coupled to the channel; and
a lower contact (130 and/or 162), electrically coupled to a respective wordline.
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Ji does not explicitly teach an amorphous IGZO (Indium Gallium Zinc Oxide) channel.
Karda teaches a IGZO (Indium Gallium Zinc Oxide) channel (InGaZnO 128) [0080].
As taught by Karda, one of ordinary skill in the art would utilize & modify the above teaching into Ji to obtain an amorphous IGZO (Indium Gallium Zinc Oxide) channel as claimed, because it aids in achieving a low-cost device having increased improvement & on-state current properties. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Karda in combination with Ji due to above reason.
Re claim 3, Ji teaches, Figs. 2-3, 7B, the vertical transistor structure comprises a generally cylindrical shape having a straight sidewall.
Re claim 4, in combination cited above, Ji teaches, under BRI, Figs. 2-3, 7B-J, the vertical transistor structure comprises pairs of walls deposed opposite of one another (Fig. 7B), each wall comprising an outer portion further include the gate oxide (outermost 334), a middle portion further include the amorphous IGZO channel (consider 332) (see Karda’s teaching), and an inner portion further including the liner layer (360 & inside 334), the walls being angled or straight.
Re claim 5, Ji teaches, Figs. 1-3, 7C, the semiconductor substrate includes a plurality of stacked layers including a layer of polysilicon comprising a gate (320) that is in contact with a portion of the gate oxide (334).
Re claim 7, Ji teaches, Figs. 1 & 8a, [0025], the vertical transistor structure is employed (e.g., as intended use) as a wordline driver (string driver) in a three-dimensional (3D) NAND device.
Re claim 8, in combination cited above, Ji teaches, Figs. 1 & 3, a metal contact (160 and/or 352) disposed above and electrically coupled to the amorphous IGZO channel (332) (see Karda’s teaching) (see also Karda’s Fig. 1K, upper contact 136).
Re claim 9, in combination cited above, Ji teaches, Figs. 1 & 3, a wordline contact (at 140) disposed below the amorphous IGZO channel (332 of 170) and electrically coupling the amorphous IGZO channel (332) to a respective wordline (140) formed in the semiconductor substrate.
Re claim 10, in combination cited above, Karda teaches, under BRI, Fig. 1K, [0028] a bottom plug contact (104) comprising a metallic alloy disposed in the vertical transistor structure.
Re claim 12, Ji teaches the 3D memory device comprises a 3D NAND memory device [0025].
Re claim 13, Ji teaches, Figs. 1-3, 7C, the plurality of layers in the semiconductor substrate includes a polysilicon layer (320) that is in contact with the gate oxide (334) and is used as a gate.
Re claim 14, Ji teaches, Figs. 2-3, the vertical transistor structure comprises a pillar having a conical frustum shape or a cylindrical shape with a straight sidewall (Figs. 2-3, 7B).
Re claim 15, in combination cited above, Ji teaches, under BRI, Figs. 2-3, 7B-J, the vertical transistor structure comprises pairs of walls deposed opposite of one another (Fig. 7B), each wall comprising an outer portion further including the gate oxide (334), a middle portion further including the amorphous IGZO channel (consider 332) (see Karda’s teaching), and an inner portion further including the liner layer (360 & inside 334), the walls being angled or straight.
Re claim 17, Ji teaches, Fig. 10, [0140, 0141], the host apparatus comprises a system on a chip (SoC) (1000) or System on Package (SoP) including a processor (1010) operatively coupled to the storage controller (1022).
Re claim 19, Ji teaches, Figs. 2-3, the vertical transistor structure comprises a pillar having a conical frustum shape or a cylindrical shape with a straight sidewall (Figs. 2-3, 7B).
3. Claims 1, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US 2020/0227429) in view of Goda et al. (US 2021/0202751).
Re claims 1, 11 & 16, Ji teaches, under BRI, Figs. 1, 3, 7K-L & 8A-B, [0023, 0027, 0036, 0028, 0041, 0042, 0044, 0063, 0123, 0124, 0126], a system (802) comprising:
-a host apparatus (810) (Figs. 8A-B) including a storage controller (816) operatively coupled to one or more memory modules (820) having at least one three-dimensional (3D) memory device, comprising,
-a semiconductor substrate including a plurality of layers (Fig. 1);
-a plurality of wordlines (WL 140) formed in a 3D stack of multiple tiers;
-a plurality of vertical wordline drivers (vertical string drivers 834), each comprising,
a vertical transistor structure (170) formed in the semiconductor substrate (of circuit 100, 200 or 300 or within area of substrate 110) comprising a gate all around (GAA) structure or a double-gate structure (e.g., 320, 332, 334, 360, 340, Figs. 3 & 7L) including,
a gate oxide (consider outermost 334), the gate oxide forming an outer member or wall defining and surrounding an internal pillar space (defined between outermost 334);
a channel (332), adjacent to the gate oxide (outermost 334);
a liner layer (360 & inside 334), adjacent to the channel (332);
a dielectric fill material (340) at least partially filling the internal pillar space created by the outer member or wall (of outermost 334);
wherein the liner layer (360 & inside 334) is disposed between the channel (332) and the dielectric fill material (340), and in direct physical contact with the channel (332) and the dielectric fill material (340);
an upper contact (160), electrically coupled to the channel; and
a lower contact (130 and/or 162), electrically coupled to a respective wordline.
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Ji does not explicitly teach an amorphous IGZO (Indium Gallium Zinc Oxide) channel.
Goda teaches amorphous IGZO (Indium Gallium Zinc Oxide) channel (e.g., amorphous IGZO) [0038].
As taught by Goda, one of ordinary skill in the art would utilize & modify the above teaching into Ji to obtain an amorphous IGZO (Indium Gallium Zinc Oxide) channel as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Goda in combination with Ji due to above reason.
4. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ji as modified by Karda as applied to claim 1 above, and further in view of CN 208284477 (“CN77”) (English translation provided with IDS 2/28/2024).
The teachings of Ji/Karda have been discussed above.
Re claim 2, Ji/Karda does not explicitly teach the vertical transistor structure comprises a conical frustum shape, and the internal pillar space has the conical frustum shape.
CN77 teaches, Figs. 3a-c, the vertical transistor structure (T) comprises a conical frustrum shape, and the internal pillar space (holding 300) has the conical frustum shape.
As taught by CN77, one of ordinary skill in the art would utilize & modify the above teaching to obtain the vertical transistor structure comprises a conical frustrum shape & the internal pillar space has the conical frustum shape as claimed, because it aids in achieving a desired shape of vertical memory transistor, and improving the performance of the vertical memory transistor. Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by CN77 in combination with Ji/Karda due to above reason.
5. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ji as modified by Karda as applied to claim 1 above, and further in view of Min (US 9,589,960).
The teachings of Ji/Karda have been discussed above.
Re claim 6, Ji/Karda does not explicitly teach the liner layer comprises an Aluminum oxide or Hafnium oxide.
Min teaches, Fig. 2A, col. 7, last par., the liner layer (107) comprises an Aluminum oxide or Hafnium oxide (e.g., Al2O3, HfO2).
As taught by Min, one of ordinary skill in the art would utilize & modify the above teaching to obtain the liner layer comprising an Aluminum oxide or Hafnium oxide as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Ji/Karda due to above reason.
Allowable Subject Matter
6. Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
The claims are amended with newly added features, interpretation & rejection under Ji are also changed to meet the current claims & newly added features. Under BRI, shown in Ji’s Figs. 3 & 7K, junction 360 & inside layer 334 can be considered as the claimed liner layer and external/outermost layer of 334 can be considered as outer member or wall that defines internal pillar space, and the junction 360 & inside layer 334 between & in direct physical contact channel 332 & dielectric fill material 340.
Given a broadest reasonable interpretation, Ji, Karda & Goda meet the claimed invention. Details included in the above rejection.
Double Patenting Rejection is currently withdrawn due to claim amendment.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/7/26
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