DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Objections
2. The claims are objected because of the following reasons:
Re claims 2, 14 & 19, line 2: delete “frustrum” and insert --frustum--.
Re claim 10, line 2: in between “vertical structure” insert --transistor--.
Re claim 16, line 2: in front of “host”, delete “A” and --a--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claims 1, 11 & 16 each cites “a dielectric fill material” is not clear. This limitation appears to be a stand-alone feature because the claims do not clearly specify any positional relationship between the dielectric fill material and other claimed features. Fig. 3, silicon oxide 330 will be used to consider “dielectric fill material”.
Claims 4, 15 & 20 each cites “an outer portion of gate oxide, a middle portion of amorphous IGZO, and an inner portion of liner material” are not clear, because each clam does not clearly specify whether these claimed features are same or different from a gate oxide, an amorphous IGZO channel & a liner cited in claims 1, 11 & 16. Same materials will be considered for examination.
Claim 10 cites “a bottom plug contact comprising a metallic alloy disposed the vertical structure” is not clear. The claim appears not being completed, e.g., disposed the vertical structure; and the claim does not clearly specify any particular position of the bottom plug contact and how it relates with other claimed features cited in claim 1. Fig. 10, bottom plug contact 1004 will be used to consider “bottom plug contact”.
Claims 2-3, 5-9, 12-14 & 17-20 are rejected as being dependent on claims 1, 11 & 16.
Applicant is suggested to revise and clarify the claims to avoid any further confusions.
For best understanding and examination purpose, the claims will be best considered based on drawings (e.g. Figs. 3 & 10), disclosure, and/or any applicable prior arts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 3-5 and 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US 2020/0227429) in view of Karda et al. (US 2021/0384354).
Re claims 1, 11 & 16, Ji teaches, under BRI, Figs. 1-3, 6L, 7L & 8A-B, [0023, 0027, 0036, 0028, 0041, 0042, 0044, 0063, 0123, 0124, 0126], a system (802) comprising:
-a host apparatus (810) (Figs. 8A-B) including a storage controller (816) operatively coupled to one or more memory modules (820) having at least one three-dimensional (3D) memory device, comprising,
-a semiconductor substrate including a plurality of layers (Fig. 1);
-a plurality of wordlines (WL 140) formed in a 3D stack of multiple tiers;
-a plurality of vertical wordline drivers (vertical string drivers 834), each comprising,
-a vertical wordline driver (866) comprising each comprising:
a vertical transistor structure (170) formed in the semiconductor substrate (of circuit 100, 200 or 300 or within area of substrate 110) comprising a gate all around (GAA) structure or a double-gate structure (e.g., 320, 332, 334, 360, 340, Figs. 3 & 7L) including,
an outer member or wall comprising a gate oxide (334);
a channel (332), adjacent to the gate oxide (334);
a liner (360), adjacent to the channel (332);
a dielectric fill material (340);
an upper contact (160), electrically coupled to the channel; and
a lower contact (130 and/or 162), electrically coupled to a respective wordline.
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Ji does not explicitly teach an amorphous IGZO (Indium Gallium Zinc Oxide) channel.
Karda teaches a IGZO (Indium Gallium Zinc Oxide) channel (InGaZnO 128) [0080].
As taught by Karda, one of ordinary skill in the art would utilize & modify the above teaching into Ji to obtain an amorphous IGZO (Indium Gallium Zinc Oxide) channel as claimed, because it aids in achieving a low-cost device having increased improvement & on-state current properties. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Karda in combination with Ji due to above reason.
Re claim 3, Ji teaches, Figs. 2-3, 7B, the vertical transistor structure comprises a generally cylindrical shape having a straight sidewall.
Re claim 4, in combination cited above, Ji teaches, under BRI, Figs. 2-3, 7B-J, the vertical transistor structure comprises pairs of walls deposed opposite of one another (Fig. 7B), each wall comprising an outer portion of gate oxide (334), a middle portion of amorphous IGZO (consider 332) (see Karda’s teaching), and an inner portion of liner material (760), the walls being angled or straight.
Re claim 5, Ji teaches, Figs. 1-3, 7C, the semiconductor substrate includes a plurality of stacked layers including a layer of polysilicon comprising a gate (320) that is in contact with a portion of the gate oxide (334).
Re claim 7, Ji teaches, Figs. 1 & 8a, [0025], the vertical transistor structure is employed (e.g., as intended use) as a wordline driver (string driver) in a three-dimensional (3D) NAND device.
Re claim 8, in combination cited above, Ji teaches, Figs. 1 & 3, a metal contact (160 and/or 352) disposed above and electrically coupled to the amorphous IGZO channel (332) (see Karda’s teaching) (see also Karda’s Fig. 1K, upper contact 136).
Re claim 9, in combination cited above, Ji teaches, Figs. 1 & 3, a wordline contact (at 140) disposed below the amorphous IGZO channel (332 of 170) and electrically coupling the amorphous IGZO channel (332) to a respective wordline (140) formed in the semiconductor substrate.
Re claim 10, in combination cited above, Karda teaches, under BRI, Fig. 1K, [0028] a bottom plug contact (104) comprising a metallic alloy disposed the vertical structure.
Re claim 12, Ji teaches the 3D memory device comprises a 3D NAND memory device [0025].
Re claim 13, Ji teaches, Figs. 1-3, 7C, the plurality of layers in the semiconductor substrate includes a polysilicon layer (320) that is in contact with the gate oxide (334) and is used as a gate.
Re claim 14, Ji teaches, Figs. 2-3, the vertical transistor structure comprises a pillar having a conical frustrum shape or a cylindrical shape with a straight sidewall (Figs. 2-3, 7B).
Re claim 15, in combination cited above, Ji teaches, under BRI, Figs. 2-3, 7B-J, the vertical transistor structure comprises pairs of walls deposed opposite of one another (Fig. 7B), each wall comprising an outer portion of gate oxide (334), a middle portion of amorphous IGZO (consider 332) (see Karda’s teaching), and an inner portion of liner material (760), the walls being angled or straight.
Re claim 17, Ji teaches, Fig. 10, [0140, 0141], the host apparatus comprises a system on a chip (SoC) (1000) or System on Package (SoP) including a processor (1010) operatively coupled to the storage controller (1022).
Re claim 18, Ji teaches the at least one 3D memory comprises a 3D NAND memory device [0025].
Re claim 19, Ji teaches, Figs. 2-3, the vertical transistor structure comprises a pillar having a conical frustrum shape or a cylindrical shape with a straight sidewall (Figs. 2-3, 7B).
Re claim 20, in combination cited above, Ji teaches, under BRI, Figs. 2-3, 7B-J, the vertical transistor structure comprises pairs of walls deposed opposite of one another (Fig. 7B), each wall comprising an outer portion of gate oxide (334), a middle portion of amorphous IGZO (consider 332) (see Karda’s teaching), and an inner portion of liner material (760), the walls being angled or straight.
5. Claims 1, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US 2020/0227429) in view of Goda et al. (US 2021/0202751).
Re claims 1, 11 & 16, Ji teaches, under BRI, Figs. 1-3, 6L, 7L & 8A-B, [0023, 0027, 0036, 0028, 0041, 0042, 0044, 0063, 0123, 0124, 0126], a system (802) comprising:
-a host apparatus (810) (Figs. 8A-B) including a storage controller (816) operatively coupled to one or more memory modules (820) having at least one three-dimensional (3D) memory device, comprising,
-a semiconductor substrate including a plurality of layers (Fig. 1);
-a plurality of wordlines (WL 140) formed in a 3D stack of multiple tiers;
-a plurality of vertical wordline drivers (vertical string drivers 834), each comprising,
-a vertical wordline driver (866) comprising each comprising:
a vertical transistor structure (170) formed in the semiconductor substrate (of circuit 100, 200 or 300 or within area of substrate 110) comprising a gate all around (GAA) structure or a double-gate structure (e.g., 320, 332, 334, 360, 340, Figs. 3 & 7L) including,
an outer member or wall comprising a gate oxide (334);
a channel (332), adjacent to the gate oxide (334);
a liner (360), adjacent to the channel (332);
a dielectric fill material (340);
an upper contact (160), electrically coupled to the channel; and
a lower contact (130 and/or 162), electrically coupled to a respective wordline.
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Ji does not explicitly teach an amorphous IGZO (Indium Gallium Zinc Oxide) channel.
Goda teaches amorphous IGZO (Indium Gallium Zinc Oxide) channel (e.g., amorphous IGZO) [0038].
As taught by Goda, one of ordinary skill in the art would utilize & modify the above teaching into Ji to obtain an amorphous IGZO (Indium Gallium Zinc Oxide) channel as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Goda in combination with Ji due to above reason.
6. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ji as modified by Karda as applied to claim 1 above, and further in view of CN 208284477 (“CN77”) (English translation provided with IDS 2/28/2024).
The teachings of Ji/Karda have been discussed above.
Re claim 2, Ji/Karda does not explicitly teach the vertical transistor structure comprises a conical frustrum shape.
CN77 teaches, Figs. 3a-c, the vertical transistor structure (T) comprises a conical frustrum shape.
As taught by CN77, one of ordinary skill in the art would utilize & modify the above teaching to obtain the vertical transistor structure comprises a conical frustrum shape as claimed, because it aids in achieving a desired shape of vertical memory transistor, and improving the performance of the vertical memory transistor. Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by CN77 in combination with Ji/Karda due to above reason.
7. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ji as modified by Karda as applied to claim 1 above, and further in view of Min (US 9,589,960).
The teachings of Ji/Karda have been discussed above.
Re claim 6, Ji/Karda does not explicitly teach the liner comprises an Aluminum oxide or Hafnium oxide.
Min teaches, Fig. 2A, col. 7, last par., the liner (107) comprises an Aluminum oxide or Hafnium oxide (e.g., Al2O3, HfO2).
As taught by Min, one of ordinary skill in the art would utilize & modify the above teaching to obtain the liner comprises an Aluminum oxide or Hafnium oxide as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Min in combination with Ji/Karda due to above reason.
Double Patenting
8. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13-23 of copending Application No. 18/542,337 (reference application) and/or in view of Ji et al. (US 2020/0227429). Although the claims at issue are not identical, they are not patentably distinct from each other because they both claim and require similar claimed features such as 3D memory device, wordlines, vertical wordline drivers, GAA or double gate structure, gate oxide, IGZO channel, line and dielectric fill material, upper and lower contacts, etc., and/or Ji teaches system and host apparatus including a storage controller (Fig. 8a), specially applied in claim 16 of the current application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Current Application 18/188,391
1. A vertical wordline driver comprising:
a vertical transistor structure formed in a semiconductor substrate comprising a gate all around (GAA) structure or a double-gate structure including,
an outer member or wall comprising a gate oxide;
an amorphous IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide;
a liner, adjacent to the amorphous IGZO channel; and
a dielectric fill material.
11. A three-dimensional (3D) memory device, comprising:
a semiconductor substrate including a plurality of layers;
a plurality of wordlines formed in a 3D stack of multiple tiers;
a plurality of vertical wordline drivers, each comprising,
a vertical transistor structure formed in the semiconductor substrate comprising a gate all around (GAA) structure or a double-gate structure including,
an outer member or wall comprising a gate oxide;
an amorphous IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide;
a liner, adjacent to the amorphous IGZO channel;
a dielectric fill material;
an upper contact, electrically coupled to the amorphous IGZO channel; and
a lower contact, electrically coupled to a respective wordline.
18/542,337
13. A vertical wordline driver comprising:
a vertical transistor structure formed in a semiconductor substrate and comprising a gate all around (GAA) structure or a double-gate structure and including,
an outer member or wall comprising a gate oxide;
an IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide;
a channel liner, adjacent to the IGZO channel, comprising a high material and forming a hermetically sealed IGZO channel of the vertical wordline driver; and
a dielectric fill material,
wherein the vertical wordline driver supports a drive voltage of at least 10 volts.
wherein the vertical wordline driver supports a drive voltage of at least 10 volts.
19. A three-dimensional (3D) memory device, comprising:
a semiconductor substrate including a plurality of layers;
a plurality of wordlines formed in a 3D stack of multiple tiers;
a plurality of vertical wordline drivers, each comprising,
a vertical transistor structure formed in a semiconductor substrate and comprising a gate all around (GAA) structure or a double-gate structure including,
an outer member or wall comprising a gate oxide;
an IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide;
a channel liner, adjacent to the IGZO channel, comprising a high-k material and forming a hermetically sealed IGZO channel;
a dielectric fill material;
an upper contact, electrically coupled to the hermetically sealed IGZO channel; and
a lower contact, electrically coupled to a respective wordline,
wherein the vertical wordline driver supports a drive voltage of at least 10 volts.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/6/26