DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 02/15/2026 has been entered. Claims 1-2 and 4-44, remain pending in the application. Applicant’s amendments have overcome each and every 112(b) rejections previously set forth in the Non-Final Office Action mailed on 11/21/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 6, 9 and 10 rejected under 35 U.S.C. 103 as being unpatentable over Hu et al., (United States Patent Application Publication Number, US 2019/0164914 A1) hereinafter referenced as Hu, in view of Paul et al., (United States Patent Application Publication Number, US 2021/0327826 A1) hereinafter referenced as Paul.
Regarding claim 1, Hu teaches a semiconductor device, comprising: a semiconductor substrate (Fig.2b, element #122) having a circuit region (Fig.2b, region to the left side of element #element #134) and a seal ring region surrounding the circuit region (Fig.2b, element #136, paragraph [0039], rows 15-17); a first dielectric layer disposed over the seal ring region, wherein the first dielectric layer has a first dielectric constant (Fig.2b, element #140 can be SiN, paragraph [0042], rows 4-7); a second dielectric layer disposed between the semiconductor substrate and the first dielectric layer (Fig.2b, element #128, paragraph [0030], rows 9-11), wherein the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant (element #128 has dielectric constant as low as 2.8, paragraph [0030], rows 9-11, and element #140 can be SiN, paragraph [0042], rows 4-7); and a conductive seal ring structure disposed in the seal ring region (Fig.2b, formed by elements #132A, #132B, #132C, #134A, #134B and #134C), wherein the conductive seal ring structure comprises: a first seal ring portion embedded in the first dielectric layer (Fig.2b, element #132C and #134C), wherein the first seal ring portion comprises first patterns (Fig.2b, element #132C and #134C form a first pattern) and a second seal ring portion disposed directly below the first seal ring portion and embedded in the second dielectric layer (Fig.2b, second seal ring region is formed by elements #132A and #134A and is embedded inside layer #128), wherein the second seal ring portion comprises at least a second continuous pattern (Fig.2b, elements #132A and #134A form a continuous ring, paragraph [0041], rows 13-14).
Hu does not teach the first patterns are arranged periodically and discontinuously. Paul teaches the first patterns are arranged periodically and discontinuously (Fig.8, elements #M4, and form a first patterns arranged periodically discontinuously, see Fig.1 for a top view, and are located in a first seal ring portion, embedded in the first dielectric layer, first seal ring region is part of element #642 located above V3 vias). Note that Paul also teaches and a second seal ring portion disposed directly below the first seal ring portion and embedded in the second dielectric layer (Fig.8, second seal ring region is formed by element #M2, #M3 and V2 vias in between), wherein the second seal ring portion comprises at least a second continuous pattern (Fig.8, elements #M2, vias V2 and #M3 form a continuous pattern). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein the first seal ring portion comprises patterns arranged periodically and discontinuously. Having the seal ring portion patterns distributed periodically and discontinuously around the circuit region results in uniform stress distribution around the circuit region, where stress may occur due to the different thermal expansion coefficients of the different conductive and dielectric layers.
Regarding claim 2, the combination of Hu and Paul teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Hu further teaches the semiconductor device as claimed in claim 1, wherein the first seal ring portion comprises: a first inner ring portion surrounding the circuit region (Fig.2b, element #134C); and a first outer ring portion surrounding the first inner ring portion (Fig.2b, element #132C). Hu does not teach wherein first patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. Paul teaches wherein first patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region (Fig.1, elements #260a, b and c and elements #262a, b and c of the first inner ring portion #260 and second outer ring portion #262 respectively, are arranged periodically and in a staggered arrangement). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein first patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. As disclosed by Paul, the parallel and staggered arrangement helps prevent cracks from propagating into the circuit region.
Regarding claim 4, the combination of Hu and Paul teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection. Hu further teaches the semiconductor device as claimed in claim 2, wherein the second seal ring portion comprises: a second inner ring pattern surrounding the circuit region (Fig.2c, pattern of element #134A seen in top view, element #134A is formed similarly with #element #132A, paragraph [0036], rows 8-11 and element #132A is a continuous ring, [0041], rows 10-13); and a second outer ring pattern surrounding the second inner ring pattern (Fig.2c, pattern of element #132A seen in top view, element #132A is a continuous ring, [0041], rows 10-13), wherein each of the second inner ring pattern and the second outer ring pattern has a first width crossing the seal ring region (Fig.2c, each pattern has a width).
Hu does not teach wherein each of the second inner ring pattern and the second outer ring pattern has a first width and a second width crossing the seal ring region, wherein the first width is different from the second width. Paul teaches a second seal ring portion disposed directly below the first seal ring portion and embedded in the second dielectric layer (Fig.8, second seal ring region comprises elements #M2, #M3 and #V2), wherein the second seal ring portion comprises at least a second continuous pattern (Fig.8, elements #M2, #V2 and #M3 form a continuous pattern). Paul teaches wherein each of the second inner ring pattern and the second outer ring pattern (Fig.8, continuous patterns formed by elements #M2, #V2 and #M3 of each ring, elements #260 and #262) has a first width and a second width wherein the first width is different from the second width (elements #M2 and M3 can have different widths, paragraph [0040], rows 42-46). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein each of the second inner ring pattern and the second outer ring pattern has a first width and a second width wherein the first width is different from the second width. This increases the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Regarding claim 5, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 4 as set forth in the obviousness rejection. Paul teaches wherein each of the second inner ring pattern and the second outer ring pattern comprises: first regions having the first width; and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width (Fig.8, first regions formed by elements #M3 have the first width, and second regions formed by elements #M2 have the second width and are alternately arranged and connected, paragraph [0040], rows 42-46 ). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein each of the second inner ring pattern and the second outer ring pattern comprises: first regions having the first width; and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width. This pattern increases the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Regarding claim 6, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2, 4 and 5 as set forth in the obviousness rejection. Paul teaches wherein the first regions have a first length along the seal ring region, and the second regions have a second length along the seal ring region, wherein the first length is different from the second length (elements #M2 and M3 have different lengths, paragraphs [0057], rows 23-25). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein the first regions have a first length along the seal ring region, and the second regions have a second length along the seal ring region, wherein the first length is different from the second length. This arrangement provides design flexibility and allows increasing the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Regarding claim 9, the combination of Hu and Paul teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection. Hu further teaches the semiconductor device as claimed in claim 2, wherein the second seal ring portion comprises: a second inner ring pattern surrounding the circuit region (Fig.2c, pattern of element #134A seen in top view); and a second outer ring pattern surrounding the second inner ring pattern (Fig.2c, pattern of element #132A seen in top view), wherein the second inner ring pattern and the second outer ring pattern have a same width (paragraph [0036], rows 11-14).
Regarding claim 10, the combination of Hu and Paul teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection. Hu further teaches the semiconductor device as claimed in claim 2, wherein the second seal ring portion (Fig.2b, formed by elements #132A and #134A is embedded inside layer #128) comprises second patterns arranged continuously (Fig.2c, elements #132A and #134A are continuous rings element #134A is formed similarly with #element #132A, paragraph [0036], rows 8-11 and element #132A is a continuous ring, [0041], rows 10-13), and wherein the second seal ring portion comprises: a second inner ring portion surrounding the circuit region (Fig.2c, pattern of element #134A seen in top view, element #134A is formed similarly with #element #132A, paragraph [0036], rows 8-11 and element #132A is a continuous ring, [0041], rows 10-13); and a second outer ring portion surrounding the second inner ring portion (Fig.2c, pattern of element #132A seen in top view, element #132A is a continuous ring, [0041], rows 10-13), wherein second patterns of the second inner ring portion and the second outer ring portion are parallel with each other (Fig.2c, patterns of elements #132A and #134A are parallel).
Hu does not teach the second seal ring portion comprises second patterns arranged periodically and discontinuously and second patterns of the second inner ring portion and the second outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. Paul teaches a second seal ring portion (Fig.8, formed by elements #M2, #M3 and #V2) comprises second patterns arranged periodically and discontinuously (Fig.8, the pattern formed of elements #M2 of the second inner and second outer ring are each periodic and discontinuous) and second patterns of the second inner ring portion and the second outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region (Fig.9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose the second seal ring portion comprises second patterns arranged periodically and discontinuously and second patterns of the of the second inner ring portion and the second outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. Having the seal ring portion pattern distributed periodically around the circuit region results in uniform stress distribution, where stress may occur due to a difference in thermal expansion coefficient of the different conductive and dielectric layers. Furthermore, the parallel and staggered arrangement helps prevent cracks from propagating in the circuit region.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hu, in view of Paul, and in view of Uesugi et al., (United States Patent Application Publication Number, US 2005/0087878 A1) hereinafter referenced as Uesugi.
Regarding claim 7, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 4 as set forth in the obviousness rejection. The combination of Hu and Paul does not teach the semiconductor device as claimed in claim 4, wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region. Uesugi teaches wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region (Fig.11, elements #12m and #12n each has a linear edge and a toothed edge). The tooth edges increases the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Regarding claim 8, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 4 as set forth in the obviousness rejection, and the combination of Hu, Paul and Uesugi teaches the semiconductor device of claim 7 as set forth in the obviousness rejection. The combination of Hu and Paul does not teach the semiconductor device as claimed in claim 7, wherein the linear edge of the second inner ring pattern is close to the linear edge of the second outer ring pattern. Uesugi teaches wherein the linear edge of the second inner ring pattern is close to the linear edge of the second outer ring pattern (Fig.11, the linear edges of elements #12m and #12n are close to each other). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Uesugi and disclose wherein the linear edge of the second inner ring pattern is close to the linear edge of the second outer ring pattern. This results in a small size seal ring which increase the wafer area available for the circuit region.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hu, in view of Paul, and in view of Lu, (United States Patent Application Publication Number, US 2020/0395296 A1) hereinafter referenced as Lu.
Regarding claim 11, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 10 as set forth in the obviousness rejection. The combination of Hu and Paul does not teach the semiconductor device as claimed in claim 10, further comprising: a dielectric seal ring structure disposed in the seal ring region, wherein the dielectric seal ring structure passes through the second dielectric layer but does not pass through the first dielectric layer. Lu teaches a dielectric seal ring structure (Fig.15, elements #125 is dielectric, paragraph [0064], rows 6-8); disposed in the seal ring region (Fig.15, element #125 is disposed in the seal ring, element #170 and #190), wherein the dielectric seal ring structure passes through the second dielectric layer (Fig.15, element #125 passes through the second dielectric formed by elements #103, #105, #107, #108, #111, #112 and #115, which can all be silicate glass, paragraph [0046], rows 3-4, paragraph [0048], rows 3-5, paragraph [0050], rows 4-6, paragraph [0050], rows 9-11, paragraph [0054], rows 3-5, paragraph [0055], rows 6-8, paragraph [0057], rows 4-7) but does not pass through the first dielectric layer (Fig.15, first dielectric layer, formed by elements #116 and #119 and the dielectric pillar, element #125 can all be same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6 and paragraph [0064], row 10-11 and therefore are undistinguishable). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose the semiconductor device comprising: a dielectric seal ring structure disposed in the seal ring region, wherein the dielectric seal ring structure passes through the second dielectric layer but does not pass through the first dielectric layer. As disclosed by Lu, the dielectric structure acts as a barrier which prevents moisture for reaching the circuit region (paragraph [0089], rows 8-11).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hu, in view of Paul, Lu and in view of Tanamachi et al., (United States Patent Application Publication Number, US 2021/0313240 A1) hereinafter referenced as Tanamachi.
Regarding claim 12, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 10 as set forth in the obviousness rejection, and the combination of Hu, Paul and Lu teaches the semiconductor device of claim 11 as set forth in the obviousness rejection. The combination of Hu and Paul does not teach the semiconductor device as claimed in claim 11, wherein the dielectric seal ring structure comprises: a dielectric pillar extending from the first dielectric layer to the semiconductor substrate, wherein the dielectric pillar is a portion of the first dielectric layer; and a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate. Lu teaches wherein the dielectric seal ring structure comprises: a dielectric pillar (Fig.15, elements #125 is dielectric, paragraph [0064], rows 4-8) extending from the first dielectric layer (Fig.15, first dielectric layer, formed by elements #116 and #119 and the dielectric pillar, element #125, can all be same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6 and paragraph [0064], row 10-11 and therefore are undistinguishable) to the semiconductor substrate (Fig.15, element #125 extend up to the substrate, element #100), wherein the dielectric pillar is a portion of the first dielectric layer (as above, elements #116, #119 and #125 can be made of the same material). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose wherein the dielectric seal ring structure comprises: a dielectric pillar extending from the first dielectric layer to the semiconductor substrate, wherein the dielectric pillar is a portion of the first dielectric layer. As disclosed by Lu, the dielectric structure acts as a barrier which prevents moisture for reaching the circuit region (paragraph [0089], rows 8-11), therefore extends from top layer all the way to the substrate. Furthermore, manufacturing the pillar together with one or more dielectric layers saves processing steps and reduces costs.
The combination of Hu, Paul and Lu does not teach a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate. Tanamachi teaches a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate (Fig.29C, dielectric pillar, element #992 has a dielectric liner, element #992A, paragraph [0202], rows 6-8, in contact with the substrate formed by element #909 and #910). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tanamachi and disclose a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate. As disclosed by Tanamachi, the liner provides enhanced adhesion to the interconnect layers and the substrate (paragraph [00201], rows 5-10).
Regarding claim 13, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 10 as set forth in the obviousness rejection, and the combination of Hu, Paul and Lu teaches the semiconductor device of claim 11 as set forth in the obviousness rejection, and the combination of Hu, Paul, Lu and Tanamachi teaches the semiconductor device of claim 12 as set forth in the obviousness rejection. Tanamachi further teaches the semiconductor device as claimed in claim 12, wherein the dielectric seal ring structure surrounds the second outer ring portion (Fig.29C, element #992 surrounds the second outer ring, paragraph [0192], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tanamachi and disclose wherein the dielectric seal ring structure surrounds the second outer ring portion. As disclosed by Tanamachi, the dielectric structure lengthens the path that the moisture must take to reach the interior of the semiconductor die (paragraph [0200], rows 18-23).
Regarding claim 14, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 10 as set forth in the obviousness rejection, and the combination of Hu, Paul and Lu teaches the semiconductor device of claim 11 as set forth in the obviousness rejection, and the combination of Hu, Paul, Lu and Tanamachi teaches the semiconductor device of claim 12 as set forth in the obviousness rejection. Lu further teaches, the semiconductor device as claimed in claim 12, wherein the dielectric seal ring structure is surrounded by the second inner ring portion (Fig.16, element #124 located in region element #160 is surrounded by the second inner ring portion located inside region element #170). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose wherein the dielectric seal ring structure is surrounded by the second inner ring portion. As disclosed by Lu, the dielectric ring structure may present a barrier in order to prevent moisture from entering to the circuit region from a side (paragraph [0064], rows 14-16).
Regarding claim 15, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 10 as set forth in the obviousness rejection, and the combination of Hu, Paul and Lu teaches the semiconductor device of claim 11 as set forth in the obviousness rejection, and the combination of Hu, Paul, Lu and Tanamachi teaches the semiconductor device of claim 12 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 12, wherein the second outer ring portion surrounds the dielectric seal ring structure, and the dielectric seal ring structure surrounds the second inner ring portion (Fig.16, the second outer ring portion located inside region element #190, surrounds region element #180, where the dielectric seal ring structure, element #125, is located, and region element #180 surrounds region element #170 where the second inner ring portion is located). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose wherein the second outer ring portion surrounds the dielectric seal ring structure, and the dielectric seal ring structure surrounds the second inner ring portion. As disclosed by Lu, the dielectric ring structure may present a barrier in order to prevent moisture from entering to the circuit region from a side (paragraph [0064], rows 14-16).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hu, in view of Paul, Lu, Tanamachi and in view of Izumi et al., (Japanese Patent Application Publication Number, JP 2005260059 A) hereinafter referenced as Izumi.
Regarding claim 16, the combination of Hu and Paul teaches the semiconductor device of claims 1, 2 and 10 as set forth in the obviousness rejection, and the combination of Hu, Paul and Lu teaches the semiconductor device of claim 11 as set forth in the obviousness rejection, and the combination of Hu, Paul, Lu and Tanamachi teaches the semiconductor device of claim 12 as set forth in the obviousness rejection. The combination of Hu, Paul, Lu and Tanamachi does not teach the semiconductor device as claimed in claim 12, wherein the dielectric seal ring structure is disposed below the first seal ring portion of the conductive seal ring structure. Izumi teaches a semiconductor device wherein the dielectric seal ring structure (Fig.2, element #3, paragraph [0021], rows 1-3) is disposed below the first seal ring portion of the conductive seal ring structure (Fig.2, first seal ring portion is the top metal layer of seal ring element #5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Izumi and disclose wherein the dielectric seal ring structure is disposed below the first seal ring portion of the conductive seal ring structure. The dielectric seal ring is used to prevent moisture and cracks from propagating through the interconnect layers located below the first seal ring portion.
Claims 17, 18, 20, 21, 25, 31-34, 36 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Paul.
Regarding claim 17, Lu teaches a semiconductor device, comprising: a semiconductor substrate (Fig.15, element #100) having a circuit region (Fig.15, element #140) and a seal ring region (Fig.15, formed by elements #160, #170, #180 and #190); surrounding the circuit region (Fig.16, elements #160, #170, #180 and #190 surround element #140); a first dielectric layer disposed over the seal ring region, wherein the first dielectric layer has a first dielectric constant (Fig.15, first dielectric layer, formed by elements #116 and #119 can all be same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6, and therefore are undistinguishable); a second dielectric layer disposed between the semiconductor substrate and the first dielectric layer (Fig.15, element #125 passes through the second dielectric formed by elements #103, #105, #107, #108, #111, #112 and #115, which can all be silicon oxide, paragraph [0046], rows 3-4, paragraph [0048], rows 3-5, paragraph [0050], rows 4-6, paragraph [0050], rows 9-11, paragraph [0054], rows 3-5, paragraph [0055], rows 6-8, paragraph [0057], rows 4-7), wherein the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant (silicon oxide has a lower dielectric constant than silicon nitride); a first seal ring portion disposed in the seal ring region and embedded in the first dielectric layer (Fig.15, formed by top metal layer, element #118, is both regions, #170 and #190).
Lu does not teach wherein the first seal ring portion comprises first discontinuous patterns in a top view. Paul teaches wherein the first seal ring portion comprises first discontinuous patterns in a top view (Fig.8, elements #M4, are located in a first seal ring portion, form discontinuous patterns, see Fig.1 for a top view). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein the first seal ring portion comprises discontinuous patterns. The seal ring having discontinuous pattens may prevent current leakage and increase the reliability of the circuit region.
Lu further teaches a second seal ring portion disposed in the seal ring region and embedded in the second dielectric layer (Fig.15, portion of element #124 located below element #116, paragraph [0064], rows 4-8, is embedded in the second dielectric), wherein the second seal ring portion comprises at least a second continuous pattern in the top view (Fig.16, element #124 is located in region #160, inside recess, element #120 that is continuous and surrounds the die, paragraph [0061], rows 1-3 and 12-13).
Regarding claim 18, the combination of Lu and Paul teaches the semiconductor device of claim 17 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 17, wherein the first seal ring portion comprises: a first inner ring portion (Fig.15, top metal element #118 in region element #170) surrounding the circuit region (Fig.16, region #170 surrounds the circuit region, element #140) and a first outer ring portion (Fig.15, top metal element #118 in region element #190) surrounding the first inner ring portion (Fig.16, region #190 surrounds region, element #170).
Lu does not teach, wherein first discontinuous patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. Paul teaches wherein first patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region (Fig.1, elements #260a, b and c and elements #262a, b and c of the first inner ring portion #260 and second outer ring portion #262 respectively, are parallel and in a staggered arrangement). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein first patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. The parallel and staggered arrangement helps prevent crack propagation to the circuit region.
Regarding claim 20, the combination of Lu and Paul teaches the semiconductor device of claim 17 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 17, wherein the second seal ring portion comprises: a second inner ring pattern (Fig.15, top view pattern formed by the metal layers of element #122 minus top metal element #118) surrounding the circuit region (Fig.16, element #122 is inside region #170 which surrounds the circuit region, element #140); and a second outer ring pattern (Fig.15, top view pattern formed by the metal layers of element #123 minus the top metal element #118) surrounding the second inner ring pattern (Fig.16; element #123 is inside region #190 which surrounds region, element #170).
Lu does not teach wherein each of the second inner ring pattern and the second outer ring pattern has a first width and a second width wherein the first width is different from the second width. Paul teaches wherein each of the second inner ring pattern and the second outer ring pattern has a first width and a second width wherein the first width is different from the second width (Fig.8, patterns formed by elements #M3 have the first width, and patterns made of elements #M2 have the second paragraph [0040], rows 42-46 ). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein each of the second inner ring pattern and the second outer ring pattern has a first width and a second width wherein the first width is different from the second width. This arrangement provides design flexibility and allows increasing the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Regarding claim 21, the combination of Lu and Paul teaches the semiconductor device of claims 17 and 20 as set forth in the obviousness rejection. The combination of Lu and Paul does not teach the semiconductor device as claimed in claim 20, wherein each of the second inner ring pattern and the second outer ring pattern comprises: first regions having the first width and a first length along the seal ring region; and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region, wherein the first length is different from the second length. Paul teaches wherein each of the second inner ring pattern and the second outer ring pattern comprises: first regions having the first width and a first length along the seal ring region; and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region, wherein the first length is different from the second length ((first regions elements #M3 and second regions, elements #M2 of each second ring pattern can have different width and lengths, paragraph [0040], rows 42-46 and paragraph [0057], rows 23-25). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein each of the second inner ring pattern and the second outer ring pattern comprises: first regions having the first width and a first length along the seal ring region; and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region, wherein the first length is different from the second length. This arrangement provides design flexibility and allows increasing the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Regarding claim 25, the combination of Lu and Paul teaches the semiconductor device of claim 17 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 17, wherein the second continuous pattern passes through the second dielectric layer (Fig.15, element #124 passes through the second dielectric formed by elements #103, #105, #107, #108, #111, #112 and #115, which can all be silicate glass, paragraph [0046], rows 3-4, paragraph [0048], rows 3-5, paragraph [0050], rows 4-6, paragraph [0050], rows 9-11, paragraph [0054], rows 3-5, paragraph [0055], rows 6-8, paragraph [0057], rows 4-7) but does not pass through the first dielectric layer (Fig.15, first dielectric layer, formed by elements #116 and #119 and the dielectric pillar, element #124 can all be same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6 and paragraph [0064], row 10-11, and therefore are undistinguishable).
Regarding claim 31, Lu teaches a semiconductor device, comprising: a semiconductor substrate (Fig.15, element #100) having a circuit region (Fig.15, element #140) and a seal ring region (Fig.15, formed by elements #160, #170, #180 and #190) surrounding the circuit region (Fig.16, elements #160, #170, #180 and #190 surround element #140); a first dielectric layer disposed over the seal ring region, wherein the first dielectric layer has a first dielectric constant (Fig.15, layer formed by elements #116 and #119 can all be the same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6, and therefore are undistinguishable); a first seal ring portion disposed in the seal ring region and embedded in the first dielectric layer (Fig.15, formed by top metal layer, element #118, is both regions, #170 and #190).
Lu does not teach wherein the first seal ring portion comprises first discontinuous patterns arranged periodically. Paul teaches wherein the first seal ring portion comprises first discontinuous patterns arranged periodically (Fig.8, elements #M4, located in a first seal ring portion, form discontinuous patterns, see Fig.1 for a top view). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein the first seal ring portion comprises discontinuous patterns arranged periodically. Having the seal ring portion pattern forming discontinues patterns around the circuit region results in uniform stress distribution, where stress may occur due to the difference in thermal expansion coefficient of the different conductive and dielectric layers.
Lu further teaches a second seal ring portion disposed in the seal ring region and between the first dielectric layer and the semiconductor substrate (Fig.15, portion formed by elements #103, #105, #107, #108, #111, #112 and #115, and portions of elements #124 and #125 located below layer #116 and on top of layer #100) wherein the second seal ring portion comprises at least one closed-loop pattern (Fig.16, element #124 located in region #160 inside recess, element #120, forms a closed-loop pattern, paragraph [0061], rows 1-3 and 12-13, is made of same material, silicon nitride, as first dielectric layer #116 and #119, paragraph [0064], rows 10-11, and so indistinguishable from them; therefore it forms a pattern embedded in the second seal ring portion).
Regarding claim 32, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 31, further comprising: a second dielectric layer disposed between the semiconductor substrate and the first dielectric layer (Fig.15, second dielectric formed by elements #103, #105, #107, #108, #111, #112 and #115 which can all be silicon oxide, paragraph [0046], rows 3-4, paragraph [0048], rows 3-5, paragraph [0050], rows 4-6, paragraph [0050], rows 9-11, paragraph [0054], rows 3-5, paragraph [0055], rows 6-8, paragraph [0057], rows 4-7), wherein the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant (second dielectric is silicon oxide which has a lower dielectric constant than the first dielectric which is silicon nitride), wherein the second seal ring portion is embedded in the second dielectric layer (Fig.15, portion of element #124 below element #116, is embedded in the second dielectric layer).
Regarding claim 33, the combination of Lu and Paul teaches the semiconductor device of claims 31 and 32 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 32, wherein the first seal ring portion is electrically connected to the second seal ring portion using a via passing through the second dielectric layer (Fig.15, elements #117 connect the two portions and pass through the second dielectric layer).
Regarding claim 34, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 31, wherein the first seal ring portion comprises: a first inner ring portion (Fig.15, top metal element #118 located in region element #170) surrounding the circuit region (Fig.16, region #170 surrounds the circuit region, element #140); and a first outer ring portion (Fig.15, top metal element #118 in region element #190), surrounding the first inner ring portion (Fig.16, region #190 surrounds region, element #170).
Lu does not teach, wherein first discontinuous patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. Paul teaches wherein first patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region (Fig.1, elements #260a, b and c and elements #262a, b and c of the first inner ring portion #260 and second outer ring portion #262 respectively, are arranged periodically and in a staggered arrangement). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein first patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. As disclosed by Paul, the parallel and staggered arrangement helps prevent cracks from propagating into the circuit region.
Regarding claim 36, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 31, wherein the second seal ring portion comprises: a second inner closed-loop pattern surrounding the circuit region (Fig.15, formed by the conductive metal layers in region #122, minus layer #118); and a second outer closed-loop pattern surrounding the second inner closed-loop pattern (Fig.15, formed by the conductive metal layers in region #123, minus layer #118). Lu does not teach wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern has a first width and a second width wherein the first width is different from the second width. Paul teaches wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern has a first width and a second width wherein the first width is different from the second width (Fig.8, patterns formed by elements #M3, #V2 and #M2 form the inner and an outer closed loop patterns, and elements #M3 have the first width, and elements #M2 have the second width, paragraph [0040], rows 42-46 ). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein each of the second inner ring pattern and the second outer ring pattern has a first width and a second width wherein the first width is different from the second width. This arrangement provides design flexibility and increases the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Regarding claim 37, the combination of Lu and Paul teaches the semiconductor device of claims 31 and 36 as set forth in the obviousness rejection. Lu does not teach the semiconductor device as claimed in claim 36, wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern comprises: first regions having the first width and a first length along the seal ring region; and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region, wherein the first length is different from the second length. Paul teaches wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern comprises: first regions having the first width and a first length along the seal ring region (Fig.8, first regions are formed by elements #M3); and second regions alternately arranged with and connected to the first regions (Fig.8, second regions are formed by elements #M2), wherein the second regions have the second width and a second length along the seal ring region, wherein the first length is different from the second length (paragraph [0040], rows 42-46 and paragraphs [0057], rows 23-25). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern comprises: first regions having the first width and a first length along the seal ring region; and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region, wherein the first length is different from the second length. This pattern provides design flexibility and increases the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Claims 19 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Paul and in view of Shih, (United Stated Patent Application Publication Number, US 2020/0168543 A1), hereinafter referenced as Shih.
Regarding claim 19, the combination of Lu and Paul teaches the semiconductor device of claim 17 as set forth in the obviousness rejection. The combination of Lu and Paul does no teach the semiconductor device as claimed in claim 17, wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region. Shih teaches wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region (Fig.3, spaces between element #106 are away from the corners). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shih and disclose wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region. As disclosed by Shih, the seal ring may strengthen the semiconductor structure and prevent or minimize warpage (paragraph [0039], rows 5-8) and die corners are the most susceptible to warpage.
Regarding claim 35, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection. The combination of Lu and Paul does no teach the semiconductor device as claimed in claim 31, wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region. Shih teaches wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region (Fig.3, spaces between element #106 are away from the corners). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shih and disclose wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region. As disclosed by Shih, the seal ring may strengthen the semiconductor structure and prevent or minimize warpage (paragraph [0039], rows 5-8) and die corners are the most susceptible to warpage.
Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Paul and Uesugi.
Regarding claim 22, the combination of Lu and Paul teaches the semiconductor device of claims 17 and 20 as set forth in the obviousness rejection. The combination of Lu and Paul does not teach the semiconductor device as claimed in claim 20, wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region. Uesugi teaches wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region (Fig.11, elements #12m and #12n each has a linear edge and a toothed edge). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Uesugi and disclose wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region. The tooth edges increase the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore helps prevent the propagation of cracks.
Regarding claim 23, the combination of Lu and Paul teaches the semiconductor device of claim 17 and 20 as set forth in the obviousness rejection, and the combination of Lu, Paul and Uesugi teaches the semiconductor device of claim 22 as set forth in the obviousness rejection. The combination of Lu, Paul and Uesugi does not teach the semiconductor device as claimed in claim 22, wherein the toothed edge of the second inner ring pattern is farther away from the toothed edge of the second outer ring pattern than the linear edge of the second outer ring pattern. However, Lu (Fig.2, 3, 8, 13) and Uesugi (Fig.10 through 15) disclose inner and outer ring patterns of different shapes that are used to prevent cracks from extending in the circuit region, patterns with tooth and straight edges. Therefore, the arrangement of the inner and outer ring patterns is a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular arrangement of the continuous patterns relative to each other brings a significant advantage or improvement.
Claims 24 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Paul and Hu.
Regarding claim 24, the combination of Lu and Paul teaches the semiconductor device of claim 17 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 17, wherein the second seal ring portion comprises: a second inner ring pattern surrounding the circuit region (Fig.15, formed by the conductive metal layers in region #122, minus layer #118); and a second outer ring pattern surrounding the second inner ring pattern (Fig.15, formed by the conductive metal layers in region #123, minus layer #118). The combination of Lu and Paul does not teach wherein the second inner ring pattern and the second outer ring pattern have a same width. Hu teaches wherein the second inner ring pattern and the second outer ring pattern have a same width (Fig.7b, first and second inner ring patterns, element #132A and #134A can have the same width, paragraph [0036], rows 11-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hu and disclose wherein the second inner ring pattern and the second outer ring pattern have the same width. Having multiple rings with a same width provides uniform mechanical strength while simplifying the manufacturing process. Furthermore, a thinner ring would create a vulnerable point rendering a wider ring less effective at protecting the circuits.
Regarding claim 39, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 31, wherein the second seal ring portion comprises: a second inner closed-loop pattern surrounding the circuit region (Fig.15, formed by the conductive metal layers in region #122, minus layer #118); and a second outer closed-loop pattern surrounding the second inner closed-loop pattern (Fig.15, formed by the conductive metal layers in region #123, minus layer #118). The combination of Lu and Paul does not teach wherein the second inner closed-loop pattern and the second outer closed-loop pattern have a same width. Hu teaches wherein the second inner closed-loop pattern and the second outer closed-loop pattern have a same width (Fig.7b, first and second inner ring patterns, element #132A and #134A can have the same width, paragraph [0036], rows 11-13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hu and disclose wherein the second inner closed-loop pattern and the second outer closed-loop pattern have the same width. Having multiple rings with a same width provides uniform mechanical strength while simplifying the manufacturing process. Furthermore, a thinner patter would create a vulnerable point rendering a wider ring less effective at protecting the circuits.
Claims 26-30, 40-44 are rejected under 35 U.S.C. 103 as being unpatentable over Lu, in view of Paul, and in view of Tanamachi.
Regarding claim 26, the combination of Lu and Paul teaches the semiconductor device of claims 17 and 25 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 25, wherein the second continuous pattern is composed of: a dielectric pillar (Fig.15, elements #124 is dielectric, paragraph [0064], rows 4-8) extending from the first dielectric layer (Fig.15, first dielectric layer, formed by elements #116 and #119 and the dielectric pillar, element #125, can all be same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6 and paragraph [0064], row 10-11 and therefore are undistinguishable) to the semiconductor substrate (Fig.15, element #125 extend up to the substrate, element #100), wherein the dielectric pillar is a portion of the first dielectric layer (as above, elements #116, #119 and #125 can be made of the same material).
The combination of Lu and Paul does not teach a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate. Tanamachi teaches a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate (Fig.29C, dielectric pillar, element #992 has a dielectric liner, element #992A, paragraph [0202], rows 6-8, in contact with the substrate formed by element #909 and #910). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tanamachi and disclose a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate. As disclosed by Tanamachi, the liner provides enhanced adhesion to the interconnect layers and the substrate (paragraph [00201], rows 5-10).
Regarding claim 27, the combination of Lu and Paul teaches the semiconductor device of claims 17 and 25 as set forth in the obviousness rejection, and the combination of Lu, Paul and Tanamachi teaches the semiconductor device of claim 26 as set forth in the obviousness rejection. Lu teaches the semiconductor device as claimed in claim 26, wherein the second seal ring portion comprises: a second inner ring portion (Fig.15, formed by the conductive structures of element #122 minus top metal element #118) surrounding the circuit region (Fig.16, element #122 is inside region #170 which surrounds the circuit region, element #140); and a second outer ring portion (Fig.15, formed by the conductive structures of element #123 minus the top metal element #118) surrounding the second inner ring portion (Fig.16; element #123 is inside region #190 which surrounds region, element #170).
Lu does not teach wherein the second inner ring portion and the second outer ring portion are composed of second discontinuous patterns, wherein the second discontinuous patterns in the second inner ring portion and the second outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. Paul teaches a second inner ring portion and the second outer ring portion are composed of second discontinuous patterns (Fig.8, elements #M3 of each ring portion form a discontinuous pattern and elements #M2 of each ring portion form another discontinuous), wherein the second discontinuous patterns in the second inner ring portion and the second outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region (Fig.9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein the second inner ring portion and the second outer ring portion are composed of second discontinuous patterns, wherein the second discontinuous patterns in the second inner ring portion and the second outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region. . Having the seal ring portion pattern distributed periodically around the circuit region results in uniform stress distribution, where stress may occur due to a difference in thermal expansion coefficient of the different conductive and dielectric layers. Furthermore, the parallel and staggered arrangement helps prevent cracks from propagating in the circuit region.
Regarding claim 28, the combination of Lu and Paul teaches the semiconductor device of claims 17 and 25 as set forth in the obviousness rejection, and the combination of Lu, Paul and Tanamachi teaches the semiconductor device of claim 26 and 27 as set forth in the obviousness rejection. The combination of Lu and Paul does not teach the semiconductor device as claimed in claim 27, wherein the second continuous pattern surrounds the second outer ring portion. Tanamachi further teaches the semiconductor device, wherein the second continuous pattern surrounds the second outer ring portion. (Fig.29C, element #992 surrounds the second outer ring, paragraph [0192], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tanamachi and disclose wherein the second continuous pattern surrounds the second outer ring portion. As disclosed by Tanamachi, the second continuous pattern lengthens the path that the moisture must take to reach the interior of the semiconductor die (paragraph [0200], rows 18-23).
Regarding claim 29, the combination of Lu and Paul teaches the semiconductor device of claims 17 and 25 as set forth in the obviousness rejection, and the combination of Lu, Paul and Tanamachi teaches the semiconductor device of claim 26 and 27 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 27, wherein the second continuous pattern is surrounded by the second inner ring portion (Fig.16, element #124 located in region element #160 is surrounded by the second inner ring portion located inside region element #170).
Regarding claim 30, the combination of Lu and Paul teaches the semiconductor device of claims 17 and 25 as set forth in the obviousness rejection, and the combination of Lu, Paul and Tanamachi teaches the semiconductor device of claim 26 and 27 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 27, wherein the second outer ring portion surrounds the second continuous pattern, and the second continuous pattern surrounds the second inner ring portion (Fig.16, the second outer ring portion located inside region element #190, surrounds region element #180, where the dielectric seal ring structure, element #125, is located, and region element #180 surrounds region element #170 where the second inner ring portion is located).
Regarding claim 40, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 31, wherein the closed-loop pattern passes through the second dielectric layer (Fig.15, elements #124 passes through layers #103, #105, #107, #108, #111, #112, and #115) and is composed of: a dielectric pillar (Fig.15, elements #124 is dielectric, paragraph [0064], rows 4-8) extending from the first dielectric layer (Fig.15, first dielectric layer, formed by elements #116 and #119 and the dielectric pillar, element #125, can all be same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6 and paragraph [0064], row 10-11, and therefore are undistinguishable, part of element #124 below element #116 is different material the second dielectric) to the semiconductor substrate (Fig.15, element #125 extend up to the substrate, element #100), wherein the dielectric pillar is a portion of the first dielectric layer (as above, elements #116, #119 and #124 can be made of the same material).
The combination of Lu and Paul does not teach a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate. Tanamachi teaches a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate (Fig.29C, dielectric pillar, element #992 has a dielectric liner, element #992A, paragraph [0202], rows 6-8, in contact with the substrate formed by element #909 and #910). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tanamachi and disclose a dielectric liner layer surrounding the dielectric pillar and in contact with the semiconductor substrate. As disclosed by Tanamachi, the liner provides enhanced adhesion to the interconnect layers and the substrate (paragraph [00201], rows 5-10).
Regarding claim 41, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection, and the combination of Lu, Paul and Tanamachi teaches the semiconductor device of claim 40 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 40, wherein the second seal ring portion comprises: a second inner ring portion (Fig.15, formed by the conductive structures of element #122 minus top metal element #118) surrounding the circuit region (Fig.16, element #122 is inside region #170 which surrounds the circuit region, element #140; and a second outer ring portion (Fig.15, formed by the conductive structures of element #123 minus the top metal element #118) surrounding the second inner ring portion (Fig.16; element #123 is inside region #190 which surrounds region, element #170).
Lu does not teach wherein the second inner ring portion and the second outer ring portion are composed of second discontinuous patterns. Paul teaches a second inner ring portion and the second outer ring portion are composed of second discontinuous patterns (Fig.8, the patterns made of elements #M2 of the second inner and second outer ring are each discontinuous). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Paul and disclose wherein the second inner ring portion and the second outer ring portion are composed of second discontinuous patterns. The discontinuous patterns mitigate the stress distribution, where stress may occur due to a difference in thermal expansion coefficient of the different conductive and dielectric layers.
Regarding claim 42, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection, and the combination of Lu, Paul and Tanamachi teaches the semiconductor device of claims 40 and 41 as set forth in the obviousness rejection. The combination of Lu and Paul does not teach the semiconductor device as claimed in claim 41, wherein the closed-loop pattern surrounds the second outer ring portion. Tanamachi further teaches wherein the closed-loop pattern surrounds the second outer ring portion. (Fig.29C, element #992 surrounds the second outer ring portion, paragraph [0192], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tanamachi and disclose wherein the closed-loop pattern surrounds the second outer ring portion. As disclosed by Tanamachi, the closed-loop pattern lengthens the path that the moisture must take to reach the interior of the semiconductor die (paragraph [0200], rows 18-23).
Regarding claim 43, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection, and the combination of Lu, Paul and Tanamachi teaches the semiconductor device of claims 40 and 41 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 41, wherein the closed-loop pattern is surrounded by the second inner ring portion (Fig.16, element #124 located in region element #160 is surrounded by the second inner ring portion located inside region element #170).
Regarding claim 44, the combination of Lu and Paul teaches the semiconductor device of claim 31 as set forth in the obviousness rejection, and the combination of Lu, Paul and Tanamachi teaches the semiconductor device of claims 40 and 41 as set forth in the obviousness rejection. Lu further teaches the semiconductor device as claimed in claim 41, wherein the second outer ring portion surrounds the closed-loop pattern, and the closed-loop pattern surrounds the second inner ring portion (Fig.16, the second outer ring portion located inside region element #190, surrounds region element #180, where the closed-loop pattern, element #125, is located, and region element #180 surrounds region element #170 where the second inner ring portion is located).
Allowable Subject Matter
Claim 38 is allowed if written in independent form.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 38, the cited prior art does not teach or fairly suggests, along with other claimed features: “wherein the second regions are disposed corresponding to spaces between the first discontinuous patterns in a top view”.
Response to Arguments
Applicant’s arguments filed on 02/15/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to the claim have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights