DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/30/2026 has been entered.
Response to Amendment
The Amendment filed on 07/30/2026 has been entered. Claims 1-2, 7-8, 17-19, 22-23, 25, 31-35, remain pending in the application. Claims 3-6, 9-16, 20-21, 24, 26-30 and 36-44 have been cancelled.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/13/2026 has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 17, 18, 25, and 31-34 rejected under 35 U.S.C. 103 as being unpatentable over Paul et al., (United States Patent Application Publication Number, US 2021/0327826 A1) hereinafter referenced as Paul., in view of Lu, (United States Patent Application Publication Number, US 2020/0395296 A1) hereinafter referenced as Lu.
Regarding claim 1, Paul teaches a semiconductor device, comprising: a semiconductor substrate (Fig.6, element #620) having a circuit region (Fig.6, element #202) and a seal ring region surrounding the circuit region (Fig.6, element #206, equivalent to element #306 of Fig.3, which surrounds the circuit region); a first layer disposed over the seal ring region (Fig.6, formed by element #606 and the horizontal slice of element #642 located right below element #606 and having the same thickness as the top metal layer; Note that element #642 is part of a BEOL process, paragraph [0103], rows 3-7 and therefore element #642 is formed by multiple dielectric layers between and surrounding the metal layers).
Paul teaches that element #606 is a passivation layer and elements #642 is a dielectric. Lu teaches a passivation layer made of a dielectric and a top BEOL dielectric layer made of the same material (Fig.15, dielectric layer is formed by elements #116 and #119 which can all be the same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6, and therefore are undistinguishable). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose a first dielectric layer disposed over the seal ring region, wherein the first dielectric layer has a first dielectric constant. Using a passivation layer formed from a dielectric material, such as silicon nitride, provides protection from environmental contaminants by acting as a barrier against moisture and ionic contaminants while offering high mechanical stability (paragraph [0089], rows 8-11).
Paul further teaches a second dielectric layer disposed between the semiconductor substrate and the first dielectric layer (Fig.6, part of element #642 below the horizontal slice of element #642 located right below element #606 and having the same thickness as the top metal layer; Note that element #642 is part of a BEOL process, paragraph [0103], rows 3-7 and therefore element #642 is formed by multiple dielectric layers between and surrounding the metal layers). Paul does not teach wherein the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant. Lu teaches wherein the second dielectric layer has a second dielectric constant (Fig.15, second dielectric formed by elements #103, #105, #107, #108, #111, #112 and #115 which can all be silicon oxide, paragraph [0046], rows 3-4, paragraph [0048], rows 3-5, paragraph [0050], rows 4-6, paragraph [0050], rows 9-11, paragraph [0054], rows 3-5, paragraph [0055], rows 6-8, paragraph [0057], rows 4-7) that is lower than the first dielectric constant (second dielectric is silicon oxide which has a lower dielectric constant than the first dielectric, which is silicon nitride). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant. Silicon oxide provides superior electrical insulation of metal lines and reduced stress at the substrate surface as compared to silicon nitride, and therefore is preferred for the lower BEOL dielectric layers, while silicon nitride provides protection from environmental contaminants by acting as a barrier against moisture and ionic contaminants while offering high mechanical stability (paragraph [0089], rows 8-11).
Paul further teaches a conductive seal ring structure disposed in the seal ring region (Fig.6, formed by metal layers and via in region #206, Fig.12 and 13 shows plan and side views of the conductive structure), wherein the conductive seal ring structure comprises: a first seal ring portion embedded in the first dielectric layer (Fig.6, formed by top metal layer M4 in the seal ring region, element #206), wherein the first seal ring portion comprises first patterns arranged periodically and discontinuously(Fig.12 plan view, M4 layer forms discontinuous patterns arranged periodically); and a second seal ring portion disposed directly below the first seal ring portion and embedded in the second dielectric layer (Fig.6, formed by metal layers M3 and M2 and the vias between them), wherein the second seal ring portion comprises at least a second continuous pattern(Fig.12 plan view M2 and M3 layers and the vias in between them form a continuous pattern), wherein the second seal ring portion comprises: a second inner closed-loop pattern surrounding the circuit region; and a second outer closed-loop pattern surrounding the second inner closed-loop pattern (Fig.12, second seal ring region has two closed-loop patterns formed by element M2, M3 and V3 corresponding to elements #1202 and #1203, Fig.3 shows closed-loops surrounding the circuit region), wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern has a first width and a second width crossing the seal ring region, wherein the first width is greater than the second width (Fig.12, each pattern has a first and a second width, where the first width is greater than the second width, paragraph [0040], rows 40-44), each of the second inner closed-loop pattern and the second outer closed-loop pattern comprises: first regions having the first width and a first length along the seal ring region (Fig.12, regions occupied by elements either M2 or M3 corresponding to elements #1220 and #1230 respectively); and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region (Fig.12, regions occupied by either elements M2 or M3 corresponding to elements #1222 and #1232 respectively, and paragraph [0040], rows 40-44, paragraph [0047], rows 23-25), wherein the first length is different from the second length (paragraph [0047], rows 23-25), and the second regions are disposed corresponding to spaces between the first patterns in a top view (Fig.12).
Regarding claim 2, the combination of Paul and Lu teaches the semiconductor device as claimed in claim 1 as set forth in the obviousness rejection. Paul further teaches the semiconductor device as claimed in claim 1, wherein the first seal ring portion comprises: a first inner ring portion surrounding the circuit region; and a first outer ring portion surrounding the first inner ring portion, wherein first patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region (Fig.12 the seal ring has two M4 inner ring portions, parallel with each other and in a staggered arrangement, Fig.3, the patterns form a ring around the circuit region).
Regarding claim 17 Paul teaches a semiconductor device, comprising: a semiconductor substrate (Fig.6, element #620) having a circuit region (Fig.6, element #202) and a seal ring region surrounding the circuit region (Fig.6, element #206, equivalent to element #306 of Fig.3, which surrounds the circuit region); a first layer disposed over the seal ring region (Fig.6, formed by element #606 and the horizontal slice of element #642 located right below element #606 and having the same thickness as the top metal layer; Note that element #642 is part of a BEOL process, paragraph [0103], rows 3-7 and therefore element #642 is formed by multiple dielectric layers between and surrounding the metal layers).
Paul teaches that element #606 is a passivation layer and elements #642 is a dielectric. Lu teaches a passivation layer made of a dielectric and a top BEOL dielectric layer made of the same material (Fig.15, dielectric layer is formed by elements #116 and #119 which can all be the same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6, and therefore are undistinguishable). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose a first dielectric layer disposed over the seal ring region, wherein the first dielectric layer has a first dielectric constant. Using a passivation layer formed from a dielectric material, such as silicon nitride, provides protection from environmental contaminants by acting as a barrier against moisture and ionic contaminants while offering high mechanical stability (paragraph [0089], rows 8-11).
Paul further teaches a second dielectric layer disposed between the semiconductor substrate and the first dielectric layer (Fig.6, part of element #642 below the horizontal slice of element #642 located right below element #606 and having the same thickness as the top metal layer; Note that element #642 is part of a BEOL process, paragraph [0103], rows 3-7 and therefore element #642 is formed by multiple dielectric layers between and surrounding the metal layers). Paul does not teach wherein the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant. Lu teaches wherein the second dielectric layer has a second dielectric constant (Fig.15, second dielectric formed by elements #103, #105, #107, #108, #111, #112 and #115 which can all be silicon oxide, paragraph [0046], rows 3-4, paragraph [0048], rows 3-5, paragraph [0050], rows 4-6, paragraph [0050], rows 9-11, paragraph [0054], rows 3-5, paragraph [0055], rows 6-8, paragraph [0057], rows 4-7) that is lower than the first dielectric constant (second dielectric is silicon oxide which has a lower dielectric constant than the first dielectric, which is silicon nitride). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant. Silicon oxide provides superior electrical insulation of metal lines and reduced stress at the substrate surface as compared to silicon nitride, and therefore is preferred for the lower BEOL dielectric layers, while silicon nitride provides protection from environmental contaminants by acting as a barrier against moisture and ionic contaminants while offering high mechanical stability (paragraph [0089], rows 8-11).
Paul further teaches a first seal ring portion disposed in the seal ring region and embedded in the first dielectric layer (Fig.6, formed by top metal layer M4 in the seal ring region, element #206), wherein the first seal ring portion comprises first discontinuous patterns in a top view (Fig.12 plan view, M4 layer forms discontinuous patterns); and a second seal ring portion disposed in the seal ring region and embedded in the second dielectric layer (Fig.6, formed by metal layers M3 and M2 and the vias between them), wherein the second seal ring portion is disposed directly below the first seal ring portion and comprises at least a second continuous pattern in the top view (Fig.12 plan view M2 and M3 layers and the vias in between them form a continuous pattern located directly below M4), wherein the second seal ring portion comprises: a second inner closed-loop pattern surrounding the circuit region; and a second outer closed-loop pattern surrounding the second inner closed-loop pattern (Fig.12, second seal ring region has two closed-loop patterns formed by elements M2, M3 and V3 corresponding to elements #1202 and #1203, Fig.3 shows closed-loops surrounding the circuit region), wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern has a first width and a second width crossing the seal ring region, wherein the first width is greater than the second width (Fig.12, each pattern has a first and a second width, where the first width is greater than the second width, paragraph [0040], rows 40-44), each of the second inner closed-loop pattern and the second outer closed-loop pattern comprises: first regions having the first width and a first length along the seal ring region (Fig.12, regions occupied by either elements M2 or M3 corresponding to elements #1220 and #1230); and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region (Fig.12, regions occupied by elements either M2 or M3 corresponding to elements #1222 and #1232 respectively, and paragraph [0040], rows 40-44, paragraph [0047], rows 23-25), wherein the first length is different from the second length (paragraph [0047], rows 23-25), and the second regions are disposed corresponding to spaces between the first discontinuous patterns in a top view (Fig.12).
Regarding claim 18, the combination of Paul and Lu teaches the semiconductor device as claimed in claim 17 as set forth in the obviousness rejection. Paul further teaches the semiconductor device as claimed in claim 17, wherein the first seal ring portion comprises: a first inner ring portion surrounding the circuit region; and a first outer ring portion surrounding the first inner ring portion, wherein first discontinuous patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region (Fig.12 the seal ring has two M4 inner ring portions, parallel with each other and in a staggered arrangement, Fig.3, the patterns form a ring around the circuit region).
Regarding claim 25, the combination of Paul and Lu teaches the semiconductor device as claimed in claim 17 as set forth in the obviousness rejection. Paul further teaches the semiconductor device as claimed in claim 17, wherein the second continuous pattern passes through the second dielectric layer but does not pass through the first dielectric layer (Fig.8 and 13 the continuous pattern formed by M2 and M3 layers and the vias in between them passes through the second dielectric layer but not through the first dielectric layer, see mapping of the dielectric layers in the rejection of claim 17).
Regarding claim 31, Paul teaches a semiconductor device, comprising: a semiconductor substrate (Fig.6, element #620) having a circuit region (Fig.6, element #202) and a seal ring region surrounding the circuit region (Fig.6, element #206, equivalent to element #306 of Fig.3, which surrounds the circuit region); a first layer disposed over the seal ring region (Fig.6, formed by element #606 and the horizontal slice of element #642 located right below element #606 and having the same thickness as the top metal layer; Note that element #642 is part of a BEOL process, paragraph [0103], rows 3-7 and therefore element #642 is formed by multiple dielectric layers between and surrounding the metal layers). Paul teaches that element #606 is a passivation layer and elements #642 is a dielectric. Lu teaches a passivation layer made of a dielectric and a top BEOL dielectric layer made of the same material (Fig.15, dielectric layer is formed by elements #116 and #119 which can all be the same material, silicon nitride, paragraph [0057], rows 10-12, paragraph [0060], rows 3-6, and therefore are undistinguishable). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose a first dielectric layer disposed over the seal ring region, wherein the first dielectric layer has a first dielectric constant. Using a passivation layer formed from a dielectric material, such as silicon nitride, provides protection from environmental contaminants by acting as a barrier against moisture and ionic contaminants while offering high mechanical stability (paragraph [0089], rows 8-11).
Paul further teaches a first seal ring portion disposed in the seal ring region and embedded in the first dielectric layer (Fig.6, formed by top metal layer M4 in the seal ring region, element #206), wherein the first seal ring portion comprises first discontinuous patterns arranged periodically (Fig.8, side view and Fig.12 plan view, M4 layer forms discontinuous and periodic patterns); and a second seal ring portion disposed in the seal ring region and between the first dielectric layer and the semiconductor substrate (Fig.6, formed by metal layers M3 and M2 and the vias V3 between them), wherein the second seal ring portion is disposed directly below the first seal ring portion and comprises at least one closed-loop pattern (Fig.8, side view, M2 and M3 layers and the vias in between them form a closed-loop pattern, and Fig.12 plan view, the pattern is located directly below M4), wherein the second seal ring portion comprises: a second inner closed-loop pattern surrounding the circuit region; and a second outer closed-loop pattern surrounding the second inner closed-loop pattern (Fig.12, second seal ring region has two closed-loop patterns formed by elements M2, M3 and V3 corresponding to elements #1202 and #1203, Fig.3 shows the closed-loop patterns surrounding the circuit region), wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern has a first width and a second width crossing the seal ring region, wherein the first width is greater than the second width (Fig.12, each pattern has a first and a second width, where the first width is greater than the second width, paragraph [0040], rows 40-44) each of the second inner closed-loop pattern and the second outer closed-loop pattern comprises: first regions having the first width and a first length along the seal ring region (Fig.12, regions occupied by either elements M2 or M3 corresponding to elements #1220 and #1230 respectively); and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region (Fig.12, regions occupied by either elements M2 or M3 corresponding to elements #1222 and #1232 respectively, and paragraph [0040], rows 40-44, paragraph [0047], rows 23-25), wherein the first length is different from the second length (paragraph [0047], rows 23-25), and the second regions are disposed corresponding to spaces between the first discontinuous patterns in a top view (Fig.12).
Regarding claim 32, the combination of Paul and Lu teaches the semiconductor device as claimed in claim 31 as set forth in the obviousness rejection. Paul teaches the semiconductor device as claimed in claim 31, further comprising: a second dielectric layer disposed between the semiconductor substrate and the first dielectric layer (Fig.6, part of element#642 below the horizontal slice of element #642 located right below element #606 and having the same thickness as the top metal layer; Note that element #642 is part of a BEOL process, paragraph [0103], rows 3-7 and therefore element #642 is formed by dielectric layers between and surrounding the metal layers), wherein the second seal ring portion is embedded in the second dielectric layer (Fig.6, elements #M3 and M2 are embedded in element #642).
Paul does not teach wherein the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant. Lu teaches wherein the second dielectric layer has a second dielectric constant (Fig.15, second dielectric formed by elements #103, #105, #107, #108, #111, #112 and #115 which can all be silicon oxide, paragraph [0046], rows 3-4, paragraph [0048], rows 3-5, paragraph [0050], rows 4-6, paragraph [0050], rows 9-11, paragraph [0054], rows 3-5, paragraph [0055], rows 6-8, paragraph [0057], rows 4-7) that is lower than the first dielectric constant (second dielectric is silicon oxide which has a lower dielectric constant than the first dielectric, which is silicon nitride). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lu and disclose the second dielectric layer has a second dielectric constant that is lower than the first dielectric constant. Silicon oxide provides superior electrical insulation of metal lines and reduced stress at the substrate surface as compared to silicon nitride, and therefore is preferred for the lower BEOL dielectric layers, while silicon nitride provides protection from environmental contaminants by acting as a barrier against moisture and ionic contaminants while offering high mechanical stability (paragraph [0089], rows 8-11).
Regarding claim 33, the combination of Paul and Lu teaches the semiconductor device as claimed in claims 31 and 32 as set forth in the obviousness rejection. Paul further teaches the semiconductor device as claimed in claim 32, wherein the first seal ring portion is electrically connected to the second seal ring portion using a via passing through the second dielectric layer (Fig.8, vias #V3 connect the first and second seal ring portions).
Regarding claim 34, the combination of Paul and Lu teaches the semiconductor device as claimed in claim 31 as set forth in the obviousness rejection. Paul further teaches the semiconductor device as claimed in claim 31, wherein the first seal ring portion comprises: a first inner ring portion surrounding the circuit region; and a first outer ring portion surrounding the first inner ring portion, wherein first discontinuous patterns of the first inner ring portion and the first outer ring portion are parallel with each other and in a staggered arrangement along the seal ring region (Fig.12 the seal ring has two M4 inner ring portions, parallel with each other and in a staggered arrangement).
Claims 7, 8, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Paul in view of Lu and in view of Uesugi et al., (United States Patent Application Publication Number, US 2005/0087878 A1) hereinafter referenced as Uesugi.
Regarding claim 7, the combination of Paul and Lu teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection. The combination of Paul and Lu does not teach the semiconductor device as claimed in claim 2, wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region. Uesugi teaches wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region (Fig.11, elements #12m and #12n each has a linear edge and a toothed edge). The tooth edges increase the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer insulating film, and therefore help prevent the propagation of cracks.
Regarding claim 8, the combination of Paul and Lu teaches the semiconductor device of claims 1 and 2 as set forth in the obviousness rejection, and the combination of Paul, Lu and Uesugi teaches the semiconductor device of claim 7 as set forth in the obviousness rejection. The combination of Paul and Lu does not teach the semiconductor device as claimed in claim 7, wherein the linear edge of the second inner ring pattern is close to the linear edge of the second outer ring pattern. Uesugi teaches wherein the linear edge of the second inner ring pattern is close to the linear edge of the second outer ring pattern (Fig.11, the linear edges of elements #12m and #12n are close to each other). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Uesugi and disclose wherein the linear edge of the second inner ring pattern is close to the linear edge of the second outer ring pattern. This results in a small size seal ring which increase the area available for the circuit region.
Regarding claim 22, the combination of Paul and Lu teaches the semiconductor device as claimed in claim 17 as set forth in the obviousness rejection. The combination of Paul and Lu does not teach the semiconductor device as claimed in claim 17, wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region. Uesugi teaches wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region (Fig.11, elements #12m and #12n each has a linear edge and a toothed edge). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Uesugi and disclose wherein each of the second inner ring pattern and the second outer ring pattern has a linear edge and a toothed edge substantially extending along the seal ring region. The tooth edges increase the perimeter and the total area of the sidewalls of the metal patterns, which improves the adhesiveness between the metal patterns and the interlayer dielectric layers, and therefore help prevent the propagation of cracks.
Regarding claim 23, the combination of Paul and Lu teaches the semiconductor device as claimed in claim 17 as set forth in the obviousness rejection, and the combination of Paul, Lu and Uesugi teaches the semiconductor device as claimed in claim 22 as set forth in the obviousness rejection. The combination of Paul, Lu and Uesugi does not teach the semiconductor device as claimed in claim 22, wherein the toothed edge of the second inner ring pattern is farther away from the toothed edge of the second outer ring pattern than the linear edge of the second outer ring pattern. However, Lu (Fig.2, 3, 8, 13) and Uesugi (Fig.10 through 15) disclose inner and outer ring patterns of different shapes that are used to prevent cracks from extending in the circuit region, patterns comprising tooth and straight edges. Therefore, the arrangement of the inner and outer ring patterns is a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular arrangement of the continuous patterns relative to each other brings a significant advantage or improvement.
Claims 19 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Paul in view of Lu and in view of Shih, (United Stated Patent Application Publication Number, US 2020/0168543 A1), hereinafter referenced as Shih.
Regarding claim 19, the combination of Paul and Lu teaches the semiconductor device of claim 17 as set forth in the obviousness rejection. The combination of Paul and Lu does not teach the semiconductor device as claimed in claim 17, wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region. Shih teaches wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region (Fig.3, spaces between element #106 are away from the corners). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shih and disclose wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region. As disclosed by Shih, the seal ring may strengthen the semiconductor structure and prevent or minimize warpage (paragraph [0039], rows 5-8) and, since die corners are the most susceptible to warpage, the metal patterns should be located in the corners of the seal ring region in order to minimize the warpage.
Regarding claim 35, the combination of Paul and Lu teaches the semiconductor device of claim 31 as set forth in the obviousness rejection. The combination of Paul and Lu does not teach the semiconductor device as claimed in claim 31, wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region. Shih teaches wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region (Fig.3, spaces between element #106 are away from the corners). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shih and disclose wherein spaces between the first discontinuous patterns are away form a corner of the seal ring region. As disclosed by Shih, the seal ring may strengthen the semiconductor structure and prevent or minimize warpage (paragraph [0039], rows 5-8) and since die corners are the most susceptible to warpage, the metal patterns should be the ones located in the corners of the seal ring region in order to minimize the warpage.
Response to Arguments
Applicant’s arguments filed on 07/30/2026 have been fully considered but they
are not persuasive. As noted in the above rejection of claim 1, 17 and 31, Paul teaches wherein the second seal ring portion (Fig.16 and 8, formed by metal layers M3 and M2 and the vias between them) comprises: a second inner closed-loop pattern surrounding the circuit region; and a second outer closed-loop pattern surrounding the second inner closed-loop pattern (Fig.12, second seal ring region has two closed patterns formed by M2, M3 and V3 vias part of elements #1202 and #1203, Fig.3 shows closed-loops surrounding the circuit region), wherein each of the second inner closed-loop pattern and the second outer closed-loop pattern has a first width and a second width crossing the seal ring region, wherein the first width is greater than the second width (Fig.12, each pattern has a first and a second width, where the first width is greater than the second width, paragraph [0040], rows 40-44), each of the second inner closed-loop pattern and the second outer closed-loop pattern comprises: first regions having the first width and a first length along the seal ring region (Fig.12, regions occupied by either elements M2 or M3 corresponding to elements #1220 and #1230 respectively); and second regions alternately arranged with and connected to the first regions, wherein the second regions have the second width and a second length along the seal ring region (Fig.12, regions occupied by either elements M2 or M3 corresponding to elements #1222 and #1232 respectively, and paragraph [0040], rows 40-44, paragraph [0047], rows 23-25), wherein the first length is different from the second length (paragraph [0047], rows 23-25), and the second regions are disposed corresponding to spaces between the first patterns in a top view (Fig.12).
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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