Office Action Predictor
Last updated: April 15, 2026
Application No. 18/188,937

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING

Non-Final OA §102
Filed
Mar 23, 2023
Examiner
BOWEN, ADAM S
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, LTD.
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
1y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allow Rate
678 granted / 704 resolved
+28.3% vs TC avg
Minimal +2% lift
Without
With
+2.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
21 currently pending
Career history
725
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
36.1%
-3.9% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 704 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement s(IDS) submitted on 09/17/2024, 06/16/2025 and 11/04/2025 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Election/Restrictions Applicant’s election without traverse of Group I in the reply filed on 10/27/2025 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5 and 7-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (2021/0305809). Re claim 1, Hung teaches an integrated circuit (IC) device (Fig. 5B), comprising: an antenna effect protection device (506); and a to-be-protected device (510), wherein a first source/drain (506a) of the antenna effect protection device (506) is electrically coupled to a first conductor (594) configured to carry a reference voltage [234], a second source/drain (506c) of the antenna effect protection device (506) is electrically coupled by a second conductor (590) to a gate (MG) of the to-be-protected device (510), and the antenna effect protection device (506) is a bulk-less device (Fig. 5B). Re claim 2, Hung teaches the IC device of claim 1, wherein a gate (506b) of the antenna effect protection device (506) is electrically coupled to the first conductor (594). Re claim 3, Hung teaches the IC device of claim 1, further comprising: a further antenna effect protection device (502), wherein a gate (MG) of the antenna effect protection device (506) is electrically coupled to a source/drain (530a) of the further antenna effect protection device (502). Re claim 4, Hung teaches the IC device of claim 1, wherein the to-be-protected device (510) is a bulk-less device (Fig. 5B). Re claim 5, Hung teaches the IC device of claim 1, further comprising: an insulation layer (521) having a front side (582) and a back side (580) opposite to the front side (582), wherein the to-be-protected device (510), the antenna effect protection device (506) and the first conductor (594) are over the front side (582) of the insulation layer (521); and a conductive structure (540, 542, 544) extending through the insulation layer (521), and electrically coupling the first conductor (594) on the front side (582) to the back side (580) of the insulation layer (521). Re claim 7, Hung teaches the IC device of claim 5, further comprising: a back side metal layer over the back side of the insulation layer [215-216, 227-229], the back side metal layer electrically coupled to the first conductor through the conductive structure [215-216, 227-229]. Re claim 8, Hung teaches the IC device of claim 7, wherein the back side metal layer comprises a back side power rail electrically coupled to the first conductor through the conductive structure [180]. Re claim 9, Hung teaches the IC device of claim 5, wherein the conductive structure (540, 542, 544) comprises: an epitaxy structure (506a) over the front side (582) of the insulation layer (521), and electrically coupled to the first conductor (594), and a feed through via extending through the insulation layer (540), and electrically coupling the epitaxy structure (506a) to the back side (580) of the insulation layer (521). Re claim 10, Hung teaches the IC device of claim 9, wherein the epitaxy structure (506a) comprises a substrate tap or a well tap [196] located outside the antenna effect protection device (506) and the to-be-protected device (510). Re claim 11, Hung teaches the IC device of claim 9, wherein the epitaxy structure (506a) comprises the first source/drain [231] of the antenna effect protection device (506). Claim(s) 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (2021/0305809). Re claim 13, Hung teaches an integrated circuit (IC) device (Fig. 5B), comprising: a first power domain ([231], “charging circuit”); a second power domain ([214], “discharging circuit”); a first antenna effect protection device (506) in the first power domain ([231], “charging circuit”); and a second antenna effect protection device (510) in the second power domain ([214], “discharging circuit”), wherein a gate (MG) of the second antenna effect protection device (510) is electrically coupled to a source/drain (506c) of the first antenna effect protection device (506). Claim(s) 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (2021/0305809). Re claim 19, Hung teaches an integrated circuit (IC) device (Fig. 5B), comprising: a first transistor (506) and a second transistor (510) over a substrate [182]; and a redistribution structure (Fig. 5B) over the first transistor (506) and the second transistor (510), to electrically couple (594) a first source/drain (506a) of the first transistor (506) to a gate (506b) of the first transistor (506), and a second source/drain (506c) of the first transistor (506) to a gate (MG) of the second transistor (510), wherein at least one of a bottom of a first source/drain (510a) of the second transistor (510) or a bottom of a second source/drain (510c) of the second transistor (510) is over and in direct contact with an insulation layer (521) of the substrate [182]. Re claim 20, Hung teaches the IC device method of claim 19, further comprising: a conductive feed (540) through via extending through the insulation layer (521), wherein the feed through via is electrically coupled to the first source/drain (506a) and the gate (506b) of the first transistor (506); and a back side metal layer over a back side of the insulation layer, the back side metal layer electrically coupled to the feed through via [215-216, 227-229]. Allowable Subject Matter Claims 6, 12 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re claim 6, Hung teaches the IC device of claim 5, yet remains explicitly silent to further comprising: a semiconductor layer over the back side of the insulation layer, the semiconductor layer electrically coupled to the first conductor through the conductive structure. Re claim 12, Hung teaches the IC device of claim 1, yet remains explicitly silent to wherein the antenna effect protection device is configured to: in response to a reversed bias applied between the first source/drain and the second source/drain of the antenna effect protection device, discharge electric charges of a first polarity on the second conductor to the first conductor through a leakage current of the antenna effect protection device, and in response to a forward bias applied between the first source/drain and the second source/drain of the antenna effect protection device, discharge electric charges of a second polarity on the second conductor to the first conductor through a channel current of the antenna effect protection device, the second polarity opposite to the first polarity. Re claim 14, Hung teaches the IC device of claim 13, yet remains explicitly silent to further comprising: a first functional device in the second power domain wherein a gate of the first functional device is electrically coupled to a source/drain of the second antenna effect protection device. Claims 15-17 are objected to for at least depending from objected claim 14. Re claim 18, Hung teaches the IC device of claim 13, yet remains explicitly silent to further comprising at least one of: a first power clamp circuit in the first power domain; a second power clamp circuit in the second power domain; a first electrostatic discharge (ESD) circuit electrically coupled between a first local power rail of the first power domain and a global power rail; a second ESD circuit electrically coupled between a second local power rail of the second power domain and the global power rail; or a third ESD circuit electrically coupled between the first local power rail and the second local power rail. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /ADAM S BOWEN/Examiner, Art Unit 2897
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Prosecution Timeline

Mar 23, 2023
Application Filed
Jul 19, 2023
Response after Non-Final Action
Dec 26, 2025
Non-Final Rejection — §102
Mar 31, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+2.5%)
1y 8m
Median Time to Grant
Low
PTA Risk
Based on 704 resolved cases by this examiner. Grant probability derived from career allow rate.

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