Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al, US 20160141378 A1 in view of Lin et al, US 20070108615 A1 in view of O,GINO SHINJI, KR 20080087659 A and further in view of Park et al, US 20160329432 A1.
Yang teaches:
a thin film transistor (figure 2) including:
an active layer (para 005, not shown figure 2);
a gate electrode (124) on the active layer; and an electrode layer (173,175) having a first stress, the electrode layer including a source electrode (173q) and a drain (173q) electrode; (para 48-50)
and a first passivation layer (180a) between the thin film transistor and the light emission layer and covering the thin film transistor, the first passivation layer having a second stress,
a first conductive layer (173p and 175 p); a second conductive layer (173q and 175q); and a third conductive layer (173r and 175r) including a metal or a metal oxide. (para 48-50)
Yang fails to teach:
a light emission layer facing the thin film transistor
defining the first stress which is greater than 0 MPa and 200 MPa or less, and
a difference between an absolute value of the first stress and an absolute value of the second stress is about 600 megapascals or less.
Lin teaches:
The formation of the first conductive layer 212, the second conductive layer 214, and the third conductive layer 216 provides stress control to withstand further processing of the manufacture of the wafer structure 300. The stack formed by the first conductive layer 212, the second conductive layer 214, and the third conductive layer 216 has a tensile stress in the range of 100 to 600 MPa with a typical value about 300 MPa. (para 043)
Ogino teaches:
it is preferable to make the internal stress to the whole passivation layer 18 into the range of -50 MPa (compression stress) to +50 MPa (tensile stress). This is because, as a whole, the stack is not biased against internal stress, and furthermore, no point defect is generated in the passivation layer 18. More specifically, among the layers constituting the passivation layer 18, it is preferable to set the internal stress of the compressive stress layer in the range of -150 MPa to -50 MPa from the viewpoint of suppressing warpage of the substrate. Similarly, in the layers constituting the passivation layer 18, it is preferable to set the internal stress of the tensile stress layer in the range of +50 MPa to +150 MPa from the viewpoint of suppressing the warpage of the substrate and the suppression of cracking in the passivation layer. (machine translation)
Therefore, combining the teachings of Lin and Ogino, one of ordinary skill would be able to determine a difference between an absolute value of the first stress and an absolute value of the second stress is about 600 megapascals or less.
Park teaches: a light emission layer (390) facing the thin film transistor. See Figure 5
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park, with the primary reference of Yang, because the OLED may conventionally emit light which is generated from the organic light emitting layer positioned in the aperture of the pixel
Yang fails to teach:
2. The display device of claim 1, wherein a roughness of the first passivation layer is about 0.3 nanometer or more and about 1.1 nanometers or less.
3. The display device of claim 1, wherein the second stress of the first passivation layer is a compressive stress of -400 megapascals or more and less than 0 megapascals.
4, The display device of claim 1, wherein a thickness of the first passivation layer is about 200 nanometers or more and about 700 nanometers or less.
In regards to claim 3, Ogino teaches:
it is preferable to set the internal stress of the compressive stress layer in the range of -150 MPa to -50 MPa from the viewpoint of suppressing warpage of the substrate. (machine translation)
In regards to the thickness value, this would have been optimized through routine experimentation and would not lend itself to patentability in the instant application, without displaying unexpected results. (in Re Aller)
Yang teaches:
5. The display device of claim 1, further comprising: a second passivation layer (180b) including an organic material or an inorganic material, and the first passivation (180a) layer between the thin film transistor and the second passivation layer (180b). Yang fails to teach:
6. The display device of claim 5, wherein each of the first passivation layer and the second passivation layer has surplus unbonded electrons on a surface to define a number of dangling bonds, and the number of dangling bonds of the second passivation layer is smaller than the number of dangling bonds of the first passivation layer.
In regards to the dangling bonds, it is well known in the art that dangling bonds are primarily located on the surface of films. Also, as films become thinner (especially at the nanoscale), surface effects become more dominant, and the influence of dangling bonds increases significantly. The presence of dangling bonds can impact the electronic and optical properties of thin films by creating localized states within the bandgap. Film thickness and strain can be used to tune the electronic properties associated with dangling bonds. And Growth conditions can affect the density of dangling bonds and their distribution within the film. Therefore, it would have been obvious to one of ordinary skill in the art to optimize the thickness and growth characteristics to achieve the desired number of dangling bonds (in re Aller)
7. The display device of claim 5, wherein each of the first passivation layer and the second passivation layer includes silicon nitride or silicon oxynitride, each of the silicon nitride and the silicon oxynitride has a content of nitrogen relative to silicon, and the content of nitrogen relative to silicon of the first passivation layer is greater than the content of nitrogen relative to silicon of the second passivation layer.
In regards to claim 7, it would have been obvious to one of ordinary skill in the art to optimize the thickness and growth characteristics to achieve the desired concentration of nitrogen. (in re Aller)
8. The display device of claim 5, wherein a thickness of the second passivation layer is about 100 nanometers or more and about 1000 nanometers or less.
In regards to the thickness value, this would have been optimized through routine experimentation and would not lend itself to patentability in the instant application, without displaying unexpected results. (in Re Aller)
Claim(s) 10, 11, 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang, Lin, Ogino and Park as applied to claim 1 above, and further in view of Kim et al, US 9871144 B2.
The above references fail to teach:
10. The display device of claim 1, wherein the first conductive layer includes Ti, and the second conductive layer includes Cu.
11. The display device of claim 10, wherein the third conductive layer includes at least one among indium tin oxide, titanium, titanium oxide, zinc indium oxide, zinc tin oxide, indium gallium zinc oxide and zinc indium tin oxide.
13. The display device of claim 11, wherein each of the source electrode and the drain electrode further includes: a capping film including a metal or a metal oxide, and the capping film between the first conductive layer and the second conductive layer.
14. The display device of claim 13, wherein the capping film includes at least one among indium tin oxide, titanium, titanium oxide, zinc indium oxide, zinc tin oxide, indium gallium zinc oxide and zinc indium tin oxide.
In regards to claims 10,11, 13 and 14
Kim teaches:
A source and drain electrode layer containing a first conductive layer (CBL1) that includes Ti and a second conductive layer (MSL) that includes CU and a third conductive layer (CCL), wherein the third conductive layer includes at least one among indium tin oxide, titanium, titanium oxide, zinc indium oxide, zinc tin oxide, indium gallium zinc oxide and zinc indium tin oxide.
And wherein each of the source electrode and the drain electrode further
includes: a capping film (CBL2) including a metal or a metal oxide, and the capping film (CBL2) between the first conductive layer (CBL1) and the second conductive layer (MSL).
And wherein the capping film (CBL2) includes at least one among indium tin
oxide, titanium, titanium oxide, zinc indium oxide, zinc tin oxide, indium gallium zinc oxide and zinc indium tin oxide.
See Figures 2 and 3 and para 20, 23, 24
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because the metal layer includes a material suitable for dry etching and capable of preventing copper in the main wiring layer from diffusing (para 026, Kim)
In regards to claim 12,
Lin teaches: wherein the first stress is defined by the third conductive layer and is greater than about 0 MPa and is about 200 MPa or less. (para 043)
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang, Lin, Ogino and Park as applied to claim 1 above, and further Lee et al, US 20150200208 A1 The above references fail to teach:
17. The display device of claim 1, further comprising:
an impact-resistance layer between the first passivation layer and the light emission layer; and
a color filter layer on the light emission layer.
Lee teaches:
an impact-resistance layer (270) (180) between the first passivation layer (180) and the light emission layer (181); and a color filter layer (230) on the light emission layer. (see figure 13)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because this is conventionally done in the art to form a flat display panel.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al, US 20160141378 A1, in view of Lin and Ogino and further in view of Kawasaki et al, JP H07211651 A Yang teaches:
18. A method of providing a display device, the method comprising: providing a thin film transistor (figure 2) including: an active layer (para 005, not shown figure 2), a gate electrode (124) on the active layer,
an electrode layer (173, 175) and
the electrode layer including a source electrode (173q) and a drain electrode (175q); and
providing a first passivation layer (180a) on the thin film transistor, the first passivation layer having a second stress,
Yang fails to teach:
an electrode layer having a first stress greater than about-0 MPa and less than
200 MPa, and
wherein the providing of the first passivation layer includes:
injecting silane gas and ammonia gas, on the source electrode and the drain electrode; and
defining a difference between an absolute value of the first stress and an absolute value of the second stress of about 600 megapascals or less.
Lin teaches:
The formation of the first conductive layer 212, the second conductive layer 214, and the third conductive layer 216 provides stress control to withstand further processing of the manufacture of the wafer structure 300. The stack formed by the first conductive layer 212, the second conductive layer 214, and the third conductive layer 216 has a tensile stress in the range of 100 to 600 MPa with a typical value about 300 MPa. (para 043)
Ogino teaches:
it is preferable to make the internal stress to the whole passivation layer 18 into the range of -50 MPa (compression stress) to +50 MPa (tensile stress). This is because, as a whole, the stack is not biased against internal stress, and furthermore, no point defect is generated in the passivation layer 18. More specifically, among the layers constituting the passivation layer 18, it is preferable to set the internal stress of the compressive stress layer in the range of -150 MPa to -50 MPa from the viewpoint of suppressing warpage of the substrate. Similarly, in the layers constituting the passivation layer 18, it is preferable to set the internal stress of the tensile stress layer in the range of +50 MPa to +150 MPa from the viewpoint of suppressing the warpage of the substrate and the suppression of cracking in the passivation layer. (machine translation)
Therefore, combining the teachings of Lin and Ogino, one of ordinary skill would be able to determine a difference between an absolute value of the first stress and an absolute value of the second stress is about 600 megapascals or less.
Kawasaki teaches:
FIG. 10 shows a schematic sectional view of the reaction chamber of
the plasma CVD apparatus used for forming the TFT element. Further: For a
silicon nitride layer, silane (SiH4) gas and ammonia (NH3) gas are main materials, and
nitrogen (N2) gas or hydrogen (H) is used as a carrier gas.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park, with the primary reference of Kawasaki, because it is convention in the art to form silicon nitride films by decomposing silane and ammonia in a CVD chamber to create a plasma.
Yang and Kawasaki further:
19. The method of claim 18, further comprising after the providing of the first passivation layer, providing a second passivation layer (180b) on the first passivation layer (180a), (see discussion of Yang)
wherein the providing of the second passivation layer includes injecting hydrogen gas in addition to the silane gas and the ammonia gas, on the source electrode and the drain electrode. (see above discussion of Kawasaki)
Yang further teaches:
20. The method of claim 18, further comprising after the providing of the source electrode (173q) and the drain electrode (173q), providing a capping film (173r and 175r) including a metal or a metal oxide, on the source electrode and the drain electrode.
Allowable Subject Matter
Claims 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art references fail to teach:
15. The display device of claim 11, wherein each of the source electrode and the drain electrode further includes:
a capping film including a metal or a metal oxide, and
the capping film between the second conductive layer and the third conductive layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
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